JP2008010449A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve manufacturing yield of a semiconductor device for which a WPP (wafer process package) technique is used. <P>SOLUTION: A conductive film 12 to be arranged between a re-wiring 9 and a bump electrode is formed by a non-electrolytic plating method in a condition where an Al wiring 2 of a plating power feeding region 52 is not exposed on the external peripheral portion of a semiconductor wafer. Exposure conditions where an opening 4 is formed on an insulating film 3 on the Al wiring 2 of a product acquiring region 51 are controlled by a photolithographic technique and an etching technique, so that the opening is not formed on the insulating film 3 on the Al wiring 2 of the plating power feeding region 52. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly, to a semiconductor device manufacturing method using a wafer process package (WPP) technique.

  In the WPP technology, a wafer process (pre-process) and a package process (post-process) are integrated, and a package process is performed on a plurality of semiconductor chips in the same state as a semiconductor wafer. According to this WPP technology, the number of steps can be greatly reduced as compared with a method of processing a package process for each semiconductor chip cut from a semiconductor wafer after the wafer process.

Japanese Unexamined Patent Publication No. 2000-349189 (Patent Document 1) discloses a step coverage of rewiring in a connection hole connecting an external terminal (bump electrode) and rewiring in a packaging process of a semiconductor device using WPP technology. Techniques for improving are disclosed.
JP 2000-349189 A

  A semiconductor device using the WPP technology in which the wafer process and the package process studied by the present inventors are integrated is manufactured through the following steps.

  In the wafer process, a semiconductor element such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on the main surface of a semiconductor wafer, and then a multilayer wiring (wiring layer) is formed on the semiconductor element. This wiring layer can be formed by forming a groove in the interlayer insulating film and then embedding a conductor film in the groove.

  In the package process, first, an Al wiring is formed on the semiconductor element, and then an insulating film in which, for example, a silicon oxide film and a silicon nitride film are stacked so as to cover the Al wiring. Next, a first opening is formed in the insulating film, and the Al wiring is exposed. This exposed Al wiring becomes an electrode pad. Next, a first polyimide film is formed on the insulating film so as to fill the first opening. A second opening is formed in the first polyimide film so as to expose the electrode pad, and a first conductor film in which, for example, a titanium nitride film and a copper film are laminated so as to cover the exposed electrode pad is formed. Next, after forming a rewiring in which, for example, a copper film and a nickel film are laminated on the first conductor film so as to fill the second opening by electrolytic plating, the first conductor film not covered with the rewiring is removed. . Next, after forming a second polyimide film so as to cover the rewiring, a third opening is formed in the second polyimide film to expose the rewiring. Next, after forming a second conductor film made of, for example, a gold film on the rewiring exposed by the electroless plating method, a bump electrode (external terminal) is formed on the second conductor film.

  FIG. 18 is a result of defect inspection of bump electrode formation in the semiconductor device examined by the present inventors. In the figure, the bump electrodes formed on the main surface of the semiconductor wafer 1W are hatched if they have defective bump electrode formation (for example, defects). From the inspection results, in the semiconductor device examined by the present inventors, a large number of defective formations of the bump electrodes have occurred, particularly in the outer peripheral portion of the semiconductor wafer 1W. Such defective formation of the bump electrode reduces the manufacturing yield of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device using the WPP technique.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the present invention, when a conductive film made of a gold film disposed between a rewiring and a bump electrode is formed by an electroless plating method, the Al wiring in the plating power feeding region on the outer periphery of the semiconductor wafer is not exposed. Is. The exposure conditions for forming the opening in the insulating film on the Al wiring in the product acquisition region are adjusted by the photolithography technique and the etching technique, and the opening is not formed in the insulating film on the Al wiring in the plating power supply region.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, the manufacturing yield of semiconductor devices using WPP technology can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
A method of manufacturing a semiconductor device using WPP technology according to an embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 1, a semiconductor wafer (disk-shaped semiconductor) 1W made of a semiconductor such as p-type single crystal silicon is prepared. In the planar region of the semiconductor wafer, a first region 51 (hereinafter referred to as “product acquisition region”) in which a semiconductor element such as MISFET is formed, and a second region 52 for supplying power when forming a rewiring by electrolytic plating. (Hereinafter referred to as “plating power supply region”). The product acquisition region 51 is a central region of the semiconductor wafer 1W, and is, for example, a region separated by 5.0 mm or more from the edge of the semiconductor wafer 1W. The plating power supply region 52 is a region surrounding the product acquisition region 51 and is also a region of the outer peripheral portion of the semiconductor wafer, for example, a region of 5.0 mm or less from the edge of the semiconductor wafer.

  Subsequently, a semiconductor element is formed on the main surface (element formation surface) of the semiconductor wafer 1W by a well-known manufacturing technique. FIG. 2 shows an n-channel MISFET (Q1) and a p-channel MISFET (Q2) constituting, for example, a high-speed SRAM or a logic circuit as semiconductor elements. These MISFETs will be described below.

  An element isolation region 21 having an STI (Shallow Trench Isolation) structure, for example, is formed on the main surface of the semiconductor substrate 1 (a part of the semiconductor wafer 1W), and the active region is isolated by the element isolation region 21. In this active region, a p-type well 22 and an n-type well 23 are formed, and an n-channel MISFET (Q1) and a p-channel MISFET (Q2) are formed respectively.

  The configuration of this n-channel type MISFET (Q1) is as follows. The p-type well 22 is a semiconductor region into which a p-type impurity such as boron (B) is introduced. A gate insulating film 24 is formed on the p-type well 22, and a gate electrode 25 a is formed on the gate insulating film 24. The gate insulating film 24 is formed of, for example, a silicon oxide film, but may be formed of a high dielectric film having a dielectric constant higher than that of the silicon oxide film. The gate electrode 25a is formed of, for example, a polysilicon film, and an n-type impurity is introduced into the polysilicon film, for example. This is performed in order to lower the threshold voltage of the n-channel type MISFET (Q1). Sidewalls 26 are formed on the side walls on both sides of the gate electrode 25a, and low-concentration n-type impurity diffusion regions 27a are formed in the p-type well 22 below the sidewalls 26. A high-concentration n-type impurity diffusion region 28a is formed outside the low-concentration n-type impurity diffusion region 27a. The low-concentration n-type impurity diffusion region 27a and the high-concentration n-type impurity diffusion region 28a are semiconductor regions into which an n-type impurity is introduced, and are higher in concentration n-type impurity diffusion region 28a than the low-concentration n-type impurity diffusion region 27a. In this case, n-type impurities are introduced at a higher concentration. The low-concentration n-type impurity diffusion region 27a and the high-concentration n-type impurity diffusion region 28a form the source region or drain region of the n-channel MISFET (Q1). A so-called LDD (Lightly Doped Drain) structure is formed by configuring the source region or the drain region from the low-concentration n-type impurity diffusion region 27a and the high-concentration n-type impurity diffusion region 28a. Thereby, the electric field concentration under the gate electrode 25a can be relaxed.

  On the other hand, the configuration of the p-channel type MISFET (Q2) is as follows. The n-type well 23 is a semiconductor region into which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced. A gate insulating film 24 is formed on the n-type well 23, and a gate electrode 25 b is formed on the gate insulating film 24. The gate electrode 25b is formed of, for example, a polysilicon film, and a p-type impurity is introduced. Thus, in the p-channel type MISFET (Q2), the threshold voltage can be lowered by introducing the p-type impurity into the gate electrode 25b. In the first embodiment, an n-type impurity is introduced into the gate electrode 25a of the n-channel MISFET (Q1), while a p-type impurity is introduced into the gate electrode 25b of the p-channel MISFET (Q2). For this reason, the threshold voltage can be lowered in both the n-channel type MISFET (Q1) and the p-channel type MISFET (Q2). Side walls 26 are formed on the side walls on both sides of the gate electrode 25b, and a low-concentration p-type impurity diffusion region 27b is formed in the n-type well 23 below the side walls 26. A high-concentration p-type impurity diffusion region 28b is formed outside the low-concentration p-type impurity diffusion region 27b. The low-concentration p-type impurity diffusion region 27b and the high-concentration p-type impurity diffusion region 28b are semiconductor regions into which p-type impurities are introduced, and are higher in concentration than the low-concentration p-type impurity diffusion region 27b. In this case, p-type impurities are introduced at a higher concentration. The low-concentration p-type impurity diffusion region 27b and the high-concentration p-type impurity diffusion region 28b form the source region or drain region of the p-channel MISFET (Q2). A so-called LDD (Lightly Doped Drain) structure is formed by forming the source region or the drain region from the low concentration p-type impurity diffusion region 27b and the high concentration p-type impurity diffusion region 28b.

  Subsequently, a multilayer wiring (wiring layer) is formed on the n-channel MISFET (Q1) and the p-channel MISFET (Q2) by a well-known manufacturing technique. This wiring layer will be described below. On the n-channel MISFET (Q1) and the p-channel MISFET (Q2) formed on the semiconductor substrate 1, a silicon oxide film 29 serving as an interlayer insulating film is formed. The silicon oxide film 29 is formed with plugs 30 reaching the source region and the drain region of the n-channel MISFET (Q1) or the p-channel MISFET (Q2). The plug 30 is formed of, for example, a laminated film of a titanium nitride film and a tungsten film serving as a barrier metal film. Next, a silicon oxide film 31 serving as an interlayer insulating film is formed on the silicon oxide film 29 on which the plug 30 is formed, and a tungsten wiring 32 is formed so as to be embedded in the silicon oxide film 31. The tungsten wiring 32 is electrically connected to the plug 30 formed in the lower layer. Subsequently, a silicon oxide film 33 is formed on the tungsten wiring 32, and a plug 34 is formed so as to be embedded in the silicon oxide film 33. Similar to the plug 30, the plug 34 is composed of a laminated film of a barrier metal film and a tungsten film. The plug 34 is electrically connected to the tungsten wiring 32 formed in the lower layer.

  On the silicon oxide film 33 on which the plug 34 is formed, a silicon oxide film 35 serving as an interlayer insulating film is formed, and a first wiring layer 36 is formed so as to be embedded in the silicon oxide film 35. The first wiring layer 36 is composed of, for example, a laminated film of a barrier metal film and a copper film for preventing copper diffusion. A silicon nitride film 37a for preventing copper diffusion is formed on the first wiring layer 36, and a silicon oxide film 37b is formed on the silicon nitride film 37a. A silicon nitride film 38a and a silicon oxide film 38b are stacked on the silicon oxide film 37b, and a second wiring layer 39 is formed so as to be embedded in the silicon nitride film 38a and the silicon oxide film 38b. Similar to the first wiring layer 36, the second wiring layer 39 is formed of, for example, a laminated film of a barrier metal film and a copper film, and is electrically connected to the lower first wiring layer 36. Similarly, a third wiring layer 40 and a plug 41 are formed on the second wiring layer 39. The third wiring layer 40 and the plug 41 are formed of, for example, a laminated film of a barrier metal film and a copper film. An uppermost wiring layer (fourth wiring layer) 43 is formed so as to be embedded in the interlayer insulating film. The uppermost wiring layer 43 is formed of a laminated film of a barrier metal film and a copper film, for example, like other copper wirings.

  The conventional semiconductor element forming step and wiring layer forming step are so-called wafer processes. After this wafer process, a so-called package process is performed in a process as shown in FIG. Specifically, after the wafer process, an Al wiring process (ALP process), a pad forming process (PAD process), a polyimide forming process (PI process), a rewiring forming process (WM process), a polyimide forming process (WPI process), The package process is performed in the order of the Au plating step and the bump electrode formation step.

  First, in the Al wiring forming step, as shown in FIG. 3, the uppermost wiring layer 43 (FIG. 2) of the wiring layer is formed on the semiconductor element and the multilayer wiring layer (not shown) formed on the main surface of the semiconductor substrate 1. The Al wiring 2 electrically connected to the reference is formed. The Al wiring 2 is formed on the main surface of the semiconductor substrate 1 using a sputtering technique in the order of a barrier metal film 2a, an aluminum film 2b, and a barrier metal film 2c, and then patterned using a photolithography technique and an etching technique. Being done. As shown in FIG. 11, the exposure condition (S1) in the step of forming the Al wiring 2 (ALP step) is as shown in FIG. 11 using the positive mask to cover the entire surface of the semiconductor wafer 1W including the product acquisition region 51 and the plating power supply region 52. Exposure (entire exposure) is performed, and a peripheral region of the semiconductor wafer 1W, for example, a region from the edge of the semiconductor wafer 1W to 2.0 mm is exposed.

  The Al wiring 2 is composed of a laminated film of barrier metal films 2a, 2c and an aluminum film 2b made of, for example, a titanium nitride film. The aluminum film 2b may be made of an aluminum alloy film instead of the aluminum film as long as it is a film containing aluminum as a main component. The Al wiring 2 has a function of relaxing the stress of the polyimide film around the rewiring and the rewiring. In other words, the reliability test that repeats the temperature cycle of low temperature and high temperature causes expansion and contraction in the rewiring and the polyimide film around the rewiring. The Al wiring 2 is provided to relieve the generated stress. ing. Therefore, in addition to the product acquisition region 51 and the vicinity thereof, the Al wiring 2 is also provided in the plating power supply region 52.

  Subsequently, in the pad forming step, as shown in FIG. 4, after forming the insulating film 3 on the main surface of the semiconductor substrate 1 so as to cover the Al wiring 2, the opening 4 is formed in the insulating film 3 in the product acquisition region 51. Then, the Al wiring 2 is exposed to form an electrode pad. The insulating film 3 is formed in the order of a silicon oxide film 3a and a silicon nitride film 3b using a plasma CVD technique. The electrode pad is formed using a photolithography technique and an etching technique. As shown in FIG. 11, the exposure condition (S2) of the electrode pad forming step (PAD step) is to expose only the product acquisition region 51 using a positive mask (blade exposure), and further to the semiconductor wafer 1W. A peripheral area, for example, an area from the edge of the semiconductor wafer 1W to 2.0 mm is exposed. As described above, in the first embodiment, the product acquisition region 51 is a region separated by 5.0 mm or more from the edge of the semiconductor wafer 1W, and the plating power supply region 52 is 5.0 mm or less from the edge of the semiconductor wafer. It is an area. For this reason, in the pad formation process, the Al wiring 2 in the plating power supply region 52 is covered with the insulating film 3, and the surface of the Al wiring 2 is not exposed.

  The reason why the surface of the Al wiring 2 is not exposed in the plating power supply region 52 will be described below. As shown in FIG. 18, in the semiconductor device using the WPP technique studied by the present inventors, bump electrode formation defects (for example, defects) occurred in the outer peripheral portion of the semiconductor wafer 1W. Therefore, the present inventors have observed the outer peripheral portion of the semiconductor wafer 1W and found that the Al wiring exposed on the outer peripheral portion is corroded. For this reason, it is considered that the gold film for improving the connectivity between the bump electrode, the rewiring, and the connection is difficult to be formed. That is, in the state where the Al wiring 2 is exposed as shown in FIG. 12, when the gold film is formed by the electroless plating technique, the aluminum of the Al wiring 2 on the outer peripheral portion of the semiconductor wafer 1W is melted and melted. It is considered that aluminum is an obstacle and a gold film is not formed on the outer peripheral portion of the semiconductor wafer 1W, resulting in defective formation of bump electrodes (for example, defects). That is, it is considered that solder wettability has occurred due to a decrease in the adherence of the gold film. Therefore, the present inventors cover the Al wiring 2 in the plating power supply region 52 with the insulating film 3 so that the surface of the Al wiring 2 is not exposed. FIG. 13 shows the exposure conditions of the semiconductor device during the manufacturing process examined by the present inventors in FIG.

  Subsequently, in the polyimide forming step, as shown in FIG. 5, after forming the polyimide film 5 on the insulating film 3 so as to embed the opening 4, the opening 6 is formed in the polyimide film 5 in the product acquisition region 51. The electrode pad (Al wiring 2) is exposed and the polyimide film 5 in the plating power supply region 52 is removed. The polyimide film 5 is cured by applying the polyimide film 5 on the main surface of the semiconductor substrate 1 using a spin coating technique, patterning it using a photolithography technique, and an etching technique. As shown in FIG. 11, the exposure condition of the step of forming the polyimide film 5 (PI step) is to expose only the product acquisition region 51 (blade exposure) using a negative mask.

  Subsequently, in the rewiring forming step, the conductor film 7 is formed so as to cover the exposed electrode pad (Al wiring 2). The conductor film 7 is formed on the main surface of the semiconductor substrate 1 in this order by a titanium nitride film 7a and a copper film 7b using a sputtering technique.

  Next, as shown in FIG. 6, a photoresist film 8 patterned so as to secure a region where a rewiring is formed by an electroplating method described later is formed. The photoresist film 8 is formed using a photolithography technique and an etching technique. As shown in FIG. 11, the exposure condition (S4) of the step of forming the photoresist film 8 (WM step) is as shown in FIG. 11 using the positive mask to expose the entire surface of the semiconductor wafer 1W including the product acquisition region 51 and the plating power supply region 52. Is exposed (entire exposure), and a peripheral region of the semiconductor wafer 1W, for example, a region from the edge of the semiconductor wafer 1W to 4.0 mm is exposed.

  Next, a rewiring 9 is formed on the conductor film 7 so as to fill the opening 6. The rewiring 9 is formed on the conductor film 7 in the order of the copper film 9a and the nickel film 9b by using an electroplating technique for supplying power to the conductor film 7 in the plating power supply region 52. Note that the rewiring 9 is not formed on the conductive film 7 in the plating power supply region 52 because the region is supplied with plating power.

  Next, after removing the photoresist film 8, as shown in FIG. 7, the conductor film 7 not covered with the rewiring 9 is removed using an etching technique.

  Subsequently, in the polyimide forming step, as shown in FIG. 8, after forming the polyimide film 10 so as to cover the rewiring 9, the opening 11 is formed in the polyimide film 10 in the product acquisition region 51, and the rewiring 9 is formed. While being exposed, a part of the polyimide film 10 in the plating power supply region 52 is removed. The polyimide film 10 is cured by applying the polyimide film 10 onto the main surface of the semiconductor substrate 1 using a spin coating technique, patterning it using a photolithography technique, and an etching technique. As shown in FIG. 11, the exposure conditions (S5) of the step of forming the polyimide film 10 (WPI step) are as follows. The negative surface mask is used to expose the entire surface of the semiconductor wafer 1W including the product acquisition region 51 and the plating power supply region 52 as shown in FIG. Exposure (entire exposure) is performed, and a peripheral region of the semiconductor wafer 1W, for example, a region from the edge of the semiconductor wafer 1W to 2.6 mm is exposed.

  Next, in the Au plating step, a conductor film 12 made of, for example, a gold film is formed on the rewiring 9 exposed using an electroless plating technique. At this time, the conductor film 12 is formed by the electroless plating technique in a state where the Al wiring 2 is not exposed in the plating power supply region 52. Therefore, the aluminum of the Al wiring 2 is prevented from melting during electroless plating when forming the gold film, and the growth of the gold film in the product acquisition region 51 on the outer peripheral side of the semiconductor wafer 1W is inhibited. The conductor film 12 made of a gold film can be formed.

  Subsequently, in the bump electrode forming step, as shown in FIG. 9, a hemispherical bump electrode 13 is formed on the conductor film 12. The bump electrode 13 is formed, for example, by printing a solder paste on the conductor film 12 using a solder printing technique, and heating the semiconductor substrate 1 to reflow (melt and recrystallize) the solder paste. The bump electrode 56 is made of lead (Pb) -free solder made of, for example, tin (Sn), silver (Ag), and copper (Cu).

  As described above, the method of manufacturing the semiconductor device according to the first embodiment includes forming a conductive film 12 made of a gold film disposed between the rewiring 9 and the bump electrode 12 by an electroless plating method. This is performed in a state where the Al wiring 2 in the plating power feeding region 52 on the outer peripheral portion of 1 W is not exposed. Specifically, the exposure conditions for forming the opening 4 in the insulating film 3 on the Al wiring 2 in the product acquisition region 51 are adjusted by the photolithography technique and the etching technique to adjust the exposure condition on the Al wiring 2 in the plating power supply region 52. No opening is formed in the insulating film 3. Thereby, the manufacturing yield of the semiconductor device using the WPP technology can be improved.

(Embodiment 2)
In the first embodiment, when forming a conductive film made of a gold film disposed between the rewiring and the bump electrode by the electroless plating method, an opening is formed in the insulating film on the Al wiring in the plating power supply region. I went without doing it. In the second embodiment, the polyimide film is used without exposing the Al wiring in the plating power feeding region. The description of the same steps as those in the first embodiment is omitted.

  FIG. 15 shows exposure conditions for the package process shown in the second embodiment. Only the exposure conditions (S5) of the polyimide forming step are different from the exposure conditions (FIG. 13) of the package process studied by the present inventors. In the second embodiment, in the polyimide forming step, as shown in FIG. 14, after forming the polyimide film 10 so as to cover the rewiring 9, the opening 11 is formed in the polyimide film 10 in the product acquisition region 51, The rewiring 9 is exposed. At this time, the polyimide film 10 in the plating power supply region 52 is not removed. The polyimide film 10 is cured by applying the polyimide film 10 onto the main surface of the semiconductor substrate 1 using a spin coating technique, patterning it using a photolithography technique, and an etching technique. As shown in FIG. 15, the exposure conditions (S5) of the step of forming the polyimide film 10 (WPI step) are as follows. The negative surface mask is used to expose the entire surface of the semiconductor wafer 1W including the product acquisition region 51 and the plating power supply region 52. Exposure (entire exposure) is performed, and a peripheral region of the semiconductor wafer 1W, for example, a region wider than 5.0 mm from the edge of the semiconductor wafer 1W is exposed.

  As described above, the method of manufacturing the semiconductor device according to the second embodiment includes the step of forming a conductive film 12 made of a gold film disposed between the rewiring 9 and the bump electrode 13 by an electroless plating method. This is performed in a state where the Al wiring 2 in the plating power feeding region 52 on the outer peripheral portion of 1 W is not exposed. Specifically, the exposure condition of the polyimide film 10 is adjusted so that the Al wiring 2 in the plating power supply region 52 is not exposed by the polyimide film 10. Thereby, the manufacturing yield of the semiconductor device using the WPP technology can be improved.

(Embodiment 3)
In the first embodiment, when forming a conductive film made of a gold film disposed between the rewiring and the bump electrode by the electroless plating method, an opening is formed in the insulating film on the Al wiring in the plating power supply region. I went without doing it. In the third embodiment, it is performed in a state where no Al wiring is formed in the plating power supply region. The description of the same steps as those in the first embodiment is omitted.

  FIG. 17 shows exposure conditions for the package process shown in the third embodiment. Only the exposure condition (S1) of the Al wiring forming step is different from the exposure condition (FIG. 13) of the package process investigated by the present inventors. In the third embodiment, in the Al wiring formation step, as shown in FIG. 16, the uppermost wiring of the wiring layer is formed on the semiconductor element and the multilayer wiring layer (not shown) formed on the main surface of the semiconductor substrate 1. An Al wiring 2 electrically connected to the layer 43 (see FIG. 2) is formed. The Al wiring 2 is formed on the main surface of the semiconductor substrate 1 using a sputtering technique in the order of a barrier metal film 2a, an aluminum film 2b, and a barrier metal film 2c, and then patterned using a photolithography technique and an etching technique. Being done. As shown in FIG. 17, the exposure condition (S1) of the step of forming the Al wiring 2 (ALP step) is as shown in FIG. 17 using the positive mask to cover the entire surface of the semiconductor wafer 1W including the product acquisition region 51 and the plating power supply region 52. Exposure (entire exposure) is performed, and a peripheral region of the semiconductor wafer 1W, for example, a region wider than 5.0 mm from the edge of the semiconductor wafer 1W is exposed.

  As described above, the method for manufacturing a semiconductor device according to the third embodiment includes the step of forming a conductive film 12 made of a gold film disposed between the rewiring 9 and the bump electrode 13 by an electroless plating method. This is performed in a state where the Al wiring 2 in the plating power feeding region 52 on the outer peripheral portion of 1 W is not exposed. Specifically, the Al wiring 2 is not formed in the plating power supply region 52 by adjusting the exposure conditions of the Al wiring 2. Thereby, the manufacturing yield of the semiconductor device using the WPP technology can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the case where the uppermost wiring layer is made of aluminum has been described. However, the present invention can also be applied to the case where aluminum is the main component.

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor devices.

1 is a plan view schematically showing a semiconductor wafer according to the present invention. It is principal part sectional drawing which shows typically the semiconductor element which concerns on this invention. FIG. 6 is a main-portion cross-sectional view schematically showing the semiconductor device during the manufacturing process according to the first embodiment. FIG. 4 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 3; FIG. 5 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 4; FIG. 6 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 5; FIG. 7 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 6; FIG. 8 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 7; FIG. 9 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 8; It is a flowchart of the packaging process of the semiconductor device which concerns on this invention. This is an exposure condition of the package process according to the first embodiment. It is principal part sectional drawing which shows typically the semiconductor device in the manufacturing process which the present inventors examined. It is the exposure condition of the package process investigated by the present inventors. FIG. 10 is a main-portion cross-sectional view schematically showing the semiconductor device in the manufacturing process according to the second embodiment. This is the exposure condition of the package process according to the second embodiment. It is principal part sectional drawing which shows typically the semiconductor device in the manufacturing process which concerns on this Embodiment 3. FIG. It is an exposure condition of the package process according to the third embodiment. It is a bump electrode test result of the semiconductor device examined by the present inventors.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1W Semiconductor wafer 2 Al wiring 2a Barrier metal film 2b Aluminum film 2c Barrier metal film 3 Insulating film 3a Silicon oxide film 3b Silicon nitride film 4 Opening part 5 Polyimide film 6 Opening part 7 Conductive film 8 Photoresist film 9 Rewiring 9a Copper film 9b Nickel film 10 Polyimide film 11 Opening portion 12 Conductor film 13 Bump electrode 21 Element isolation region 22 P-type well 23 N-type well 24 Gate insulating film 25a Gate electrode 25b Gate electrode 26 Side wall 27a Low-concentration n-type impurity diffusion Region 27b Low-concentration p-type impurity diffusion region 28a High-concentration n-type impurity diffusion region 28b High-concentration p-type impurity diffusion region 29 Silicon oxide film 30 Plug 31 Silicon oxide film 32 Tungsten wiring 33 Silicon oxide film 34 Plug 35 Silicon oxide film 36 1 wiring layer 37a nitriding Silicon film 37b of silicon oxide film 38a of silicon nitride film 38b of silicon oxide film 39 second wiring layer 40 third wiring layer 41 plug 43 uppermost wiring layer (fourth wiring layer)
51 Product acquisition area (first area)
52 Plating feeding area (second area)
Q1 n-channel MISFET
Q2 p-channel MISFET

Claims (5)

(A) preparing a semiconductor wafer having a first region in which a semiconductor element is formed;
(B) forming the semiconductor element on the main surface of the semiconductor wafer;
(C) forming a first wiring on the semiconductor element;
(D) forming an insulating film so as to cover the first wiring;
(E) forming a first opening in the insulating film and exposing the first wiring;
(F) forming a first polyimide film on the insulating film so as to fill the first opening;
(G) forming a second opening in the first polyimide film and exposing the first wiring;
(H) after the step (g), a step of forming a first conductor film so as to cover the exposed first wiring;
(I) surrounding the first region and using the second region on the outer periphery of the semiconductor wafer as a power feeding region, the second opening is formed by an electrolytic plating method for feeding power to the first conductor film formed in the second region. Forming a second wiring on the first conductive film so as to embed
(J) removing the first conductor film not covered with the second wiring;
(K) forming a second polyimide film so as to cover the second wiring;
(L) forming a third opening in the second polyimide film and exposing the second wiring;
(M) forming a second conductor film on the second wiring exposed by the electroless plating method;
A method of manufacturing a semiconductor device having
In the step (c), the first wiring is formed in the second region, and in the step (d), the insulating film is formed so as to cover the first wiring in the second region,
The method of manufacturing a semiconductor device, wherein the step (m) is performed in the second region in a state where the first wiring is not exposed.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first wiring is mainly composed of aluminum.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the second conductor film is made of gold. (A) preparing a semiconductor wafer having a first region in which a semiconductor element is formed;
(B) forming the semiconductor element on the main surface of the semiconductor wafer;
(C) forming a first wiring on the semiconductor element;
(D) forming an insulating film so as to cover the first wiring;
(E) forming a first opening in the insulating film and exposing the first wiring;
(F) forming a first polyimide film on the insulating film so as to fill the first opening;
(G) forming a second opening in the first polyimide film and exposing the first wiring;
(H) after the step (g), a step of forming a first conductor film so as to cover the exposed first wiring;
(I) surrounding the first region and using the second region on the outer periphery of the semiconductor wafer as a power feeding region, the second opening is formed by an electrolytic plating method for feeding power to the first conductor film formed in the second region. Forming a second wiring on the first conductive film so as to embed
(J) removing the first conductor film not covered with the second wiring;
(K) forming a second polyimide film so as to cover the second wiring;
(L) forming a third opening in the second polyimide film and exposing the second wiring;
(M) forming a second conductor film on the second wiring exposed by the electroless plating method;
A method of manufacturing a semiconductor device having
In the step (c), the uppermost wiring layer is formed in the second region, and in the step (l), the second polyimide film is formed so as to cover the first wiring in the second region,
The method of manufacturing a semiconductor device, wherein the step (m) is performed in the second region in a state where the first wiring is not exposed. (A) preparing a semiconductor wafer having a first region in which a semiconductor element is formed;
(B) forming the semiconductor element on the main surface of the semiconductor wafer;
(C) forming a first wiring on the semiconductor element;
(D) forming an insulating film so as to cover the first wiring;
(E) forming a first opening in the insulating film and exposing the first wiring;
(F) forming a first polyimide film on the insulating film so as to fill the first opening;
(G) forming a second opening in the first polyimide film and exposing the first wiring;
(H) after the step (g), a step of forming a first conductor film so as to cover the exposed first wiring;
(I) surrounding the first region and using the second region on the outer periphery of the semiconductor wafer as a power feeding region, the second opening is formed by an electrolytic plating method for feeding power to the first conductor film formed in the second region. Forming a second wiring on the first conductive film so as to embed
(J) removing the first conductor film not covered with the second wiring;
(K) forming a second polyimide film so as to cover the second wiring;
(L) forming a third opening in the second polyimide film and exposing the second wiring;
(M) forming a second conductor film on the second wiring exposed by the electroless plating method;
A method of manufacturing a semiconductor device having
In the step (c), the first wiring is not formed in the second region,
The method of manufacturing a semiconductor device, wherein the step (m) is performed in the second region without the first wiring.

Images