JP2008016514A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology that can improve the connection strength between a solder bump electrode and an UBM. <P>SOLUTION: An UBM (electrode layer) 17, wherein a second metal film 16 is stacked on a first metallic film 15 is connected on the upper surface of a bonding pad M6a, an Au seed layer is selectively formed on the upper surface and the side surface of the second metal film 16, and then a solder pattern is formed to be connected with the Au seed layer on the upper surface of the UBM 17. The solder pattern is heated to be made to react with the Au seed layer, thereby forming a solder bump 20 which is to be connected with the upper surface and the side surface of the second metal film 16. Thus, the connection part between the solder bump 20 and the UBM 17 is made to have an anchor shape. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique and a semiconductor device, and more particularly to a technique that is effective when applied to the manufacture of a surface mount element having solder bump electrodes.

  For example, after forming a metal adhesion / barrier / electrolytic plating bath layer on at least the bonding pad, a resist layer is formed on the bonding pad in a predetermined pattern defining an opening, and a solder wettable layer is formed in the opening. Forming and removing a part of the resist from the opening area to form a gap between the edge of the solder wettable metal layer and the resist, and the solder wettability on the solder wettable metal layer including the gap A technique for forming a barrier metal layer for sealing the metal layer is disclosed (see Patent Document 1).

  Also, it has a terminal part for soldering the ball, a support part disposed in the vicinity of the outer peripheral part of the terminal part, and a connecting part that connects the terminal part and the support part, and the entire terminal part is exposed. A technique is disclosed in which an insulating layer is provided so as to cover the support portion in a state, and solder is soldered to the terminal portion in a state where the solder straddles the surface of the terminal portion and the edge portion (see Patent Document 2).

  A rewiring layer electrically connected to the pad through an opening formed in the passivation film; and a barrier metal layer that completely covers the rewiring layer and has an overhanging portion projecting on the passivation film; Discloses a semiconductor device including an organic film having an opening reaching the barrier metal layer and a bump electrode electrically connected to the rewiring layer through the opening and the barrier metal layer (Patent Document 3). reference).

  Further, an extended portion having a shape extending in the direction of the center of gravity with respect to the distribution of the solder bump electrode group or in the opposite direction is formed on at least one of the plurality of electrode pads on which the solder bump electrodes are formed. An electrode structure of a surface mount device is disclosed (see Patent Document 4).

  In addition, an insulating film covering the bonding pad, an opening formed in the insulating film to expose the bonding pad, and a bump electrode connected to the bonding pad in the opening are provided. An electronic component having a portion whose area is smaller than the opening area of the upper portion is disclosed (see Patent Document 5).

  In addition, the protective film is formed of two or more layers, the opening of the lower protective film is formed larger than the opening of the upper protective film, and the connection terminal in which the bottom of the protruding electrode enters under the upper protective film It is disclosed (see Patent Document 6).

Further, the first protruding electrode portion formed on the electrode pad and the second protruding electrode portion formed at the tip of the first protruding electrode portion, the tip of the second protruding electrode portion and the electrode A substantially drum-shaped protruding electrode having a constricted portion between the pad-side end portion is disclosed (see Patent Document 7).
JP 2003-7755 A (paragraphs [0018] to [0023], FIGS. 1 and 2) JP 2003-243813 A (paragraphs [0016] to [0023], FIGS. 1 to 4) JP 2000-306938 A (paragraphs [0023] to [0025], FIG. 2) JP 10-284500 A (paragraphs [0015] to [0022], FIG. 1 and FIG. 2) JP 2000-195887 (paragraph [0018], paragraph [0031], paragraph [0042], FIG. 1, FIG. 8, FIG. 15) JP 2003-324120 A (paragraphs [0050] to [0052], FIG. 1) Japanese Patent Laid-Open No. 11-251472 (paragraphs [0020] to [0023], FIG. 1)

  Surface mount technology using ball grid array (BGA) was developed in the mid-1990s due to demands for high-speed and high-density mounting of semiconductor products. Currently, it is the same as a semiconductor chip manufactured in a wafer state. Development of a size package, that is, a wafer level CSP (Chip Size Package) is being carried out by various companies. The wafer level CSP is a technology in which a wafer process (pre-process) and a package process (post-process) are integrated, and the size of the package is reduced as the size of the semiconductor chip is reduced. As the number of chips increases, the cost of semiconductor products can be reduced.

  By the way, in the FC (Flip Chip) -BGA connection in the wafer level CSP, the bump electrode is electrically connected to the lead electrode which is the uppermost layer wiring of the semiconductor device, but between the lead electrode and the bump electrode, A UBM (Under Bump Metal) for preventing mutual diffusion is formed. Solder is generally used for the bump electrode, and Ni film is generally used for the UBM in consideration of the function of preventing mutual diffusion, versatility, cost, and the like. In addition, since a low electrical resistance cannot be obtained only with the Ni film, for example, a laminated film in which a Cu film, a Cr film, a TiN film or the like is formed under the Ni film may be used.

  However, even if an Au seed layer having good solder wettability is formed on the upper surface of the UBM, a strong connection strength between the solder bump electrode and the UBM cannot be obtained, and the solder bump electrode may be peeled off. For this reason, the solder bump electrode and the UBM are sealed with an underfill to prevent the solder bump electrode from being peeled off, but there is a problem that the cost is increased.

  An object of the present invention is to provide a technique capable of improving the connection strength between a solder bump electrode and a UBM.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the method of manufacturing a semiconductor device according to the present invention, an electrode layer formed by laminating a second metal film on a first metal film is formed by being connected to the upper surface of the bonding pad portion to constitute an upper layer of the electrode layer. A metal seed layer is selectively formed on the upper surface and side surfaces of the second metal film, a solder pattern connected to the metal seed layer on the upper surface of the electrode layer is formed, and then heat treatment is performed to form the solder pattern and the metal seed layer. It is made to react and the solder bump electrode connected with the upper surface and side surface of the 2nd metal film which comprises the upper layer of an electrode layer is formed.

  Also, in the method of manufacturing a semiconductor device according to the present invention, a rewiring layer formed by laminating a second metal film on a first metal film is formed by connecting to the upper surface of the bonding pad portion. A metal seed layer is selectively formed on the upper surface and side surface of the second metal film in the vicinity of the end away from the bonding pad portion, and a solder pattern connected to the metal seed layer on the upper surface of the redistribution layer is formed, followed by heat treatment And reacting the solder pattern with the metal seed layer to connect the upper surface and the side surface of the second metal film constituting the upper layer of the rewiring layer in the vicinity of the end away from the bonding pad portion of the rewiring layer A bump electrode is formed.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming an electrode layer formed by laminating a second metal film on a first metal film; connecting the upper surface of the bonding pad portion; A metal seed layer is selectively formed on the upper surface and side surfaces of the second metal film to be formed, and a solder pattern connected to the metal seed layer on the upper surface of the electrode layer is formed, and then heat treatment is performed, so that the solder pattern and the metal seed layer are formed. To form a preliminary solder bump electrode connected to the upper surface and the side surface of the second metal film constituting the upper layer of the electrode layer, and further to form a solder bump electrode connected to the preliminary solder bump.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming an electrode layer formed by laminating a second metal film on a first metal film; connecting the upper surface of the bonding pad portion; A metal seed layer is selectively formed on the upper and side surfaces of the second metal film constituting the taper, and the lower opening area is smaller than the upper opening area around the second metal film constituting the upper layer of the electrode layer. After forming an insulating film having a shape-shaped opening and forming a solder pattern connected to the metal seed layer on the upper surface of the electrode layer, heat treatment is performed to cause the solder pattern and the metal seed layer to react to form an upper layer of the electrode layer The solder bump electrode connected to the upper surface and the side surface of the second metal film that constitutes is formed.

  The semiconductor device according to the present invention is connected to the bonding pad portion through the insulating film covering the bonding pad portion, the first opening portion exposing the upper surface of the bonding pad portion formed in the insulating film, and the first opening portion. And it has the electrode layer which consists of a laminated film in which the 2nd metal film was formed on the 1st metal film, and the solder bump electrode connected to the upper surface and side surface of the 2nd metal film.

  The semiconductor device according to the present invention includes an insulating film that covers the bonding pad portion, a first opening that exposes the upper surface of the bonding pad portion formed in the insulating film, and the bonding pad portion through the first opening. And a redistribution layer drawn on the insulating film, and an end portion of the redistribution layer remote from the bonding pad portion, and a laminated film in which a second metal film is formed on the first metal film. A solder bump electrode connected to the upper surface and side surface of the second metal film is provided in the vicinity.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By making the portion of the solder bump electrode connected to the UBM an anchor shape, the connection strength between the solder bump electrode and the UBM can be improved.

  In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related.

  Further, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, it is needless to say that the constituent elements (including element steps and the like) are not necessarily indispensable, unless otherwise specified and clearly considered essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In this embodiment, the term “wafer” mainly refers to a Si (Silicon) single crystal wafer, but not only to this, but also to form an SOI (Silicon On Insulator) wafer and an integrated circuit thereon. It refers to an insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A method of manufacturing a semiconductor device having a solder bump electrode connected to an electrode layer according to the first embodiment of the present invention will be described in the order of steps with reference to FIGS. FIG. 1 is a cross-sectional view of main parts of a solder bump electrode including a CMOS device and a multilayer wiring, and FIGS. 2 to 5 are cross-sectional views of main parts of only the solder bump electrode in which the CMOS device is omitted.

  First, as shown in FIG. 1, a desired semiconductor element is formed on the main surface of a semiconductor substrate (a semiconductor wafer processed into a circular thin plate) 1 made of silicon single crystal. As the semiconductor element, for example, a complementary metal oxide semiconductor (CMOS) device, a resistor element, a capacitor element, and the like are formed. In the first embodiment, a CMOS device is exemplified. A p-channel type MIS • FET (Metal Insulator Semiconductor Field Effect Transistor) constituting the CMOS device is abbreviated as pMIS, and an n-channel type MIS • FET is abbreviated as nMIS.

  After the isolation portion 2 made of an insulating film is formed in the element isolation region of the semiconductor substrate 1, a p-well 3 is formed by ion-implanting impurities showing p-type conductivity into the semiconductor substrate 1, and similarly, an n-type An n-well 4 is formed by ion-implanting impurities showing conductivity. Subsequently, the gate insulating film 5 and the gate electrodes 6n and 6p constituting the nMIS and pMIS are formed, and the sidewall 7 is formed on the side walls of the gate electrodes 6n and 6p. Subsequently, an impurity having n-type conductivity is ion-implanted into the p-well 3 on both sides of the gate electrode 6n, so that the n-type semiconductor region 8 functioning as the source / drain of the nMIS is self-assembled with respect to the gate electrode 6n and the sidewalls 7. Form consistently. Similarly, an impurity exhibiting p-type conductivity is ion-implanted into the n-well 4 on both sides of the gate electrode 6p, so that the p-type semiconductor region 9 functioning as the source / drain of pMIS is formed with respect to the gate electrode 6p and the sidewalls 7. Form in a self-aligning manner.

  Next, after forming the insulating film 10 on the semiconductor substrate 1, the insulating film 10 is processed by etching using the resist pattern as a mask to form the connection hole 11. The connection hole 11 is formed in a necessary portion such as on the n-type semiconductor region 8 or the p-type semiconductor region 9. Subsequently, a plug 12 having, for example, W (tungsten) as a main conductor is formed in the connection hole 11, and then a first layer wiring M <b> 1 connected to the plug 12 is formed. The wiring M1 is formed by, for example, a single damascene method using Cu as a main conductor. Further, the sixth-layer wiring M6 is formed from the second-layer wiring M2 in the upper layer. The wirings M2 to M5 are formed by a duel damascene method using, for example, Cu as a main conductor. The wiring M6 is formed, for example, by processing Al film deposited on the semiconductor substrate 1 by etching using Al as a main conductor and a resist pattern as a mask. The thickness of the wiring M6 is, for example, 1 μm. In the first embodiment, Al is used as the main conductor for the sixth-layer wiring M6, but Cu may be used as the main conductor. Further, although six wiring layers are provided, the number of layers is not limited to this.

  Next, a silicon nitride film 13a is formed on the sixth-layer wiring M6, and a silicon oxide film 13b is formed on the silicon nitride film 13a. These silicon nitride film 13a and silicon oxide film 13b function as a passivation film 14 that prevents moisture and impurities from entering from the outside and suppresses the transmission of α rays. Subsequently, the silicon oxide film 13b and the silicon nitride film 13a are sequentially processed by etching using the resist pattern as a mask, and the first opening C1 exposing the bonding pad portion M6a which is a part of the sixth-layer wiring M6. Form.

  Next, a resist pattern having an opening larger than the opening C1 is formed on the passivation film 14, and the first metal film 15 connected to the bonding pad part M6a through the first opening C1 is formed on the semiconductor substrate 1. Then, a second metal film 16 is formed on the first metal film 15. As the second metal film 16, in addition to functioning as a barrier metal that suppresses the diffusion of solder, the metal film has properties such as good adhesion with Au, fast solder diffusion, and good solder wettability. For example, a Ni film is used. In addition to functioning as a barrier metal that suppresses the diffusion of solder, the first metal film 15 has properties such as low contact electrical resistance and low sheet resistance, and is further compared with the second metal film 16. Metal films having properties such as poor adhesion to Au, slow diffusion of solder, poor solder wettability, such as Cu film, Ti film, TiN film, TiW film, Ta film, W film, Cr A membrane or the like is used. The thickness of the first metal film 15 is 3 μm, for example, and the thickness of the second metal film 16 is 3 μm, for example. Subsequently, the resist pattern is removed, and as shown in FIG. 2, a laminated film of the first metal film 15 and the second metal film 16 electrically connected to the bonding pad portion M6a through the first opening C1. A UBM (electrode layer) 17 is formed.

  Next, as shown in FIG. 3, an Au seed layer 18 is selectively formed on the surface (upper surface and side surface) of the second metal film 16 constituting the upper layer of the UBM 17 by electroless plating. Au is easy to grow on the second metal film (representative material, for example, Ni film) 16, but Au on the first metal film (representative material, for example, Cu film) 15. Since it is difficult to grow, the Au seed layer 18 can be selectively formed on the surface of the second metal film 16. The thickness of the Au seed layer 18 is, for example, 0.08 μm.

  Next, as shown in FIG. 4, a resin film 19, for example, a polyimide resin film, is applied on the semiconductor substrate 1, and then processed by a lithography method to be an upper surface of the UBM 17 and a region where a solder bump electrode is formed. A second opening C2 exposing the Au seed layer 18 is formed. The thickness of the resin film 19 is 5 μm, for example.

  Next, as shown in FIG. 5, the solder bump electrode 20 is formed on the upper surface of the UBM 17 through the second opening C2. The solder bump electrode 20 is an external connection electrode, and for example, lead-free solder is used. The solder bump electrode 20 can be formed by, for example, a printing method, a plating method, or a ball method. In the printing method, the solder paste is mask-printed on the UBM 17 via the Au seed layer 18, and then the solder paste is formed into a spherical shape by reflow processing and connected to the UBM 17. In the plating method, a solder layer is formed on the UBM 17 by plating through the Au seed layer 18 and then flux is applied. Subsequently, the solder layer is formed into a spherical shape by reflow treatment and flux residue removal and cleaning. Connect. In the ball method, a flux is mask-printed on the UBM 17 and then solder balls are mounted on the flux. Subsequently, the solder balls are connected to the UBM 17 by reflow treatment and flux residue removal cleaning.

  The conditions for the reflow process performed in each method for forming the solder bump electrode 20 are, for example, a temperature of 220 to 265 ° C. and a time of 30 to 50 seconds, regardless of the formation method. During this reflow process, a solder pattern (for example, a solder paste used in a printing method, a solder layer used in a plating method, a solder ball used in a ball method) is formed on an Au seed layer 18 formed on the upper surface of the second metal film 16. It reacts and also reacts with the Au seed layer 18 formed on the side surface of the second metal film 16 covered with the resin film 19, so that the solder bump electrode 20 is formed of the second metal film 16 constituting the upper layer of the UBM 17. Connect to top and side. Therefore, at the same time when the solder bump electrode 20 is formed on the UBM 17, the portion of the solder bump electrode 20 connected to the UBM 17 has an anchor shape, and for example, without using reinforcing means such as underfill, the solder bump electrode 20 and the UBM 17. Connection strength can be improved.

  Thereafter, the semiconductor wafer is cut into individual semiconductor chips to complete the semiconductor device, but the description thereof is omitted.

  As described above, according to the first embodiment, the portion of the solder bump electrode 20 connected to the UBM (electrode layer connected to the bonding pad portion M6a of the semiconductor device) 17 is formed in the anchor shape, so that the solder bump electrode 20 And the UBM 17 can be reinforced, and the connection strength can be improved.

(Embodiment 2)
A method for manufacturing a semiconductor device having a solder bump electrode connected to a rewiring layer according to the second embodiment of the present invention will be described in the order of steps with reference to cross-sectional views of main parts of the solder bump electrode shown in FIGS.

  First, in the same manner as in the first embodiment described above, a desired semiconductor element is formed on the main surface of the semiconductor substrate 1. Next, a resist pattern having an opening larger than the opening C1 is formed on the passivation film 14, the first metal film 15 and the second metal film 16 are sequentially deposited on the semiconductor substrate 1, and then the resist pattern is formed. As shown in FIG. 6, the first metal film 15 and the second metal film that are electrically connected to the bonding pad portion M6a through the first opening C1 and drawn on the passivation film 14 are removed. A UBM (rewiring layer) 21 made of 16 laminated films is formed.

  Next, as shown in FIG. 7, after the resin film 22 is applied on the semiconductor substrate 1, the second opening C2 exposing the UBM 21 in the region where the solder bump electrodes are formed is processed by lithography. Form. At this time, the region where the solder bump electrode is formed is in the vicinity of the end of the UBM 21 away from the bonding pad portion M6a, and the second opening C2 is formed so that the side surface of the UBM 21 in that region is exposed. A gap (L in the figure) between the UBM 21 and the resin film 22 is, for example, 5 μm.

  Next, as shown in FIG. 8, an Au seed layer 18 is selectively formed on the surface (upper surface and side surface) of the second metal film 16 constituting the upper layer of the exposed UBM 21 by electroless plating.

  Next, as shown in FIG. 9, the resin film 22 is removed. Subsequently, as shown in FIG. 10, a resin film 19, for example, a polyimide resin film, is applied on the semiconductor substrate 1, and then processed by a lithography method to form a region on the upper surface of the UBM 21 where the solder bump electrodes are formed. A third opening C3 that exposes the Au seed layer 18 is formed. The thickness of the resin film 19 is 5 μm, for example.

  Next, as shown in FIG. 11, the solder bump electrode 23 is formed on the upper surface of the UBM 17 through the third opening C3 by the printing method, the plating method, or the ball method, for example, in the same manner as in the first embodiment. Form. During the reflow process performed in the formation process of the solder bump electrode 23, the solder pattern (for example, solder paste used for the printing method, solder layer used for the plating method, solder ball used for the ball method) is formed on the upper surface of the second metal film 16. And the Au seed layer 18 formed on the side surface of the second metal film 16 covered with the resin film 19. It connects with the upper surface and side surface of the 2nd metal film 16 which comprises the upper layer of UBM21 through opening part C3. Accordingly, at the same time when the solder bump electrode 23 is formed on the UBM 21, the portion of the solder bump electrode 23 connected to the UBM 21 has an anchor shape, and for example, without using reinforcing means such as underfill, the solder bump electrode 23 and the UBM 21. Connection strength can be improved.

  As described above, according to the second embodiment, the solder bump electrode 23 is formed in the anchor shape by forming the portion connected to the UBM (redistribution layer connected to the bonding pad portion M6a of the semiconductor device) 21 of the solder bump electrode 23. 23 and the UBM 21 can be reinforced, and the connection strength can be improved.

(Embodiment 3)
A method of manufacturing a semiconductor device having a solder bump electrode connected to the electrode layer according to the third embodiment of the present invention will be described in the order of steps with reference to cross-sectional views of the main part of the solder bump electrode shown in FIGS.

  First, in the same manner as in the first embodiment described above, a desired semiconductor element is formed on the main surface of the semiconductor substrate 1 and then electrically connected to the bonding pad portion M6a through the first opening C1. A UBM (electrode layer) 17 composed of a laminated film of the first metal film 15 and the second metal film 16 is formed. Further, as shown in FIG. 12, an Au seed layer 18 is selectively formed on the surface (upper surface and side surface) of the second metal film 16 constituting the upper layer of the UBM 17 by electroless plating.

  Next, as shown in FIG. 13, a solder pattern is formed on the upper surface of the UBM 17 by, for example, a printing method or a plating method, and this solder pattern and the surface of the second metal film 16 constituting the upper layer of the UBM 17 (upper surface and By reacting with the Au seed layer 18 formed on the side surface, a preliminary solder bump electrode (first solder bump electrode) 24 covering the second metal film 16 is formed. A portion of the preliminary solder bump electrode 24 connected to the UBM 17 has an anchor shape.

  Next, as shown in FIG. 14, a resin film 19, for example, a polyimide resin film, is applied on the semiconductor substrate 1, and then processed by lithography to expose the upper surface of the preliminary solder bump electrode 24. Subsequently, as shown in FIG. 15, a solder bump electrode (second solder bump electrode) 25 is formed on the upper surface of the preliminary solder bump electrode 24 by, for example, a printing method, a plating method, or a ball method.

  As described above, according to the third embodiment, similarly to the first embodiment described above, the portion of the solder bump electrode 25 connected to the UBM 17 is formed in an anchor shape, thereby joining the solder bump electrode 25 and the UBM 17. The interface can be reinforced and the connection strength can be improved.

(Embodiment 4)
A method of manufacturing a semiconductor device having a solder bump electrode connected to the electrode layer according to the fourth embodiment of the present invention will be described in the order of steps with reference to cross-sectional views of the main part of the solder bump electrode shown in FIGS.

  First, in the same manner as in the first embodiment described above, a desired semiconductor element is formed on the main surface of the semiconductor substrate 1 and then electrically connected to the bonding pad portion M6a through the first opening C1. A UBM (electrode layer) 17 composed of a laminated film of the first metal film 15 and the second metal film 16 is formed. Further, as shown in FIG. 16, after a first resin film 26, for example, a polyimide resin film, is applied on the semiconductor substrate 1, the first metal film 16 is processed by a lithography method to form the upper layer of the UBM 17. Expose the surface (top and side).

  Next, as shown in FIG. 17, an Au seed layer 18 is selectively formed on the surface (upper surface and side surface) of the second metal film 16 constituting the upper layer of the UBM 17 by electroless plating.

  Next, as shown in FIG. 18, a second resin film 27, for example, a polyimide resin film is applied on the semiconductor substrate 1. Subsequently, the second resin film 27 is processed by a lithography method, and a second space having a space (for example, a structure similar to NSDM (Non Solder Mask Defined)) around the second metal film 16 constituting the upper layer of the UBM 17. And the Au seed layer 18 formed on the surface (upper surface and side surface) of the second metal film 16 constituting the upper layer of the UBM 17 is exposed. At this time, the shape of the second opening C2 is tapered so that the opening area gradually decreases from the bottom to the top.

  Next, as shown in FIG. 19, a solder bump electrode 28 is formed on the upper surface of the UBM 17 through the second opening C2 by, for example, a printing method, a plating method, or a ball method. The solder bump electrode 28 is also formed in a tapered space around the second metal film 16 constituting the upper layer of the UBM 17, and a portion of the solder bump electrode 28 connected to the UBM 17 has an anchor shape.

  Thus, according to the fourth embodiment, as in the first embodiment described above, the portion of the solder bump electrode 28 connected to the UBM 17 is formed in an anchor shape, thereby joining the solder bump electrode 28 and the UBM 17. The interface can be reinforced and the connection strength can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the solder bump electrode applied to the wafer level CSP produced in the wafer state has been described. However, the present invention also applies to the solder bump electrode formed on the interposer or the package substrate on which the semiconductor device is mounted. be able to.

  The present invention can be applied to the formation of solder bump electrodes for terminal connection in the manufacturing process of a semiconductor device.

It is principal part sectional drawing which shows the manufacturing process of the semiconductor device by Embodiment 1 of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the same portion as that of FIG. 2 of the semiconductor substrate during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the same portion as that in FIG. 2 of the semiconductor substrate during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the same portion as that in FIG. 2 of the semiconductor substrate during a manufacturing step following that of FIG. 4; It is principal part sectional drawing which shows the manufacturing process of the semiconductor device by Embodiment 2 of this invention. FIG. 7 is an essential part cross-sectional view of the same portion as that of FIG. 6 of the semiconductor substrate during a manufacturing step following that of FIG. 6; FIG. 8 is an essential part cross-sectional view of the same portion as that of FIG. 6 of the semiconductor substrate during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross-sectional view of the same portion as that of FIG. 6 of the semiconductor substrate during a manufacturing step following that of FIG. 8; FIG. 10 is an essential part cross-sectional view of the same portion as that of FIG. 6 of the semiconductor substrate during a manufacturing step following that of FIG. 9; FIG. 11 is an essential part cross-sectional view of the same portion as that of FIG. 6 of the semiconductor substrate during a manufacturing step following that of FIG. 10; It is principal part sectional drawing which shows the manufacturing process of the semiconductor device by Embodiment 3 of this invention. FIG. 13 is a fragmentary cross-sectional view of the same place as that in FIG. 12 during a manufacturing step of the semiconductor substrate following that of FIG. 12; FIG. 14 is an essential part cross-sectional view of the same portion as that of FIG. 12 of the semiconductor substrate during a manufacturing step following that of FIG. 13; FIG. 15 is an essential part cross-sectional view of the same portion as that of FIG. 12 of the semiconductor substrate during a manufacturing step following that of FIG. 14; It is principal part sectional drawing which shows the manufacturing process of the semiconductor device by Embodiment 4 of this invention. FIG. 17 is an essential part cross-sectional view of the same portion as that of FIG. 16 of the semiconductor substrate during a manufacturing step following that of FIG. 16; FIG. 18 is an essential part cross-sectional view of the same portion as that of FIG. 16 of the semiconductor substrate during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross-sectional view of the same portion as that of FIG. 16 of the semiconductor substrate during a manufacturing step following that of FIG. 18;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Separation part 3 P well 4 N well 5 Gate insulating film 6n, 6p Gate electrode 7 Side wall 8 N type semiconductor region 9 P type semiconductor region 10 Insulating film 11 Connection hole 12 Plug 13a Silicon nitride film 13b Silicon oxide film 14 Passivation film 15 First metal film 16 Second metal film 17 UBM (electrode layer)
18 Au seed layer 19 Resin film 20 Solder bump electrode 21 UBM (redistribution layer)
22 Resin film 23 Solder bump electrode 24 Preliminary solder bump electrode (first solder bump electrode)
25 Solder bump electrode (second solder bump electrode)
26 First resin film 27 Second resin film 28 Solder bump electrodes C1 to C3 Openings M1 to M6 Wiring M6a Bonding pad part

Claims (16)

(A) forming an insulating film covering the bonding pad portion on the semiconductor substrate, and then forming a first opening in the insulating film to expose the bonding pad portion;
(B) A first metal film connected to the bonding pad portion via the first opening is formed on the semiconductor substrate, and then a second metal film is formed on the first metal film. Process,
(C) An electrode composed of the first and second metal films which is sequentially processed through the second metal film and the first metal film and is connected to the bonding pad portion through the first opening. Forming a layer;
(D) a step of selectively forming a metal seed layer on the upper and side surfaces of the second metal film constituting the upper layer of the electrode layer;
(E) after forming a resin film covering the metal seed layer on the semiconductor substrate, forming a second opening in the resin film to expose the metal seed layer on the upper surface of the electrode layer;
(F) forming a solder pattern connected to the metal seed layer on the upper surface of the electrode layer through the second opening;
(G) heat treating the semiconductor substrate to cause the solder pattern and the metal seed layer to react with each other to form solder bump electrodes connected to the upper surface and side surfaces of the second metal film constituting the upper layer of the electrode layer; A method of manufacturing a semiconductor device. (A) forming an insulating film covering the bonding pad portion on the semiconductor substrate, and then forming a first opening in the insulating film to expose the bonding pad portion;
(B) A first metal film connected to the bonding pad portion via the first opening is formed on the semiconductor substrate, and then a second metal film is formed on the first metal film. Process,
(C) The second metal film and the first metal film are sequentially processed to be connected to the bonding pad portion through the first opening and to be drawn on the insulating film. And a step of forming a rewiring layer made of the second metal film,
(D) After forming a first resin film covering the redistribution layer on the semiconductor substrate, the second redistribution layer is exposed in the vicinity of the end of the redistribution layer away from the bonding pad portion. Forming the opening of the first resin film,
(E) forming a metal seed layer selectively on the top and side surfaces of the second metal film constituting the upper layer of the redistribution layer exposed from the second opening;
(F) removing the first resin film;
(G) After forming a second resin film covering the metal seed layer on the semiconductor substrate, a third opening exposing the metal seed layer on the upper surface of the redistribution layer is formed in the second resin film. Forming the step,
(H) forming a solder pattern connected to the metal seed layer on the upper surface of the redistribution layer through the third opening;
(I) A solder bump electrode which is connected to the upper surface and the side surface of the second metal film constituting the upper layer of the redistribution layer by applying heat treatment to the semiconductor substrate to react the solder pattern with the metal seed layer Forming a semiconductor device. A method for manufacturing a semiconductor device, comprising: (A) after forming an insulating film covering the bonding pad portion on the semiconductor substrate, forming an opening in the insulating film to expose the bonding pad portion;
(B) forming a second metal film on the first metal film after forming a first metal film connected to the bonding pad portion through the opening on the semiconductor substrate;
(C) The second metal film and the first metal film are sequentially processed to form an electrode layer composed of the first and second metal films connected to the bonding pad portion through the opening. And a process of
(D) a step of selectively forming a metal seed layer on the upper and side surfaces of the second metal film constituting the upper layer of the electrode layer;
(E) forming a solder pattern connected to the metal seed layer on the upper surface of the electrode layer;
(F) a first solder that heat-treats the semiconductor substrate to cause the solder pattern and the metal seed layer to react with each other and to connect with an upper surface and a side surface of the second metal film constituting the upper layer of the electrode layer; Forming bump electrodes;
(G) exposing a top surface of the first solder bump electrode after forming a resin film on the semiconductor substrate;
(H) forming a second solder bump electrode connected to the upper surface of the first solder bump electrode. (A) forming an insulating film covering the bonding pad portion on the semiconductor substrate, and then forming a first opening in the insulating film to expose the bonding pad portion;
(B) A first metal film connected to the bonding pad portion via the first opening is formed on the semiconductor substrate, and then a second metal film is formed on the first metal film. Process,
(C) An electrode composed of the first and second metal films which is sequentially processed through the second metal film and the first metal film and is connected to the bonding pad portion through the first opening. Forming a layer;
(D) after forming a first resin film covering the electrode layer on the semiconductor substrate, exposing the upper surface and side surfaces of the second metal film constituting the upper layer of the electrode layer;
(E) a step of selectively forming a metal seed layer on an upper surface and a side surface of the second metal film constituting the upper layer of the electrode layer;
(F) forming a second resin film covering the metal seed layer on the semiconductor substrate, exposing the metal seed layer, and forming a second tapered shape in which a lower opening area is smaller than an upper opening area; Forming an opening in the second resin film;
(G) forming a solder pattern connected to the metal seed layer on the upper surface of the electrode layer through the second opening;
(H) A solder bump electrode connected to an upper surface and a side surface of the second metal film constituting the upper layer of the electrode layer by reacting the solder pattern with the metal seed layer by performing a heat treatment on the semiconductor substrate. A method of manufacturing a semiconductor device.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal film is a Ni film. 6.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal film is a Cu film, a Ti film, a TiN film, a TiW film, a Ta film, a W film, or a Cr film. A method of manufacturing a semiconductor device.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the metal seed layer is an Au seed layer. 6.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the metal seed layer is formed by an electroless plating method. 6.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the metal seed layer has a thickness of 0.1 to 0.03 μm. 6.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the bonding pad portion uses Al or Cu as a main conductor. 6.   5. The method of manufacturing a semiconductor device according to claim 1, wherein a temperature of the heat treatment applied to the semiconductor substrate is 220 to 265 ° C. 6. An insulating film covering the bonding pad,
A first opening exposing an upper surface of the bonding pad portion formed in the insulating film;
An electrode layer comprising a laminated film in which a second metal film is formed on the first metal film, connected to the bonding pad part via the first opening;
A semiconductor device comprising: a solder bump electrode connected to an upper surface and a side surface of the second metal film constituting the upper layer of the electrode layer. An insulating film covering the bonding pad,
A first opening exposing an upper surface of the bonding pad portion formed in the insulating film;
A rewiring layer that is connected to the bonding pad portion through the first opening, is a laminated film in which a second metal film is formed on the first metal film, and is drawn out on the insulating film When,
A solder bump electrode connected to an upper surface and a side surface of the second metal film constituting the upper layer of the redistribution layer is provided in the vicinity of the end of the redistribution layer away from the bonding pad portion. Semiconductor device.   14. The semiconductor device according to claim 12, wherein the second metal film is a Ni film.   14. The semiconductor device according to claim 12, wherein the first metal film is a Cu film, a Ti film, a TiN film, a TiW film, a Ta film, a W film, or a Cr film.   14. The semiconductor device according to claim 12, wherein the bonding pad portion uses Al or Cu as a main conductor.

Images