JPS6112031A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6112031A JPS6112031A JP13117584A JP13117584A JPS6112031A JP S6112031 A JPS6112031 A JP S6112031A JP 13117584 A JP13117584 A JP 13117584A JP 13117584 A JP13117584 A JP 13117584A JP S6112031 A JPS6112031 A JP S6112031A
- Authority
- JP
- Japan
- Prior art keywords
- doped polysilicon
- semiconductor substrate
- substrate
- film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 63
- 229920005591 polysilicon Polymers 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005461 lubrication Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、集積回路等の半導体装置の製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing semiconductor devices such as integrated circuits.
し従来技術〕
一般に集積回路の高集積化、高速化および低消費電力化
のために祉素子間分離部分の平坦化が重要でるる。[Prior Art] In general, it is important to flatten the isolation portion between the welfare elements in order to achieve higher integration, higher speed, and lower power consumption of integrated circuits.
従来この種の平坦化は、累子間分離領域に溝上形成し、
そこに絶縁物を埋め込むことによって行なわれているが
、幅の狭い微細な溝上完全に埋めるためには十分に厚い
膜上形成しなければならず、また余分な膜を除去するた
めに大量の異方性エツチングを行なう必要がめることか
ら、工程に長時間を有するとともに制御性にも問題がめ
った。また、配線下のフィールド領域の平坦化も別工程
で行なっていたため、工程が複雑とな９、かつホトリン
グラフィによるアライメントめ制御性の限界も良好な平
坦化の妨げとなっており、これらがＬＳＩ の集積度お
よび歩留Ｖを低下させる要因となっていた。Conventionally, this type of flattening is performed by forming grooves in the interregnum separation area,
This is done by burying an insulator in that area, but in order to completely fill the narrow, fine groove, it must be formed on a sufficiently thick film, and a large amount of insulating material must be used to remove the excess film. Since it was necessary to perform directional etching, the process took a long time and problems were encountered in controllability. In addition, planarization of the field area under the wiring was done in a separate process, making the process complicated9.Also, the limitations of alignment controllability using photolithography also impede good planarization. This was a factor that lowered the degree of integration and yield V of LSI.
本発明はこのような事情に鑑みてなされたもので、その
目的は、種々のバタン幅を有する基板段差の平坦化など
が非常に簡略なプロセスで行なえる半導体装置の製造方
法を提供することにろる。The present invention has been made in view of the above circumstances, and its purpose is to provide a method for manufacturing a semiconductor device that can flatten substrate steps having various widths through a very simple process. Roru.
このようか目的を達成するために、本発明は、半導体基
板上に高濃度の不純物を含む不純物源薄［／＜タンを形
成した上にノンドープポリシリコン層を形成し、下地バ
タンの不純物をポリシリコン層に選択的に熱拡散させた
後、不純物ドープポリシリコンとノンドープポリシリコ
ンとのエツチング特性の違いを利用して、前者のみ選択
的にエツチング除去よるものでめる。In order to achieve the above object, the present invention forms a non-doped polysilicon layer on a thin impurity source containing a high concentration of impurities on a semiconductor substrate, and removes the impurities in the base layer by forming a thin layer of impurity on a semiconductor substrate. After selectively thermally diffusing the silicon layer, only the former can be selectively removed by utilizing the difference in etching characteristics between impurity-doped polysilicon and non-doped polysilicon.
ここで、予め段差を有する半導体基板を用い、上段部の
みに不純物源薄膜を形成し、かつノンドープポリシリコ
ン層を基板段差に相当する厚みに形成すれば、容易に平
坦化した構造が得られる。Here, if a semiconductor substrate having a step in advance is used, an impurity source thin film is formed only in the upper step, and a non-doped polysilicon layer is formed to a thickness corresponding to the substrate step, a flattened structure can be easily obtained.
表お、ここでノンドープポリシリコン層とは、不純物源
薄膜が高濃度に含む不純を、全く含まないか、るるいは
上記不純物源薄膜に比較して低濃度にしか含まないポリ
シリコン層丘・意味する。In this table, a non-doped polysilicon layer is a polysilicon layer that does not contain the impurities that the impurity source thin film contains at a high concentration, or only contains them at a low concentration compared to the impurity source thin film. means.
また、不純物源薄膜は、ポリシリコン金はじめ、アモル
ファスるるいは単結晶状の半導体または絶縁物等、不純
物の拡散源となるものでめれば特に制約はない。これに
対し、熱拡散によりこの不純物源薄膜のバタンを転写す
る烏ヲポリシリコンとしたのは、後述するようにポリシ
リコンの場合、ブレーンが下地基板表面での法線に沿っ
て成長し、かつ不純物が当該ブレーンに沿って拡散する
ことから、不純物薄膜のバタン全忠実に転写できるため
である。以下、実施例を用いて本発明の詳細な説明する
。Further, the impurity source thin film is not particularly limited as long as it serves as a diffusion source of impurities, such as polysilicon gold, amorphous lubrication, or single crystal semiconductor or insulator. On the other hand, the reason why we used polysilicon, which transfers the impurity source thin film pattern by thermal diffusion, is that in the case of polysilicon, as will be described later, the branes grow along the normal to the surface of the underlying substrate, and impurities are This is because the impurity thin film can be faithfully transferred in its entirety because it is diffused along the branes. Hereinafter, the present invention will be explained in detail using Examples.
本発明によれば、段差を有する基板の平坦化プロセスが
簡略に行なえることは上述した通シでめるが、本発明の
プロセス鉱、もちろん平坦な基板上に選択的にポリシリ
コン層全形成する場合にも適用できる。はじめにこの例
について第１図゛を用いて説明する。According to the present invention, it can be seen from the above-mentioned process that the planarization process of a substrate having a step can be easily performed. It can also be applied when First, this example will be explained using FIG. 1.
半導体基板１１の上にｘｏｏｏＸの厚みのＡｓ ドープ
ポリシリコン膜１２を形成し、その上にホトレジストバ
タン１ｓｔ形成する（第１図（ａ））。An As-doped polysilicon film 12 having a thickness of xoooox is formed on a semiconductor substrate 11, and a photoresist pattern 1st is formed thereon (FIG. 1(a)).
次に、このホトレジストバタン１３ｆ：マスクとしてＡ
８ ドープポリシリコン膜１２をエツチングし、所定の
形状を有するＡ８ドープポリシリコンパタン１２ａ と
する（第１図６））。Next, this photoresist button 13f: A as a mask.
8. The doped polysilicon film 12 is etched to form an A8 doped polysilicon pattern 12a having a predetermined shape (FIG. 1, 6).
このＡｓドープポリシリコンパタン１２ａｉ形成した半
導体基板１１の上に、ノンドープポリシリコン膜１４を
、例えばＳ ｉ Ｈ４ガスを用いた減圧ＣＶＤ法により
１μｍの厚みに形成する（第１図（Ｃ））。On the semiconductor substrate 11 on which the As-doped polysilicon pattern 12ai is formed, a non-doped polysilicon film 14 is formed to a thickness of 1 μm by, for example, low pressure CVD using SiH4 gas (FIG. 1(C)).
この半導体基板１１を例えば窒素雰囲気中で処理温度９
００℃で１０秒間の熱処理を行なう。この時のノンドー
プポリシリコン［１４中のＡｓの拡散鑞、当該ポリシリ
コンｊｉｌＪ中のブレーンに沿つて進行するため、横方
向の拡散は抑制され、Ａｓ鉱基板１１の表面での法線方
向にきわめて速く拡散し、下地バタン１２ａに対してき
わめて忠実なＡｓ ドープポリシリコン膜１５が形成さ
れる（第１図（ｄ）〕。This semiconductor substrate 11 is processed at a temperature of 9 in a nitrogen atmosphere, for example.
Heat treatment is performed at 00°C for 10 seconds. At this time, since the diffusion of As in the non-doped polysilicon [14] progresses along the branes in the polysilicon jilJ, lateral diffusion is suppressed, and the diffusion of As in the As ore substrate 11 is extremely normal to the surface of the substrate 11. An As-doped polysilicon film 15 that diffuses quickly and is extremely faithful to the underlying batten 12a is formed (FIG. 1(d)).
次に、Ａ８ドープポリシリコンのエツチングレートがノ
ンドープポリシリコンのそれよりもきわめて大きい選択
性の高いエツチング法、例えばエツチング温度２５０℃
におけるｃｔｌ プラズマエツチング法によりＡｓ
ドープポリシリコン膜１５を選択的に除去する。この結
果、半導体基板１１上のＡ８ドープポリシリコン展１５
部分を除いた領域のみにノンドープポリシリコン膜１４
が厚み方向に対しては垂直形状で形成された構造が得ら
れる（第１図（ｅ））。Next, a highly selective etching method in which the etching rate of A8 doped polysilicon is much higher than that of non-doped polysilicon is used, for example, at an etching temperature of 250°C.
As by the ctl plasma etching method in
Doped polysilicon film 15 is selectively removed. As a result, the A8 doped polysilicon layer 15 on the semiconductor substrate 11
Non-doped polysilicon film 14 is formed only in the area excluding the
A structure is obtained in which the shape is perpendicular to the thickness direction (FIG. 1(e)).
次に、段差を有する基板を平坦化する例について第２図
を用いて説明する。Next, an example of planarizing a substrate having a step will be described using FIG. 2.
段差を有する半導体基板２１の上に上述した実施例と同
様にＡｓ ドープポリシリコン膜ヲ形成し、エツチン
グによシ下段部を除去し上段部のみ残してＡｓドープポ
リシリコンパタン２２ａ とする（第２図（ａ））。An As-doped polysilicon film is formed on a semiconductor substrate 21 having a step in the same manner as in the embodiment described above, and the lower part is removed by etching, leaving only the upper part to form an As-doped polysilicon pattern 22a (second pattern). Figure (a)).
次に、減圧ＣＶＤ法により基板段差に相当する厚みのノ
ンドープポリシリコン膜２４全形成する（第２図（ｂ）
）。Next, a non-doped polysilicon film 24 with a thickness corresponding to the substrate step is entirely formed by low-pressure CVD (Fig. 2(b)).
).
この半導体基板２１を上述した実施例と同様に熱処理す
る。ノンドープポリシリコン膜２４のクレーンは下地基
板の表面での法線に沿って成長しており、Ａｓはそのク
レーンに沿って基板表面方向に拡散し、下地バタン２２
ａに対応して基板２１９上段部表面よｐ上の部分にのみ
Ａｓ ドープポリシリコン膜２５が形成される（第２図
（Ｃ））。This semiconductor substrate 21 is heat treated in the same manner as in the above embodiment. The crane of the non-doped polysilicon film 24 grows along the normal line to the surface of the base substrate, and As diffuses along the crane toward the substrate surface, forming the base substrate 22.
An As doped polysilicon film 25 is formed only in a portion above the upper surface of the substrate 219 corresponding to point a (FIG. 2(C)).
次に、Ａ、ドープポリシリコン膜２５のみを上述した実
施例と同様の方法で選択エツチングすれば、平坦な基板
表面を得ることができる（第２図（ｄ））。これを、例
えばｎ＋埋め込み層、ｎ形エピタキシャル）＠を含むｐ
−半導体基板に適用すればバイポーラＬＳＩの平坦な素
子量分Ｎ＃構造を得ることができる。その他、０ＭＯ８
、ｎＭＯ８等の素子間分離にも適用でき、種々のパター
ン幅（溝幅）を有する基板段差を、ポリシリコンのエツ
チング特性を利用することにょクセルファライン的に容
易に平坦化することができる。Next, by selectively etching only the doped polysilicon film 25 in the same manner as in the above embodiment, a flat substrate surface can be obtained (FIG. 2(d)). For example, p
- If applied to a semiconductor substrate, it is possible to obtain an N# structure with a flat element size of a bipolar LSI. Others, 0MO8
, nMO8, etc., and substrate steps having various pattern widths (groove widths) can be easily flattened in a self-aligning manner by utilizing the etching characteristics of polysilicon.
さらに、段差を有する基板を用い、その上下段部に相互
に分離されたポリシリコン膜を形成する例を、第３図を
用いて説明する。Furthermore, an example in which a substrate having steps is used and polysilicon films separated from each other are formed on the upper and lower steps will be described with reference to FIG.
段差を有する半導体基板３１に上述した実施例と同様に
Ａｓ ドープポリシリコン膜３２′？！：形成する（
第３図（ａ））。As in the embodiment described above, an As-doped polysilicon film 32' is formed on a semiconductor substrate 31 having a step. ! :Form(
Figure 3(a)).
次にこの人８ ドープポリシリコン［３２に異方性ドラ
イエツチングを施し、基板３１の上下段の平坦部のみ除
去して段差部側壁にのみＡｓ ドープポリシリコンパ
タン３２ａ を残す（第３図（ｂ））。Next, this doped polysilicon pattern 32 is subjected to anisotropic dry etching to remove only the upper and lower flat portions of the substrate 31, leaving As doped polysilicon patterns 32a only on the side walls of the stepped portions (Fig. 3(b) )).
ここで、異方性ドライエツチング法としては例えば５ｉ
Ｃ１４ガスを用いた垂直加工性にすぐれたりアクティブ
イオンエツチング法が好適である。Here, as an anisotropic dry etching method, for example, 5i
An active ion etching method using C14 gas is suitable because it has excellent vertical processability.
次いで、上述したと同様にノンドープポリシリコンｒＭ
３４を堆積した後、高温アニールを行なうことにより、
段差部側壁のＡｓ ドーズシリコンバタン３２ａ に接
しているノンドープポリシリコン膜にＡｓ が拡散され
、Ａｓ ドープポリシリコン膜３５が形成される（第３
図（Ｃ））。Next, as described above, non-doped polysilicon rM
After depositing 34, by performing high temperature annealing,
As is diffused into the non-doped polysilicon film in contact with the As-doped silicon batten 32a on the side wall of the stepped portion, and an As-doped polysilicon film 35 is formed (third
Figure (C)).
次にＣ４！プラズマエツチングによ５Ａａ ドープポリ
シリコン膜３５を除去することにより、上下段の平坦部
にのみノンドープポリシリコン３４３４が残され、段差
部側壁にはポリシリコン膜がなく半導体基板３１自体が
露出した基板ａ４造が得られる（第３図（ｄ））。Next is C4! By removing the 5Aa doped polysilicon film 35 by plasma etching, non-doped polysilicon 3434 is left only on the upper and lower flat parts, and there is no polysilicon film on the side walls of the step part, leaving the semiconductor substrate 31 itself exposed. A structure is obtained (Fig. 3(d)).
このように基板の段差部以外の創域にポリシリコンＭｒ
セルファライン的に形成することにより、ＣれｋＭＯ８
，６るいはバイポーラデバイス等の製造プロセスに適用
した一合、基板段差の量によってデバイスのパターン幅
ケ正確に制御することができる。例えば第４図はＭＯＳ
＋・ランジスタに適用し一７’Ｃ揚合の断面構造を示
すが、半導体基板４１の上下段の平坦部に形成したポリ
シリコン膜に不純物をドープしてンーメ４２およびドレ
イン４３とし、基板露出部を含む段差部にゲート絶縁膜
４４を介して不純物ドープポリシリコンからなるゲート
電極４５を形成している。なお４６祉半導体基板４１の
上下段平坦部表面に形成された不純物（例えばボロン）
Ｍを示す。In this way, polysilicon Mr.
By forming in a self-aligned manner, CrekMO8
, 6, or bipolar devices, the pattern width of the device can be accurately controlled by the amount of the substrate step. For example, Figure 4 shows MOS
＋・The cross-sectional structure of a 17'C transistor applied to a transistor is shown; impurities are doped into the polysilicon film formed on the upper and lower flat parts of the semiconductor substrate 41 to form the drain 42 and the drain 43, and the exposed parts of the substrate are A gate electrode 45 made of impurity-doped polysilicon is formed on the stepped portion including the gate insulating film 44 . Note that impurities (for example, boron) formed on the surface of the upper and lower flat parts of the semiconductor substrate 41
Indicates M.
同図から明ら力為なように、この構造では基板の表面段
差がそのｔｔ−ゲート長りとなるため、ゲート長の制御
が容易となる利点を有する。As is clear from the figure, this structure has the advantage that the gate length can be easily controlled because the surface step of the substrate becomes the tt-gate length.
以上説明したように、本発明によれば、半導体基板上に
不純物源薄膜パタン全弁して形成したノンドープポリシ
リコン層に、熱拡散により不純物ドープバタンを転写し
、その後エツチング特性の差を利用してこの不純物ドー
プポリシリコンのみ除去してノンドープポリシリコンの
み残すというきわめて簡単なプロセスにより、段差を有
する基板の平坦化をはじめとする種々の基板構造が実現
でき、微ｉ累子間分離構造をはじめ高性能デバイスの製
造プロセスに利用してきわめて有用である。As explained above, according to the present invention, an impurity doped pattern is transferred by thermal diffusion to a non-doped polysilicon layer formed by fully forming an impurity source thin film pattern on a semiconductor substrate, and then etching is performed using the difference in etching characteristics. This extremely simple process of removing only impurity-doped polysilicon and leaving only non-doped polysilicon makes it possible to realize various substrate structures, including the planarization of substrates with steps, and to create high-temperature structures such as micro-i isolation structures. It is extremely useful for use in the manufacturing process of performance devices.
第１図線本発明の一実施例を示す工程断面図、第２図お
よび第３図はそれぞれ本発明の他の実施例を示す工程断
面図、第４図は第３図の実施例を利用したＭＯＳ ）ラ
ンジスタを示す断面図でらる。
１１，２１．３１・・・・半導体基板、１２ａ。
２２ａ、３２ａ ・・争・Ａｓ ドープポリシリコ
ン膜（タン（不純物源薄膜）、１４，２４．３４・・・
・・ノンドープポリシリコンｆｆｌ、１５，２５．３５
・・・・Ａｓ ドープポリシリコン膜。Fig. 1 is a process sectional view showing one embodiment of the present invention, Figs. 2 and 3 are process sectional views showing other embodiments of the invention, and Fig. 4 is a process sectional view using the embodiment of Fig. 3. This is a cross-sectional view showing a MOS (MOS) transistor. 11,21.31...Semiconductor substrate, 12a. 22a, 32a... As doped polysilicon film (tan (impurity source thin film), 14, 24.34...
・・Non-doped polysilicon ffl, 15, 25.35
...As doped polysilicon film.
Claims (3)
膜を所定のパタンに形成する工程と、この不純物源薄膜
を形成した半導体基板上にノンドープポリシリコン層を
堆積する工程と、熱処理によつて下地の不純物源薄膜中
の不純物をその上のポリシリコン層中に選択的に拡散さ
せる工程と、拡散部分のポリシリコン層を選択的にエッ
チングすることにより非拡散部分のポリシリコン層のみ
を残す工程とを含むことを特徴とする半導体装置の製造
方法。(1) A process of forming an impurity source thin film containing a high concentration of impurities in a predetermined pattern on a semiconductor substrate, a process of depositing a non-doped polysilicon layer on the semiconductor substrate on which this impurity source thin film is formed, and a heat treatment process. Then, the impurities in the underlying impurity source thin film are selectively diffused into the polysilicon layer above it, and the polysilicon layer in the diffused portion is selectively etched, leaving only the polysilicon layer in the non-diffused portion. A method for manufacturing a semiconductor device, comprising the steps of:
に不純物源薄膜を形成し、かつノンドープポリシリコン
層を基板段差に相当する厚みに形成することを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。(2) A semiconductor substrate having a step is used, an impurity source thin film is formed only on the upper step, and a non-doped polysilicon layer is formed to a thickness corresponding to the substrate step. A method of manufacturing the semiconductor device described above.
のみに不純物源薄膜を形成し、エッチングにより上下段
部のみに相互に分離したポリシリコン層を残すことを特
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(3) A semiconductor substrate having a step is used, an impurity source thin film is formed only on the side wall of the step, and polysilicon layers separated from each other are left only in the upper and lower steps by etching. A method for manufacturing a semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13117584A JPS6112031A (en) | 1984-06-27 | 1984-06-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13117584A JPS6112031A (en) | 1984-06-27 | 1984-06-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6112031A true JPS6112031A (en) | 1986-01-20 |
Family
ID=15051757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13117584A Pending JPS6112031A (en) | 1984-06-27 | 1984-06-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6112031A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5310698A (en) * | 1990-12-21 | 1994-05-10 | Siemens Aktiengesellschaft | Process for producing an arsenic-doped smooth polycrystalline silicon layer for very large scale integrated circuits |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5312278A (en) * | 1976-07-20 | 1978-02-03 | Matsushita Electric Ind Co Ltd | Production of mos type semiconductor device |
-
1984
- 1984-06-27 JP JP13117584A patent/JPS6112031A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5312278A (en) * | 1976-07-20 | 1978-02-03 | Matsushita Electric Ind Co Ltd | Production of mos type semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5310698A (en) * | 1990-12-21 | 1994-05-10 | Siemens Aktiengesellschaft | Process for producing an arsenic-doped smooth polycrystalline silicon layer for very large scale integrated circuits |
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