JPS59219966A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make contact windows sufficiently small by forming a groove through etching while using a film left on the side wall of the contact window as a mask when two regions are brought into contact with an electrode from one contact window. CONSTITUTION:A P well 2, a gate electrode 5, a gate oxide film 11 and N type drain 3 and source 4 regions are formed, contact windows 15 are bored, a SiO2 film 16 is deposited, and SiO2 films 17 are left only on the side walls of the contact windows 15 through anisotropic etching. A groove 9 reaching to the P type region 2 is formed by etching through a window 15' by using a photo-resist 18. Metallic wirings 6, 7 for a drain and a source are shaped, thus forming an N channel MOSFET. Since the window 15' has the relationship of self-alignment to the contact windows 15 and the thickness of the films 17 can be made sufficiently smaller than that of the contact windows, the width of the contact windows 15 can be brought to fine size in approximately minimum line width.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device.
It relates to contacts between electrodes and impurity regions used in O3ICs, double-diffused MO8) transistors, and the like.

Conventional configurations and their problems In recent years, as the density of semiconductor devices has increased, the contact area between electrodes and impurity regions on the surface of semiconductor substrates has become smaller, resulting in the problem of increased contact resistance between them. ing.

Conventional problems will be explained by taking complementary MOSLSI (hereinafter abbreviated as CMOS) as an example. Figure 1(a).

(b) is n-channel MO3F in p-well of CMOS
It is a figure showing the cross-sectional structure of ET. In FIG. 1(a), 1 is an n-type substrate, 2 is a p-type impurity region called a p-well, 3 and 4 are n-type high concentration regions, which are drain and source regions, respectively, 6 is a gate electrode, 6, 7 is a drain and source electrode, and 8 is an oxide film.

When the p-well region 2 is at a floating potential, the MOS in the p-well
The potential of this region is usually fixed to the ground potential because the transistor's threshold value (T) changes or the withstand voltage between the drain and the substrate decreases, making it easy to cause so-called latch and lag phenomena. In this case, the impurity concentration in the p-well is kept low to avoid increasing the threshold of the n-channel MO3) transistor, so in order to keep the potential of the well at ground potential, it is common to keep it at ground potential at multiple locations in the well. It is.

For this reason, the source electrode &7 in Fig. 1 is in contact not only with the source region 4 but also with the well 2.

The larger the number of contacts with such a well, the more the well can be kept completely at the ground potential, or on the other hand, from the standpoint of high density, it is necessary to make the contact area as small as possible. The contact between the source electrode 7 and the diffusion layers 2 and 4 in FIG.
This is intended to lower the contact resistance, and is disclosed, for example, in Japanese Patent Application No. 68-20638 filed by the present applicant. However, in the conventional manufacturing method as shown in this application, although the contact resistance is reduced, it is necessary to reserve a margin in advance for the photo-etching process during the manufacturing process, so the contact window width W
. (shown in FIG. 1a) cannot be made below a certain value, and this method is not necessarily suitable for high integration.

Figure 1(b) is a diagram for explaining the conventional manufacturing method.
FIG. 3 is a process cross-sectional view of a process of forming grooves 9; After forming the p-well 2, n-regions 3, 4, and gate 5 and opening a window in the oxide film 8, a photoresist 10 is patterned as an etching mask for forming the groove 9, as shown in FIG. 1(b). It is. After this, the silicon region 9 exposed on the surface is etched by plasma etching in CF4 gas.
' is etched, and 9 is formed. In this process, the width W of the contact window is determined. The minimum value of is determined. In other words, even if the photoresist window width b (shown in FIG. 1(b)) is formed with the minimum pattern-formable dimension d, if the mask alignment accuracy is ±Δd, then in FIG. 1(b)
, c) Since it must be Δd, it ends up being W. 〉d+2
It is necessary to set it to Δd. In reality, since the photoresist film 10 is thick near the contact window, the resolution tends to decrease, and Wo is usually selected to be at least twice the minimum line width d. In this way, in the conventional manufacturing method, the contact window width W
0 could not be made small, which was one of the causes that hindered the increase in the density of integrated circuits.

The above example was for contacting the source n+ region and p-well of 0MO8 at the same time, but the double-diffused MO3 (
DMO3 (abbreviated hereafter) had a similar problem. As discussed in detail in the above-mentioned Japanese Patent Application No. 58-20638, in order to increase the voltage resistance of the DMO 8, it is necessary to ensure that the channel region is at the source potential. I can't think of a way to widen the contact window to ensure that the channel region is at the source potential, but widening the contact window increases parasitic capacitance, reduces high-frequency characteristics, and increases the chi knob size. There was also the problem of high costs.

Purpose of the Invention The present invention was made in view of the problem that when making contact with an electrode from one contact window to two regions of P type and N type, the contact window cannot be made sufficiently small. The present invention provides a method for manufacturing a semiconductor device having a contact structure capable of realizing reliable contact between electrode impurity regions with a small contact window and low contact resistance.

Structure of the Invention The present invention provides contact windows with different depths from one contact window.
When forming contacts with electrodes in two regions of a mold, a film is left on the side wall of the contact window in a self-aligned manner by anisotropic dry etching, and the remaining film is used as a mask to etch the impurity region to form the deeper one. The present invention provides a method for manufacturing a semiconductor device characterized by forming a groove that reaches a region and obtaining contact between two regions and an electrode.

DESCRIPTION OF EMBODIMENTS Specific embodiments of the present invention will be described with reference to the drawings. Second
The figure shows the present invention in a p-well of 0MO8) and 1v
It is a sectional process diagram when applied to the manufacture of iO3FET. For ease of explanation, components common to the conventional example are given the same numbers. In Figure 2 (-), 1 is an n-type substrate, 2 is a p-well, 5 is a gate electrode made of polycrystalline silicon, 11 is a gate oxide film, and 12 is a nootresist, which is an n-type drain formed by ion-implanting arsenic. 3 and a source 4 are formed. Next, Figure 2(b)
As shown in the figure, the 3102 film 13 was formed into a 200% film by the CVD method.
About 5000A is formed from o people.

Furthermore, as shown in FIG. 2(c), using the photoresist 14 as a mask, contact windows 1 are formed in the S102 films 11 and 13.
Open 5. Next, as shown in Figure 2(d), S containing phosphorus
102 membrane 16 (thickness t) from 1000 to 3000A
It accumulates to some extent. The S102 film 16 does not necessarily have to be a Si02 film containing phosphorus, but it is
This is because it is desirable that the etching rate of the S102 film 16 be faster than that of the S2 film 13. Next, the S z 02 film 16 is etched in a gas atmosphere such as CCl4 using a parallel plate type active sputtering device. The etching then becomes so-called anisotropic etching, which progresses uniformly in the vertical direction, leaving the S 102 film 16 only on the side wall of the contact window 15, as shown in FIG. 2(e). In this case, the thickness S of the remaining S x 02 film 17 is S 102 film 16
The thickness will be approximately t.

Next, cover the contact area that is not desired to be etched with a photoresist 18, and then apply the remaining S102 film 1.
A groove 9 reaching the p-type region 2 is formed by etching the silicon through the window 15' sandwiched between the grooves 7 and 7. Silicon etching uses plasma etching in a cF4 atmosphere.

Of course, wet etching using a mixed solution of hydrofluoric acid and nitric acid may also be used. Next, after removing the photoresist 18, etching is performed using a hydrofluoric acid-based etching solution to remove the 5IO2 film 17. In this case, if the aforementioned ioK S 102 film 17 contains phosphorus, 5io
Since the etching rate is several times higher than that of 2[13], the size of the contact window 16 does not need to be changed much (51).
02 film 17 can be removed. Then, drain and source metal wirings 6 and 7 are formed by a known method to form an n-channel MO8FET in a p-well as shown in FIG. 2(q).

In this way, there is a groove inside the contact window that penetrates the source region and reaches the channel region, and the source region and source electrode are in contact with the side surfaces of the groove and the flat part of the inner periphery of the contact window. You can get the equipment.

If such a manufacturing method of the present invention is used, the contact window 15
The width can be made as fine as the minimum line width.

This is because the window 16' is self-aligned with the contact window 15 when silicon etching is performed, and the thickness S of the coating 17 on the side wall of the contact window 15 is sufficiently large compared to the contact window width W (coating 16'). This is because it can be made to a thickness of about t).

This is very helpful in increasing the density of CMOS integrated circuits.

Furthermore, as shown in FIG. 2(q), the source region 4 and the source electrode 7 have contact at the flat part of the inner periphery of the contact window that is formed after removing the side surface of the groove 9 and the coating 17 on the side wall of the contact window. The structure has a large contact area and low contact resistance. Furthermore, since the electrode 7 has a structure in which it penetrates into the inside of the p-well 2, the contact area with the p-well 2 is small, and the contact resistance is small, so the p-well 2 is kept at ground potential, making it difficult to cause latch knobs. .

The above example is a case where the present invention is applied to a CMOS, but P from one contact window such as DMO8.

It is clear that the present invention can also be applied to devices in which it is desirable to contact two regions. When applied to the DMO8, it is possible to prevent a drop in breakdown voltage due to the parasitic bipolar transistor of the DMOS and to make the contact smaller, which is highly effective in increasing the breakdown voltage and frequency.

Effects of the Invention As described above, the manufacturing method and semiconductor device of the present invention have 1
It is possible to achieve reliable contact with the electrodes in both the p and n regions through two small contact windows with low contact resistance, and this greatly contributes to higher density and higher frequency of semiconductor devices and integrated circuits.

[Brief explanation of drawings]

FIG. 1(a) t(b> is a structural cross-sectional view and a process cross-sectional view of an n-channel MO8FET in a conventional 0MO8 p-well, and FIGS. 2(a) to (q) are manufacturing examples of an embodiment of the present invention. n-channel MO3 in C1vIO5p well by method
It is a sectional view of the manufacturing process of FET. 1... N-type silicon substrate, 2... P-well, 3... N-type drain region, 4...
・N-type source region, 6...gate electrode, 6...
...Drain electrode, 7...Source electrode, 9.
...is formed on a silicon substrate, 16...
...Contact window, 17...S No 2 film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (2)

[Claims] (1) A step of forming a first conductivity type region on the surface of the semiconductor substrate, a step of forming a first film on the surface of the semiconductor substrate, and a step of forming a first conductivity type region from a window provided in the first film. forming a second conductivity type region shallower than that region; forming a second coating and selectively leaving the second coating on the sidewall of the window using anisotropic dry etching; etching the semiconductor substrate using the remaining second coating as a mask until reaching the first conductivity type region;
A method of manufacturing a semiconductor device, the method comprising: forming an electrode in contact with a conductivity type region. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the second coating is a coating containing phosphorus glass.