JPH01214040A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the degree of integration of a semiconductor integrated circuit by a method wherein a vertically pierced groove is formed in a semiconductor substrate and the groove is used as a mutual alignment mark between a surface circuit pattern and a rear circuit pattern in order to improve the alignment accuracy between both, to enhance the operation efficiency or to reduce an area of a mutual connection part. CONSTITUTION:When a semiconductor integrated circuit having mutually electrically connected circuit patterns 3, 4 on both the surface and the rear of a semiconductor substrate 1 is to be manufactured, vertically pierced grooves 2 formed in advance in the semiconductor substrate 1 before or after a circuit formation process of the surface (or the rear) of the semiconductor substrate 1 or structures formed on the basis of the grooves 2 are used as alignment marks in a circuit formation process of the rear (or the surface) of the semiconductor substrate 1. For example, after the grooves whose diameter corresponds to the outside diameter of silicon nitride films 5 have been formed in required parts on the surface of the Si substrate 1, the silicon nitride films 5 and polycrystalline Si layers 6 are formed. Then, after the surface circuit pattern 3 has been formed, the vertically pierced grooves 2 are formed. Then, a rear circuit pattern 4 is formed on the rear of the Si substrate 1. The vertically pierced grooves 2 are used as alignment reference points during this process.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for manufacturing a semiconductor integrated circuit, particularly when forming circuit patterns that require mutual electrical connection on both the front and back surfaces of a semiconductor substrate. Regarding mutual alignment method.

[Conventional technology]

Conventionally, when forming circuit patterns that require mutual electrical connection on the front and back sides of a semiconductor substrate, the circuit patterns on the front and back sides are placed on the semiconductor substrate in such a way that the circuit positions that should be the connection points of the front and back side circuit patterns match. As a means for determining the formation position of the semiconductor substrate, it has been common to perform positioning with reference to an orientation flat formed on the outer periphery of the semiconductor substrate.

[Problem to be solved by the invention]

The conventional semiconductor integrated circuit manufacturing method described above relies only on the shape of the outer periphery of the semiconductor substrate to align the circuit patterns on both the front and back sides, so there is a limit to the improvement of accuracy, and It is not possible to correct the position for each circuit pattern, and it is necessary to make only the interconnection part of the circuit pattern on both sides abnormally larger than the other parts.

[Means to solve the problem]

The method for manufacturing a semiconductor integrated circuit of the present invention includes forming a circuit on the front surface (or back surface) of the semiconductor substrate in manufacturing a semiconductor integrated circuit having circuit patterns electrically connected to each other on both the front and back surfaces of the semiconductor substrate. A vertical through groove previously formed on the semiconductor substrate before or after the process or a structure formed based on the groove is applied to the back surface (or front surface) of the semiconductor substrate.
It is used as an alignment mark in the circuit formation process.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(a) is a plan view of a semiconductor chip for explaining the first embodiment of the present invention, and FIG. 1(b) is a plan view of a semiconductor chip for explaining the first embodiment of the present invention.
This is a cross-sectional view taken along line xx' of the tree.

This embodiment will be described assuming a manufacturing process order in which circuit formation on the front surface is performed first and circuit formation on the back surface is performed later. Figure 1 (a
), the silicon nitride film 5 and polycrystalline silicon 6 shown by many broken lines penetrate through the silicon substrate 1 as shown in FIG. Form it first. That is, after forming grooves corresponding to the circular outer diameter of the silicon nitride film 5 through a photoresist processing process (PR process) and an etching process at locations necessary for the circuit on the surface of the silicon substrate 1, a silicon nitride film as an insulating layer is formed. 5 and a polycrystalline silicon layer 6 as a conductive layer by CVD.
Formed by etc. Next, a surface circuit pattern 3 (shown very simply for convenience) including elements such as transistors and metal wiring is formed using a normal manufacturing process, and then a vertical through groove 2 is formed using a PR process and an etching process. . Next, a back side circuit pattern 4 consisting mainly of metal wiring is formed on the back side of the silicon substrate 1, but the previously manufactured back side circuit pattern 4 is used as an alignment reference when determining the mask pattern position for this first PR process. A vertical through groove 2 is used.

In the subsequent manufacturing process of the backside circuit pattern 4, the mask pattern position determination method for the second and subsequent PR processes includes:
There is a method of using the vertical through groove 2 again as the alignment reference, and a method of using the vertical through groove 2 again as the alignment reference, and a method of using the vertical through groove 2 again as the alignment reference, and
There is a method of putting alignment marks in advance for use in the R process. In this way, the necessary places are made of polycrystalline silicon 6.
Surface circuit patterns 3 electrically connected to each other by
A semiconductor integrated circuit having the back side circuit pattern 4 can be manufactured.

According to this method, the vertical through groove 2 provided for each chip is used as a means for determining the position of the circuit pattern on the back side, so it is similar to the PR process assembly method for each layer when forming the circuit pattern on only one side. It is possible to use the general method described above, and the alignment accuracy can be improved in proportion to the improvement in the accuracy of forming the vertical through grooves 2. Therefore, the alignment method for the PR process for the back side circuit and the front side circuit can be made common, which leads to simplification of the manufacturing process. In addition, vertical through groove 2
The shape, arrangement on the chip, and number can be changed as necessary, and there is also room for change in the order of manufacturing steps. Furthermore, if the back side circuit pattern 4 includes not only metal wiring but also transistor elements etc., it is necessary to manufacture the transistor elements etc. of the back side wiring pattern 4 before forming the metal wiring of the front side circuit pattern 3. The vertical through groove 2 may be formed before the metal wiring of the surface circuit pattern 3 is formed.

Since the vertical through grooves are provided for each chip, the front and back circuit patterns can be aligned with high precision, so the size of the interconnection portions of the circuit patterns on both sides can be reduced and the degree of integration can be improved.

FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention. In this embodiment, a polycrystalline silicon film 6' is embedded in a vertical through-groove via a silicon nitride film 5' as a mark for the alignment process when forming the back side circuit pattern 4.
Since this structure is similar to the electrical connection path between the front and back circuit patterns, there is an advantage that both can be formed in the same process.

[Effects of the Invention] As explained above, the present invention improves the alignment accuracy between the front and back circuit patterns by forming vertical through grooves in the semiconductor substrate and using them as marks for mutual alignment between the front and back circuit patterns. This has the effect of improving work efficiency or reducing the area of interconnections and improving the degree of integration of semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1<a) is a plan view of a semiconductor chip for explaining the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along the line xx' of FIG. 1(a), The figure is a cross-sectional view of a semiconductor chip for explaining the second embodiment. 1... Silicon substrate, 2... Vertical through groove, 3...
Surface circuit pattern, 4... Back circuit pattern, 5.5
'...Silicon nitride film, 6.6'...Polycrystalline silicon. Agent Patent Attorney Uchi Hara Oto 3F〉〉Turn to each concave surface Fig. 1

Claims (1)

[Claims] In manufacturing semiconductor integrated circuits that have circuit patterns that are electrically connected to each other on both the front and back sides of a semiconductor substrate,
A vertical through groove previously formed on the semiconductor substrate before or after the circuit formation process on the front surface (or back surface) of the semiconductor substrate or a structure formed based on the groove is formed on the back surface (or front surface) of the semiconductor substrate. ) A method for manufacturing a semiconductor integrated circuit, characterized in that it is used as an alignment mark in a circuit formation process.