CN117666279A - Mask plate and assembly thereof, semiconductor structure, forming method and measuring method thereof - Google Patents

Mask plate and assembly thereof, semiconductor structure, forming method and measuring method thereof Download PDF

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Publication number
CN117666279A
CN117666279A CN202211033524.1A CN202211033524A CN117666279A CN 117666279 A CN117666279 A CN 117666279A CN 202211033524 A CN202211033524 A CN 202211033524A CN 117666279 A CN117666279 A CN 117666279A
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CN
China
Prior art keywords
pattern
mask plate
shaped
patterns
mask
Prior art date
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Pending
Application number
CN202211033524.1A
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Chinese (zh)
Inventor
朱宏亮
段培业
王凤娇
谢逸飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202211033524.1A priority Critical patent/CN117666279A/en
Publication of CN117666279A publication Critical patent/CN117666279A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/70516—Calibration of components of the microlithographic apparatus, e.g. light sources, addressable masks or detectors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Multimedia (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

A mask and components thereof, a semiconductor structure, methods of forming and measuring the same, the mask comprising: at least 1 metrology pattern structure, the metrology pattern structure comprising: at least 1 of a comb pattern, a semi-chain pattern, and a T-pattern; and when the semiconductor structure formed by the mask assembly formed by the mask plate is measured, the splicing offset is measured according to the at least 1 first positioning pattern and the at least 1 second positioning pattern. According to the electrical performance test result, the mask splicing condition is monitored, the accuracy is higher, the pattern alignment condition can be accurately judged, and the monitoring position is increased for on-line defect scanning.

Description

Mask plate and assembly thereof, semiconductor structure, forming method and measuring method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a mask, a mask assembly, a semiconductor structure, a method of forming the same, and a method of measuring the same.
Background
Charge coupled devices are widely used in the fields of military, industrial monitoring, security monitoring and the like, and as the technology level increases, CCDs develop towards larger pixels and array sizes to meet the increasing application demands, and although wafers used for large array CCD chips can meet the demands, the maximum exposure area of a photoetching machine cannot meet the demands of CCDs, so that photoetching technology manufacturing is required by adopting a spliced exposure mode.
In contrast to the interlayer alignment technique of a normal photolithography process, mask stitching needs to take into account both interlayer alignment and alignment issues of the same layer pattern. The pattern defects such as deformation, incoherence, line widening or narrowing and the like often occur at the spliced position, and particularly if the photoetching is followed by an etching process, the pattern defects generated by photoetching splicing can be further amplified in the follow-up etching step, the quality of the manufactured pattern of the process is seriously influenced, and finally, the performance index of the large-array CCD is influenced.
However, the existing measurement method is difficult to comprehensively monitor the alignment condition of the patterns on the same layer, and has low measurement accuracy.
Disclosure of Invention
The invention solves the problem of improving the alignment measurement precision of the splicing of mask assemblies.
In order to solve the above problems, the present invention provides a mask plate, comprising: at least 1 measurement pattern structure, the measurement pattern structure includes: at least 1 of a comb pattern, a semi-chain pattern, and a T-pattern; wherein the comb pattern comprises: a connection stripe pattern extending in a first direction; the plurality of comb-rack-shaped patterns extend along the second direction, one end of each comb-rack-shaped pattern is connected with the connecting strip-shaped patterns, the plurality of comb-rack-shaped patterns are separated and arranged in parallel along the first direction, and the second direction is perpendicular to the first direction; the semi-chain pattern includes: at least 1U-shaped pattern which is arranged along the first direction in a separated mode, and the openings of the U-shaped patterns are oriented to be the same along the second direction; the T-shaped pattern includes: a first stripe pattern extending in a first direction; and the second strip-shaped pattern extends along the second direction, and one end of the second strip-shaped pattern is connected with the midpoint of the first strip-shaped pattern along the first direction.
Correspondingly, the invention also provides a mask assembly, which comprises: the first mask plate and the second mask plate are respectively mask plates of the invention; when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, the patterns of at least 1 measurement pattern structure of the first mask plate and the patterns of at least 1 measurement pattern structure of the second mask plate are in one-to-one correspondence.
In addition, the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate and a mask assembly, wherein the mask assembly is the mask assembly of the invention; transferring the pattern of the mask assembly onto the substrate, wherein the step of transferring the pattern of the mask assembly onto the substrate comprises: transferring the pattern of the lower mask plate to a substrate, wherein the lower mask plate is one of a first mask plate and a second mask plate; after the pattern of the lower-layer mask plate is transferred, transferring the pattern of the upper-layer mask plate to a substrate, wherein the upper-layer mask plate is the other one of the first mask plate and the second mask plate.
In addition, the invention also provides a measuring method of the semiconductor structure, wherein the semiconductor structure is the semiconductor structure of the invention; the semiconductor structure includes: at least 1 first positioning structure, wherein the first positioning structure is formed by transferring at least 1 measuring pattern structure of a first mask plate onto a substrate; at least 1 second positioning structure, wherein the second positioning structure is formed by transferring at least 1 measuring pattern structure of a second mask plate onto a substrate; at least 1 first positioning structure corresponds to at least 1 second positioning structure one by one; the measuring method comprises the following steps: and measuring the splice offset according to at least 1 first positioning pattern and at least 1 second positioning pattern.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the invention, the mask plate comprises: at least 1 measurement pattern structure, the measurement pattern structure includes: at least 1 of a comb pattern, a semi-chain pattern, and a T-pattern; when measuring the semiconductor structure formed by the mask assembly formed by the mask plate, measuring the splicing offset according to at least 1 first positioning pattern and at least 1 second positioning pattern. According to the electrical performance test result, the mask splicing condition is monitored, the accuracy is higher, the pattern alignment condition can be accurately judged, and the monitoring position is increased for on-line defect scanning.
Drawings
FIG. 1 is a schematic top view of a mask assembly used in a method of forming a semiconductor structure;
FIG. 2 is an enlarged schematic view of a corresponding pair of first alignment bars and second alignment bars in the mask assembly of FIG. 1;
FIG. 3 is a pair of first and second alignment patterns aligned in a semiconductor structure formed by the method of forming a semiconductor structure of FIG. 1;
FIG. 4 is a schematic top view of an embodiment of a mask of the present invention;
FIG. 5 is a schematic top view of an embodiment of a mask assembly of the present invention;
FIG. 6 is a schematic structural view of a first test pattern in a first reticle in the embodiment of the mask assembly shown in FIG. 5;
FIG. 7 is a schematic diagram of a second test pattern in a second reticle in the embodiment of the mask assembly shown in FIG. 5;
FIG. 8 is a schematic structural diagram of a first test pattern and a corresponding second test pattern when the patterns of the first mask plate and the second mask plate are spliced to form a complete mask pattern in the embodiment of the mask assembly shown in FIG. 5;
FIG. 9 is a schematic top view of an embodiment of a semiconductor structure according to the present invention;
FIG. 10 is a flow chart of a method for measuring a semiconductor structure according to an embodiment of the invention.
Detailed Description
As known from the background art, the measurement method of graph stitching in the prior art has the problem of low precision. The method for measuring the semiconductor structure is combined to analyze the reason of the problem of low precision of the graph splicing measuring method.
In a method of forming a semiconductor structure, first, a substrate (not shown) and a mask assembly 10 (fig. 1) are provided, wherein the mask assembly 10 includes: a first mask plate 11 and a second mask plate 12, the first mask plate 11 has a plurality of first alignment strips 11o thereon, and the second mask plate 12 has a plurality of second alignment strips 12i thereon.
Secondly, transferring the pattern of the lower mask plate to a substrate, wherein the lower mask plate is one of the first mask plate 11 and the second mask plate 12; after transferring the pattern of the lower mask plate, transferring the pattern of the upper mask plate to a substrate, wherein the upper mask plate is the other one of the first mask plate 11 and the second mask plate 12; in the step of transferring the pattern of the upper mask plate onto the substrate, the first alignment bars 11o of the first mask plate 11 and the second alignment bars 12i of the second mask plate 12 are aligned one by one. As shown in fig. 2, the alignment pattern 13o on the first alignment bar 11o and the alignment pattern 13i on the second alignment bar 12i are boxes with unequal side lengths.
The semiconductor structure formed includes: a plurality of first positioning patterns, wherein the first positioning patterns are formed by transferring alignment patterns on the first alignment strips onto a substrate; and the second positioning patterns are formed by transferring the alignment patterns on the second alignment strips to the substrate.
Referring to fig. 3, a pair of first and second alignment patterns aligned in a formed semiconductor structure is shown.
When the first positioning pattern 14o and the second positioning pattern 14i are aligned, the second positioning pattern 14 having a larger side length surrounds the first positioning pattern 14o having a smaller side length, i.e., the first positioning pattern 14o having a smaller side length is located inside the second positioning pattern 14 having a larger side length.
The method for measuring the semiconductor structure comprises the following steps: the pitches between the corresponding sides of the first positioning image 14o and the second positioning image 14i, that is, the pitch a and the pitch b, are measured to obtain the shift amount of the pattern stitching of the first mask plate 11 and the pattern stitching of the second mask plate 12.
The measurement method cannot comprehensively and accurately monitor the alignment of the patterns on the same layer, particularly relates to pattern splicing of an active region, a patterned polysilicon layer and a patterned metal wire, and is more difficult to monitor the alignment of the patterns.
In addition, in the step of measuring the distance between the corresponding sides of the first positioning image 14o and the second positioning image 14i, the measurement is usually performed by using a measuring tool, so that the measurement accuracy is low, and it is difficult to obtain the alignment more accurately.
In order to solve the technical problem, the invention provides a mask plate, which comprises: at least 1 measurement pattern structure, the measurement pattern structure includes: at least 1 of a comb pattern, a semi-chain pattern, and a T-pattern; wherein the comb pattern comprises: a connection stripe pattern extending in a first direction; the plurality of comb-rack-shaped patterns extend along the second direction, one end of each comb-rack-shaped pattern is connected with the connecting strip-shaped patterns, the plurality of comb-rack-shaped patterns are separated and arranged in parallel along the first direction, and the second direction is perpendicular to the first direction; the semi-chain pattern includes: at least 1U-shaped pattern arranged along the first direction in a separated manner, wherein the openings of the U-shaped patterns face the same direction along the second direction, and the second direction is perpendicular to the first direction; the T-shaped pattern includes: a first stripe pattern extending in a first direction; and the second strip-shaped pattern extends along the second direction, one end of the second strip-shaped pattern is connected with the midpoint of the first strip-shaped pattern along the first direction, and the second direction is perpendicular to the first direction.
According to the technical scheme, the mask splicing condition is monitored according to the electrical performance test result, the accuracy is higher, the pattern alignment condition can be accurately judged, and the monitoring position is increased for on-line defect scanning.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 4, a schematic top view of an embodiment of a mask of the present invention is shown.
In this embodiment, the mask plate includes: at least 1 metrology pattern structure 100. Wherein, the measurement pattern structure 100 comprises: at least 1 of comb pattern 110, semi-chain pattern 120, and T-shaped pattern 130.
In some embodiments of the present invention, each of the metrology pattern structures 100 includes: a plurality of comb pattern 110, semi-chain pattern 120, and T-shaped pattern 130; the patterns are sequentially and separately arranged along the first direction X.
Specifically, in the embodiment shown in FIG. 4, measurement pattern structure 100 includes comb pattern 110, semi-chain pattern 120, and T-shaped pattern 130; comb pattern 110, semi-chain pattern 120, and T-shaped pattern 130 are sequentially and separately arranged along a first direction X.
Wherein comb pattern 110 includes: a connection stripe pattern 111 extending in the first direction X; a plurality of comb-shaped patterns 112 extending in the second direction Y, one end of the comb-shaped patterns 112 being connected to the connection bar-shaped patterns 111, the plurality of comb-shaped patterns 111 being disposed in parallel and apart along the first direction X, the second direction Y being perpendicular to the first direction.
It should be noted that the mask plate is used to splice with another mask plate to obtain a complete pattern. Therefore, the direction in which one end 112a of the comb-rack-shaped pattern 112 connected to the connection bar-shaped pattern 111 points to the other end 112b coincides with the direction in which the mask points to the other mask which is spliced.
In some embodiments of the present invention, a spacing a1 between adjacent comb-rack-like patterns 112 is greater than a dimension b1 of the comb-rack-like patterns 112 along the first direction X.
In the embodiment shown in FIG. 4, comb pattern 110 includes: 4 comb-rack-like patterns 112; the 4 comb-rack-shaped patterns 112 are arranged on the same side of the connecting strip-shaped pattern 111 in parallel at equal intervals; further, both ends of the connection bar pattern 111 are connected to 2 comb-shaped patterns 112, respectively.
In some embodiments of the present invention, the dimensions d1 of the plurality of comb-rack-shaped patterns 111 are equal along the second direction Y to ensure accuracy and precision of alignment measurement.
In comb pattern 110, at least one of width c1 of connection stripe pattern 111 and width b1 of comb-rack pattern 112 satisfies the minimum width of the pattern in the "pattern design rule"; the spacing a1 between adjacent comb-rack-like patterns 112 also satisfies the requirement of the minimum pitch of patterns in the "pattern design rule".
With continued reference to fig. 4, the semi-chain graphic 120 includes: at least 1U-shaped pattern 121 is arranged separately along the first direction X, and openings 123 of the U-shaped pattern 121 are oriented identically along a second direction Y, which is perpendicular to the first direction X.
As previously described, the mask is configured to be intermeshed with another mask to obtain a complete pattern. Therefore, the direction in which the bottom 121a of the opening 123 of the U-shaped pattern 121 points to the top 121b coincides with the direction in which the mask points to another mask to be spliced.
In some embodiments of the present invention, semi-chain graphic 120 includes: the plurality of U-shaped patterns 121, and the plurality of U-shaped patterns 121 are identical in shape. The plurality of U-shaped patterns 121 are equally spaced along the first direction X. In the embodiment shown in fig. 4, the semi-chain pattern 120 includes: 3U-shaped patterns 121. The 3U-shaped patterns 121 are arranged at equal intervals.
In some embodiments of the present invention, the dimension a2 of the opening 123 of the U-shaped pattern 121 and the spacing b2 between adjacent U-shaped patterns 121 are equal along the first direction X, so that the openings 123 of the 2U-shaped patterns 121 can be relatively aligned and connected end to end.
Furthermore, as shown in fig. 4, in some embodiments of the present invention, the semi-chain graphic 120 further includes: the tail stripe pattern 122 extending along the second direction Y is located at one side of the plurality of U-shaped patterns 121 along the first direction X, that is, the tail stripe pattern 122 is one side of all the U-shaped patterns 121.
In some embodiments of the present invention, the distance c2 between the tail stripe pattern 122 and the plurality of U-shaped patterns 121 and the dimension a2 of the opening 123 of the U-shaped pattern 121 are equal along the first direction X, so that the tail stripe pattern 121 and the U-shaped pattern 121 adjacent thereto can be aligned with the head-to-tail ends of the other U-shaped pattern 121.
In the semi-chain pattern 120, at least one of the width of the U-shaped pattern 121 and the width of the tail stripe pattern 121 satisfies the minimum width of the pattern in the "pattern design rule". In addition, the interval b2 between the adjacent U-shaped patterns 121 and the interval c2 between the tail stripe pattern 121 and the U-shaped patterns 121 adjacent thereto also satisfy the requirement of the minimum pitch of patterns in the "pattern design rule".
The U-shaped pattern 121 includes a first segment 121a and 2 second segments 121b extending along a first direction X, wherein the 2 second segments 121b extend along a second direction Y, and the 2 second segments 121b are respectively connected to two ends of the first segment 121 a. The width of the U-shaped pattern 121, i.e., the width d2 of the first segment 121a and the width e2 of the second end 121b, so the width d2 of the first segment 121a and the width e2 of the second end 121b also satisfy the minimum width of the pattern in the "pattern design rule".
It should be further noted that in some embodiments of the present invention, openings 123 of plurality of U-shaped patterns 121 in semi-chain pattern 120 are oriented in the same direction as openings of comb pattern 110. As shown in fig. 4, the direction of the bottom 121a of the opening 123 of the U-shaped pattern 121 toward the top 121b coincides with the direction of the one end 112a of the comb-rack-shaped pattern 112 connected to the connection bar-shaped pattern 111 toward the other end 112 b.
With continued reference to fig. 4, the t-shaped graphic 130 includes: a first stripe pattern 131 extending in a first direction X; and a second stripe pattern 132 extending in the second direction Y, one end of the second stripe pattern 132 being connected to a midpoint of the first stripe pattern 131 in the first direction X.
In the present embodiment, in the semi-chain pattern 120, the width of the T-shaped pattern 130 satisfies the "photolithography pattern stitching design rule", that is, the width of at least one of the width a3 of the first stripe pattern 131 and the width b3 of the second stripe pattern 132 satisfies the requirement of the minimum width of the pattern in the "pattern design rule".
In addition, in the T-shaped pattern 130, the direction in which the first stripe pattern 131 points to the second stripe pattern 132 coincides with the direction in which the opening 123 of the U-shaped pattern 121 is formed, that is, the direction in which the first stripe pattern 131 points to the second stripe pattern 132 coincides with the direction in which the bottom 121a of the opening 123 of the U-shaped pattern 121 points to the top 121 b.
It should be noted that the mask plate further includes: a functional pattern and a test pattern, wherein the functional pattern is used for forming a functional structure with an electrical function, and the test pattern is used for forming a test structure for testing the functional structure; the test pattern includes: at least 1 measurement pattern structure. In other embodiments of the present invention, the functional graphics include: at least 1 measurement pattern structure.
Correspondingly, the invention further provides a mask assembly.
Referring to fig. 5, a schematic top view of one embodiment of a mask assembly of the present invention is shown.
In this embodiment, the mask assembly includes: the first mask plate and the second mask plate are the mask plates of the invention; when the first mask plate and the second mask plate are spliced to form a complete pattern, at least 1 measurement pattern structure 200 of the first mask plate corresponds to at least 1 measurement pattern structure 300 of the second mask plate one by one.
It should be noted that fig. 5 shows a schematic top view structure of 1 measurement pattern structure of the first mask plate and two corresponding side pattern structures of the second mask plate when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern.
It should be further noted that each measurement pattern structure includes: at least 1 measurement pattern, the measurement pattern is at least 1 of comb pattern, semi-chain pattern and T-shaped pattern.
In some embodiments, each metrology pattern structure includes: a plurality of measurement patterns; when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, a plurality of measurement patterns in the measurement pattern structure of the first mask plate are in one-to-one correspondence with a plurality of measurement patterns in the measurement pattern structure of the corresponding second mask plate.
Specifically, in the embodiment shown in fig. 5, the measurement pattern structure 200 of the first mask includes: comb pattern 210, semi-chain pattern 220, and T-pattern 230; correspondingly, the measurement pattern structure 300 of the second mask plate also includes: comb pattern 310, semi-chain pattern 320, and T-shaped pattern 330.
Moreover, when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, the comb pattern 210, the half-chain pattern 220, and the T-shaped pattern 230 in the measurement pattern structure 200 of the first mask plate are in one-to-one correspondence with the comb pattern 310, the half-chain pattern 320, and the T-shaped pattern 330 in the measurement pattern structure 300 of the second mask plate.
In some embodiments of the present invention, comb pattern 210 in metrology pattern structure 200 of the first mask plate includes: a connection stripe pattern 211 extending in the first direction X; the plurality of comb-shaped patterns 212 extending in the second direction Y, one end of the comb-shaped patterns 212 being connected to the connection bar-shaped patterns 211, the plurality of comb-shaped patterns 212 being disposed in parallel and apart in the first direction X, the second direction Y being perpendicular to the first direction.
Correspondingly, comb pattern 310 in metrology pattern structure 300 of the second mask plate, corresponding to comb pattern 210 in metrology pattern structure 200 of the first mask plate, includes: a connection stripe pattern 311 extending in the first direction X; a plurality of comb-shaped patterns 312 extending in the second direction Y, one end of the comb-shaped patterns 312 being connected to the connection bar-shaped patterns 311, the plurality of comb-shaped patterns 312 being arranged in parallel and apart in the first direction X.
As shown in fig. 5, when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, in the corresponding measurement pattern structure 200 of the first mask plate and the corresponding measurement pattern structure 300 of the second mask plate, the plurality of comb-shaped patterns 212 in the comb pattern 210 and the plurality of comb-shaped patterns 312 in the comb pattern 310 are alternately arranged, that is, the plurality of comb-shaped patterns 212 are respectively located between the gaps of the adjacent comb-shaped patterns 312, and correspondingly, the plurality of comb-shaped patterns 312 are also respectively located between the gaps of the adjacent comb-shaped patterns 212.
Specifically, in the embodiment shown in fig. 5, in the measurement pattern structure 200 of the first mask, the comb pattern 210 includes: 4 comb-rack-like patterns 212; in metrology pattern structure 300 of the second mask, comb pattern 310 includes: 3 comb-rack-like patterns 312.
In the present embodiment, the 4 comb-rack-like patterns 212 have 3 gaps, and the 3 comb-rack-like patterns 312 are located in the 3 gaps of the 4 comb-rack-like patterns 212; the 3 comb-shaped patterns 312 have 2 gaps, 2 of the 4 comb-shaped patterns 212 are respectively located in 2 gaps of the 3 comb-shaped patterns 312, and the other 2 of the 4 comb-shaped patterns 212 are respectively located at both sides of the 3 comb-shaped patterns 312.
It should be noted that, in the embodiment shown in fig. 5, the lengths of the connection stripe patterns 211 of the comb pattern 210 in the measurement pattern structure 200 of the first mask plate and the lengths of the connection stripe patterns 311 of the comb pattern 310 in the measurement pattern structure 300 of the second mask plate are equal. Therefore, in the first direction X, the connection stripe pattern 311 of the comb pattern 310 in the measurement pattern structure 300 of the second mask plate extends to one side of the outermost comb-rack-like pattern 212.
With continued reference to fig. 5, in some embodiments of the present invention, the semi-chain pattern 220 in the metrology pattern structure 200 of the first reticle includes: at least 1U-shaped pattern 221 discretely arranged along the first direction X; correspondingly, the half-chain pattern 320 in the measurement pattern structure 300 of the second mask plate corresponding to the half-chain pattern 220 in the measurement pattern structure 200 of the first mask plate includes: at least 1U-shaped pattern 321 arranged separately along the first direction X.
As shown in fig. 5, when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, at least 1U-shaped pattern 221 of the half-chain pattern 210 of the first mask plate and at least 1U-shaped pattern 321 of the half-chain pattern 310 of the second mask plate are connected end to end in the corresponding measurement pattern structure 200 of the first mask plate and measurement pattern structure 300 of the second mask plate.
Specifically, the at least 1U-shaped pattern 221 of the half-chain pattern 210 of the first mask plate and the at least 1U-shaped pattern 321 of the half-chain pattern 310 of the second mask plate are partially overlapped to be connected, so that the at least 1U-shaped pattern 221 of the half-chain pattern 210 of the first mask plate and the half-chain pattern 310 of the second mask plate form a square wave pattern.
In the embodiment shown in fig. 5, the second U-shaped pattern (e.g. the dashed box 342 in fig. 5) and the third U-shaped pattern (e.g. the dashed box 343 in fig. 5) are respectively located at two sides of the first U-shaped pattern (e.g. the dashed box 241 in fig. 5) along the first direction X, wherein the first U-shaped pattern is 1U-shaped pattern 221 in the semi-chain pattern 210; the second and third U-shaped patterns are 2U-shaped patterns 221 in the semi-chain pattern 310.
In this embodiment, 1 second segment 221b of the first U-shaped pattern overlaps with a portion of the second U-shaped pattern adjacent to the second segment 321b of the first U-shaped pattern to connect; the other 1 second segment 221b of the first U-shaped pattern overlaps with a portion of the second segment 321b of the third U-shaped pattern adjacent to the first U-shaped pattern to connect.
In some embodiments of the present invention, semi-chain graphic 220 further comprises: a tail stripe pattern 222 extending in the second direction Y; the semi-chain graphic 320 further includes: a tail pattern 322 extending in the second direction Y.
Specifically, along the first direction X, the tail bar patterns 222 of the semi-chain pattern 220 and the tail bar patterns 322 of the semi-chain pattern 320 are located at two sides of the plurality of U-shaped patterns 221 and the plurality of U-shaped patterns 321, respectively.
Also, the tail bar pattern 222 of the half-chain pattern 220 is partially overlapped with the outermost 1 second segments 321b of the U-shaped pattern 321 furthest from the tail bar pattern 322 to be connected; the tail bar pattern 322 of the half-chain pattern 320 is partially overlapped with the outermost 1 second segment 221b of the U-shaped pattern 221 furthest from the tail bar pattern 222 to be connected.
With continued reference to fig. 5, in some embodiments of the invention, the T-pattern 230 in the metrology pattern structure 200 of the first reticle includes: a first stripe pattern 231 extending along a first direction X; a second stripe pattern 232 extending in a second direction Y; the T-shaped pattern 330 in the metrology pattern structure 300 of the second reticle includes: a first stripe pattern 331 extending along a first direction X; a second stripe pattern 332 extending in the second direction Y.
In this embodiment, when the first mask plate and the second mask plate are spliced to form a complete pattern, the second stripe pattern 232 of the T-shaped pattern 230 of the first mask plate and the second stripe pattern 332 of the T-shaped pattern 330 of the second mask plate are correspondingly connected in the corresponding measurement pattern structure 200 of the first mask plate and measurement pattern structure 300 of the second mask plate.
Specifically, the second stripe pattern 232 of the T-shaped pattern 230 of the first mask plate and the second stripe pattern 332 of the T-shaped pattern 330 of the second mask plate are connected by partially overlapping.
As shown in fig. 6, the first mask plate includes: the first test pattern 250 for forming the first test structure, the first test pattern 250 includes: at least 1 measurement pattern structure 251; as shown in fig. 7, the second mask plate includes: a second test pattern 350 for forming a second test structure, the second test pattern 350 comprising: at least 1 metrology pattern structure 351.
In addition, as shown in fig. 8, the first test pattern 250 further includes: a first alignment pattern 252; the second test pattern 350 further includes: a second alignment pattern 352; the first alignment pattern 252 and the second alignment pattern 352 are used for alignment to achieve the stitching of the first mask plate and the second mask plate. Specifically, in the embodiment shown in fig. 8, when the first mask plate and the second mask plate are spliced to form a complete pattern, the first alignment pattern 252 is located within the range of the corresponding second alignment pattern 352.
In this embodiment, when the first mask plate and the second mask plate are spliced to form a complete pattern, the measurement pattern structure 251 of the first mask plate and the measurement pattern structure 351 of the corresponding second mask plate are partially overlapped to form an overlapping region 400 (as shown in fig. 5).
Correspondingly, the invention further provides a method for forming the semiconductor structure.
In this embodiment, the semiconductor structure forming method includes: providing a substrate and a mask assembly, wherein the mask assembly is the mask assembly of the invention; transferring the pattern of the mask assembly onto a substrate to form a semiconductor structure; wherein the step of transferring the pattern of the mask assembly onto the substrate comprises: transferring the pattern of the lower mask plate to a substrate to form a first positioning structure, wherein the lower mask plate is one of the first mask plate and the second mask plate; after the pattern of the lower-layer mask plate is transferred, transferring the pattern of the upper-layer mask plate to the substrate to form a second positioning structure, wherein the upper-layer mask plate is the other one of the first mask plate and the second mask plate.
The substrate is used for providing a process operation platform and also used for providing a process foundation for the subsequent steps.
In some embodiments of the invention, the substrate comprises: a substrate and a semiconductor structure located on the substrate. Wherein the material of the substrate is selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the material of the substrate may also be selected from silicon, germanium, gallium arsenide or silicon germanium compounds; the material of the substrate may also be other semiconductor materials. The invention is not limited in this regard. In other embodiments of the invention, the base may also include only the substrate.
In this embodiment, the mask assembly is used to transfer a pattern onto a substrate.
The mask assembly is the mask assembly of the present invention. Therefore, the specific technical scheme of the mask assembly refers to the foregoing embodiment of the mask assembly, and the disclosure is not repeated here.
The step of transferring the pattern of the mask assembly onto the substrate is used to effect the pattern transfer.
The mask plate further includes: and a functional pattern adapted to be transferred to a substrate to form a functional structure.
In the step of transferring the image of the mask assembly onto the substrate, the functional pattern of the first mask plate and at least 1 measurement pattern structure are simultaneously transferred onto the substrate; the functional pattern and at least 1 measurement pattern structures of the second mask plate are transferred to the substrate at the same time. Referring to fig. 5, a schematic top view of a mask assembly according to an embodiment of the method for forming a semiconductor structure of the present invention is shown after transferring the pattern of the mask assembly onto a substrate.
In some embodiments of the invention, the step of transferring the pattern of the mask assembly onto the substrate comprises: at least 1 of forming an active region, forming a polysilicon layer, forming a metal layer, and forming a metal silicide layer.
Because the functional pattern of the mask plate and at least 1 measurement pattern structure are transferred onto the substrate at the same time, the functional structure formed by transferring the functional pattern onto the substrate is the same type of semiconductor structure as the semiconductor structure formed by transferring at least 1 measurement pattern structure onto the substrate.
Specifically, when the step of transferring the pattern of the mask assembly onto the substrate is a step of forming an active region with doping, the functional structure formed by transferring the functional pattern onto the substrate is an active region with doping, and the semiconductor structure formed by at least 1 measurement pattern structure is also an active region with doping; when the step of transferring the pattern of the mask assembly onto the substrate is a step of forming a doped polysilicon layer, the functional structure formed by transferring the functional pattern onto the substrate is a doped polysilicon layer, and the semiconductor structure formed by at least 1 measurement pattern structure is also a doped polysilicon layer; when the step of transferring the pattern of the mask assembly onto the substrate is a step of forming a metal layer, the functional structure formed by transferring the functional pattern onto the substrate is a metal layer, and the semiconductor structure formed by at least 1 measurement pattern structure is also a metal layer; when the step of transferring the pattern of the mask assembly onto the substrate is a step of forming a metal silicide layer, the functional structure formed by transferring the functional pattern onto the substrate is the metal silicide layer, and the semiconductor structure formed by at least 1 measurement pattern structure is also the metal silicide layer.
In the step of transferring the pattern of the upper layer mask plate to the substrate, the pattern of the upper layer mask plate is aligned with the pattern of the lower layer mask plate transferred to the substrate, so that the pattern of the upper layer mask plate and the pattern of the lower layer mask plate are spliced to form a complete mask pattern.
When the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, the patterns of at least 1 measurement pattern structure of the first mask plate and the patterns of at least 1 measurement pattern structure of the second mask plate are in one-to-one correspondence, that is, in the complete mask pattern, the patterns of at least 1 measurement pattern structure of the first mask plate and the patterns of at least 1 measurement pattern structure of the second mask plate are in one-to-one correspondence.
In some embodiments of the present invention, in the step of transferring the pattern of the lower mask plate onto the substrate, the lower mask plate is the first mask plate; in the step of transferring the pattern of the upper layer mask plate onto the substrate, the upper layer mask plate is a second mask plate.
Therefore, in the step of transferring the pattern of the lower mask plate to the substrate to form at least 1 first positioning structure, the first positioning structure is formed by transferring at least 1 measurement pattern structure of the first mask plate to the substrate; in the step of transferring the pattern of the upper layer mask plate onto the substrate to form at least 1 second positioning structure, at least 1 measurement pattern structure of the second mask plate corresponds to at least 1 first positioning structure one by one.
In the step of transferring the pattern of the upper layer mask plate onto the substrate to form a second positioning structure, the second positioning structure is formed by transferring at least 1 measurement pattern structure of the second mask plate onto the substrate; so that at least 1 second positioning structure corresponds to at least 1 first positioning structure one by one.
As shown in fig. 9, in some embodiments of the present invention, a measurement pattern structure in a mask for forming a semiconductor structure includes: at least a plurality of comb patterns, semi-chain patterns, and T-shaped patterns; therefore, the first positioning structure 500 includes: first comb positioning pattern 510, first half-chain positioning pattern 520, and first T-shaped positioning pattern 530; the second positioning structure 600 includes: second comb positioning pattern 610, second half-chain positioning pattern 620, and second T-shaped positioning pattern 630.
Correspondingly, the invention also provides a semiconductor structure which is formed by the method for forming the semiconductor structure.
The semiconductor structure is formed by the method for forming a semiconductor structure according to the present invention, so the specific technical scheme of the semiconductor structure refers to the embodiment of the method for forming a semiconductor structure described above, and the disclosure is not repeated here.
Note that the semiconductor structure includes: the test pattern is transferred to a test key formed on the substrate, and at least 1 first positioning structure and at least 1 second positioning structure are located in the test structure. In other embodiments of the present invention, the semiconductor structure has a functional structure formed by transferring a functional pattern onto a substrate, and at least 1 first positioning structure and at least 1 second positioning structure may also be located in the functional structure.
As shown in fig. 9, the semiconductor structure includes: at least 1 first positioning structure 500, wherein the first positioning structure 500 is formed by transferring at least 1 measurement pattern structure of a first mask plate onto a substrate; at least 1 second positioning structure 600, wherein the second positioning structure 600 is formed by transferring at least 1 measurement pattern structure of the second mask plate onto the substrate; at least 1 first positioning structure 500 and at least 1 second positioning structure 600 are in one-to-one correspondence.
In some embodiments of the present invention, a metrology pattern structure in a mask for forming a semiconductor structure includes: at least a plurality of comb patterns, semi-chain patterns, and T-shaped patterns; therefore, the first positioning structure 500 includes: first comb positioning pattern 510, first half-chain positioning pattern 520, and first T-shaped positioning pattern 530; the second positioning structure 600 includes: second comb positioning pattern 610, second half-chain positioning pattern 620, and second T-shaped positioning pattern 630.
As shown in fig. 9, in some embodiments of the present invention, each positioning structure is connected to one pad to implement loading of a voltage signal or a current signal; a plurality of positioning patterns in the same positioning structure are connected with the corresponding welding pads through different metal layers.
Specifically, in first positioning structure 500, first comb-shaped positioning pattern 510, first half-chain positioning pattern 520, and first T-shaped positioning pattern 530 are connected to bonding pad 551, bonding pad 552, and bonding pad 553, respectively, by different metal layers; in the second positioning structure 600, the second comb-shaped positioning pattern 610, the second half-chain positioning pattern 620 and the second T-shaped positioning pattern 630 are connected to the bonding pads 651, 652 and 653 respectively by different metal layers.
In some embodiments of the present invention, all of the positioning structures in the semiconductor structure are connected to the corresponding pads through different metal layers.
In the embodiment shown in fig. 9, first comb-shaped positioning pattern 510, first half-chain positioning pattern 520, and second comb-shaped positioning pattern 610, second half-chain positioning pattern 620, and second T-shaped positioning pattern 630 in first positioning structure 500 and first T-shaped positioning pattern 530 and second positioning structure 600 are connected to bonding pad 551, bonding pad 552, bonding pad 553, bonding pad 651, bonding pad 652, and bonding pad 653, respectively, by different metal layers.
In some embodiments of the present invention, in the corresponding first positioning structure and second positioning structure, a distance between two pads of the corresponding positioning pattern is equal to a distance between needle points on the test needle card.
In the embodiment shown in FIG. 9, the distance between bond pad 551 of first comb pattern 510 and bond pad 651 of second comb pattern 610, the distance between bond pad 552 of first half-chain pattern 520 and bond pad 652 of second half-chain pattern 620, and the distance between bond pad 553 of first T-shaped pattern 530 and bond pad 653 of second T-shaped pattern 630 are all equal to the distance between the tips on a test pin card.
In addition, the invention also provides a measuring method of the semiconductor structure, wherein the semiconductor structure is the semiconductor structure of the invention.
Referring to fig. 10, a flow chart of an embodiment of a method for measuring a semiconductor structure according to the present invention is shown.
Referring in conjunction to fig. 9, a schematic top view of a semiconductor structure is shown.
As shown in fig. 9, the semiconductor structure includes: at least 1 first positioning structure 500, wherein the first positioning structure 500 is formed by transferring at least 1 measurement pattern structure of a first mask plate onto a substrate; at least 1 second positioning structure 600, wherein the second positioning structure 600 is formed by transferring at least 1 measurement pattern structure of the second mask plate onto the substrate; at least 1 first positioning structure 500 and at least 1 second positioning structure 600 are in one-to-one correspondence; as shown in fig. 9, the measurement method includes: step S100 is performed to measure the splice offset according to at least 1 first positioning structure 500 and at least 1 second positioning structure 600.
In some embodiments of the present invention, a metrology pattern structure includes: a comb pattern; the first positioning structure 500 includes: first comb-shaped positioning pattern 510, first comb-shaped positioning pattern 510 is formed by transferring the comb-shaped pattern of the measurement pattern structure of the first mask plate onto the substrate; the corresponding second positioning structure 600 includes: second comb-shaped positioning pattern 610. Second comb-shaped positioning pattern 610 is formed by transferring the comb-shaped pattern of the corresponding measurement pattern structure of the second mask plate onto the substrate.
Therefore, the step of executing the step S100 to measure the splice offset includes: step S110 is performed to measure at least 1 of leakage current and breakdown voltage between first comb positioning pattern 510 and second comb positioning pattern 610 to obtain a splice offset.
As shown in fig. 9, first comb positioning pattern 510 and second comb positioning pattern 610 can form a capacitive structure therebetween; the offset of pattern splicing can influence the distance between structures formed by the comb-rack-shaped patterns on different mask plates and the thickness of a dielectric layer between the structures formed by the comb-rack-shaped patterns on different mask plates, so that the leakage current or breakdown voltage between the two structures is influenced; the details of the pattern stitching can thus be obtained by measuring at least 1 of the leakage current and breakdown voltage between the two.
Specifically, a voltage signal is applied to first comb positioning pattern 510 and second comb positioning pattern 610, respectively, to measure leakage current, or a current signal is applied to first comb positioning pattern 510 and second comb positioning pattern 610, respectively, to measure breakdown voltage, to obtain a splice offset.
With continued reference to FIG. 5, in some embodiments of the invention, the metrology pattern structure includes: a semi-chain pattern; the first positioning structure 500 includes: the first half-chain positioning pattern 520, wherein the first half-chain positioning pattern 520 is formed by transferring a half-chain pattern of the measurement pattern structure of the first mask plate onto the substrate; the corresponding second positioning structure 600 includes: and a second half-chain positioning pattern 620, which is formed by transferring the half-chain pattern of the corresponding measurement pattern structure of the second mask plate onto the substrate.
Therefore, the step of executing the step S100 to measure the splice offset includes: step S120 is performed to measure the resistance values of the first and second half-chain positioning patterns 520 and 620 to obtain the splice offset.
As shown in fig. 9, the first half-chain positioning pattern 520 and the second half-chain positioning pattern 620 are connected to each other to form a conductive connection line; the offset of pattern splicing can influence the overlapping condition between structures formed by U-shaped patterns on different mask plates and the width and length between structures formed by the U-shaped patterns on different mask plates, thereby influencing the resistance value between the two structures; therefore, the specific situation of pattern stitching can be obtained by measuring the resistance value between the two.
Specifically, voltage signals are applied to the first and second half-chain positioning patterns 520 and 620, respectively, to measure resistance, thereby obtaining a splice offset.
With continued reference to FIG. 5, in some embodiments of the invention, the metrology pattern structure includes: a T-shaped pattern; the first positioning structure 500 includes: the first T-shaped positioning pattern 530, wherein the first T-shaped positioning pattern 530 is formed by transferring a T-shaped pattern of the measurement pattern structure of the first mask plate onto the substrate; the corresponding second positioning structure 600 includes: the second T-shaped positioning pattern 630, the second T-shaped positioning pattern 630 is formed by transferring the T-shaped pattern of the corresponding measurement pattern structure of the second mask plate onto the substrate.
Therefore, the step of executing the step S100 to measure the splice offset includes: step S130 is performed to measure the resistance values of the first and second T-shaped positioning patterns 530 and 630 to obtain a splice offset.
As shown in fig. 9, the first T-shaped positioning pattern 530 and the second T-shaped positioning pattern 630 are connected to each other to form a conductive connection line; the offset of the pattern stitching may affect the overlapping condition between the first T-shaped positioning pattern 530 and the second T-shaped positioning pattern 630, and may affect the width and length of the first T-shaped positioning pattern 530 and the second T-shaped positioning pattern 630, thereby affecting the resistance value therebetween; therefore, the specific situation of pattern stitching can be obtained by measuring the resistance value between the two.
Specifically, voltage signals are applied to the first and second T-shaped positioning patterns 530 and 630, respectively, to measure resistance, thereby obtaining a splice offset.
In summary, the mask plate includes: at least 1 measurement pattern structure, the measurement pattern structure includes: at least 1 of a comb pattern, a semi-chain pattern, and a T-pattern; when measuring the semiconductor structure formed by the mask assembly formed by the mask plate, measuring the splicing offset according to at least 1 first positioning pattern and at least 1 second positioning pattern. According to the electrical performance test result, the mask splicing condition is monitored, the accuracy is higher, the pattern alignment condition can be accurately judged, and the monitoring position is increased for on-line defect scanning.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A mask blank, comprising: at least 1 metrology pattern structure, the metrology pattern structure comprising: at least 1 of a comb pattern, a semi-chain pattern, and a T-pattern; wherein the comb pattern comprises: a connection stripe pattern extending in a first direction; the plurality of comb-rack-shaped patterns extend along a second direction, one end of each comb-rack-shaped pattern is connected with each connecting strip-shaped pattern, the plurality of comb-rack-shaped patterns are arranged in a separated and parallel mode along a first direction, and the second direction is perpendicular to the first direction;
The semi-chain pattern includes: at least 1U-shaped graph which is arranged along the first direction in a separated mode, and the openings of the U-shaped graphs are oriented to be the same along the second direction;
the T-shaped pattern includes: a first stripe pattern extending along the first direction; and one end of the second strip-shaped pattern is connected with the midpoint of the first strip-shaped pattern along the first direction.
2. The mask plate of claim 1, wherein each of the metrology pattern structures comprises: a plurality of patterns among a comb pattern, a semi-chain pattern, and a T-pattern;
the plurality of patterns are sequentially and separately arranged along the first direction.
3. The mask plate according to claim 1, wherein a pitch between adjacent comb-rack-like patterns is larger than a size of the comb-rack-like pattern in the first direction.
4. The mask plate according to claim 1, wherein the semi-chain pattern comprises: the plurality of U-shaped patterns are identical in shape.
5. The mask plate according to claim 4, wherein in the first direction, a size of an opening of the U-shaped pattern is equal to a pitch between adjacent U-shaped patterns.
6. The mask plate according to claim 1, wherein the semi-chain pattern further comprises: and the chain tail strip-shaped patterns extend along the second direction, and are positioned on one side of the plurality of U-shaped patterns along the first direction.
7. The mask plate of claim 6, wherein a distance between the tail pattern and the plurality of U-shaped patterns and a size of an opening of the U-shaped pattern are equal in the first direction.
8. A mask assembly, comprising: a first mask blank and a second mask blank, both of which are as claimed in any one of claims 1 to 7;
when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, the patterns of at least 1 measurement pattern structure of the first mask plate and the patterns of at least 1 measurement pattern structure of the second mask plate are in one-to-one correspondence.
9. The mask assembly of claim 8, wherein the metrology pattern structure comprises: a comb pattern;
when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, the comb-shaped patterns of the first mask plate and the comb-shaped patterns of the second mask plate are alternately arranged in the corresponding patterns of the measuring pattern structure of the first mask plate and the corresponding patterns of the measuring pattern structure of the second mask plate.
10. The mask assembly of claim 8, wherein the metrology pattern structure comprises: a semi-chain pattern;
when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, at least 1U-shaped pattern of the half-chain pattern of the first mask plate and at least 1U-shaped pattern of the half-chain pattern of the second mask plate are correspondingly connected end to end in the corresponding patterns of the measurement pattern structure of the first mask plate and the measurement pattern structure of the second mask plate.
11. The mask assembly of claim 8, wherein the metrology pattern structure comprises: a T-shaped pattern;
when the patterns of the first mask plate and the patterns of the second mask plate are spliced to form a complete mask pattern, the corresponding patterns of the measurement pattern structure of the first mask plate and the corresponding patterns of the measurement pattern structure of the second mask plate are correspondingly connected with the second strip patterns of the T-shaped patterns of the first mask plate and the second strip patterns of the T-shaped patterns of the second mask plate.
12. A method of forming a semiconductor structure, comprising:
Providing a substrate and a mask assembly as claimed in any one of claims 8 to 11;
transferring the pattern of the mask assembly onto the substrate to form a semiconductor structure;
wherein transferring the pattern of the mask assembly onto the substrate comprises: transferring the pattern of a lower mask plate to the substrate to form a first positioning structure, wherein the lower mask plate is one of the first mask plate and the second mask plate; after the pattern of the lower-layer mask plate is transferred, transferring the pattern of the upper-layer mask plate to the substrate to form a second positioning structure, wherein the upper-layer mask plate is the other one of the first mask plate and the second mask plate.
13. The method of forming of claim 12, wherein transferring the pattern of the mask assembly onto the substrate further comprises: at least 1 of forming an active region having a doping, forming a polysilicon layer having a doping, forming a metal layer, and forming a metal silicide layer on the substrate.
14. A semiconductor structure formed by the method of forming a semiconductor structure of claim 12 or 13.
15. A method for measuring a semiconductor structure, comprising:
the semiconductor structure of claim 14, wherein splice offset is measured for a first location structure and a second location structure of the semiconductor structure, the first location structure and the second location structure corresponding.
16. The method of claim 15, wherein the measurement pattern structure comprises: a comb pattern;
the first positioning structure includes: a first comb-shaped positioning pattern, wherein the first comb-shaped positioning pattern is formed by transferring a comb-shaped pattern of a measurement pattern structure of the first mask plate onto the substrate;
the corresponding second positioning structure comprises: a second comb-shaped positioning pattern, wherein the second comb-shaped positioning pattern is formed by transferring a comb-shaped pattern of a corresponding measuring pattern structure of the second mask plate onto the substrate;
the step of measuring the splice offset includes: at least 1 of leakage current and breakdown voltage between the first and second comb-positioning patterns is measured to obtain a splice offset.
17. The method of claim 15, wherein the measurement pattern structure comprises: a semi-chain pattern;
The first positioning structure includes: the first half-chain positioning pattern is formed by transferring a half-chain pattern of the measurement pattern structure of the first mask plate to the substrate;
the corresponding second positioning structure comprises: the second half-chain positioning pattern is formed by transferring the half-chain pattern of the corresponding measuring pattern structure of the second mask plate to the substrate;
the step of measuring the splice offset includes: and measuring resistance values of the first half-chain positioning pattern and the second half-chain positioning pattern to obtain a splicing offset.
18. The method of claim 15, wherein the measurement pattern structure comprises: a T-shaped pattern;
the first positioning structure includes: the first T-shaped positioning pattern is formed by transferring a T-shaped pattern of a measurement pattern structure of the first mask plate to the substrate;
the corresponding second positioning structure comprises: the second T-shaped positioning pattern is formed by transferring a T-shaped pattern of the corresponding measuring pattern structure of the second mask plate to the substrate;
The step of measuring the splice offset includes: and measuring resistance values of the first T-shaped positioning pattern and the second T-shaped positioning pattern to obtain a splicing offset.
CN202211033524.1A 2022-08-26 2022-08-26 Mask plate and assembly thereof, semiconductor structure, forming method and measuring method thereof Pending CN117666279A (en)

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CN202211033524.1A CN117666279A (en) 2022-08-26 2022-08-26 Mask plate and assembly thereof, semiconductor structure, forming method and measuring method thereof

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