CN116454070A - Semiconductor test structure and semiconductor device - Google Patents
Semiconductor test structure and semiconductor device Download PDFInfo
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- CN116454070A CN116454070A CN202310714630.4A CN202310714630A CN116454070A CN 116454070 A CN116454070 A CN 116454070A CN 202310714630 A CN202310714630 A CN 202310714630A CN 116454070 A CN116454070 A CN 116454070A
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- 238000012360 testing method Methods 0.000 title claims abstract description 363
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 58
- 229920005591 polysilicon Polymers 0.000 abstract description 58
- 238000005530 etching Methods 0.000 abstract description 27
- 238000000034 method Methods 0.000 abstract description 15
- 238000010586 diagram Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present application relates to a semiconductor test structure and a semiconductor device, the semiconductor test structure comprising: a substrate; the first test layer is arranged on the substrate; the first test layer comprises a plurality of first test strips which are arranged at intervals, and a substrate is exposed between two adjacent first test strips; the second test layer is arranged on the first test layer and the exposed substrate; the second test layer includes a plurality of second test strips disposed in spaced relation to one another, the orthographic projection of each second test strip on the substrate coinciding with the orthographic projection of at least one first test strip on the substrate. The pattern sizes of the overlapping region and the non-overlapping region formed by the second test strip overlapped on the first test strip can be respectively pushed to obtain the pattern sizes formed by the interval etching of the polysilicon gate lines on the wafer, so that the actual pattern sizes formed by the etching process of the polysilicon gate lines can be reflected.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor test structure and a semiconductor device.
Background
In semiconductor manufacturing, a pattern of a photomask design can be transferred to a wafer by a photolithographic etching process to form a correspondingly patterned material layer on the wafer. When the pattern width of a particular patterned material layer has a significant impact on the performance of the electronic component, dimensional errors in the pattern width need to be tightly controlled. Critical dimension test strips (english: critical Dimension bar, abbreviated as CD bar) capable of reacting to the pattern dimensions of the material layer are typically formed on the test area of the wafer, thereby monitoring the actual pattern width of the patterned material layer of the wafer.
When the process node is evolved to 55 or 40 nanometers and smaller, a new polysilicon gate line etching process is needed to break the polysilicon gate line due to the accuracy limitation of the photolithography etching process.
However, CD bar designed in the prior art often does not reflect the actual pattern size when monitoring the pattern size formed by the polysilicon etching process.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor test structure and a semiconductor device capable of reflecting the actual pattern size formed by the polysilicon gate line etching process, in view of the technical problems in the prior art.
To achieve the above object, in one aspect, the present application provides a semiconductor test structure.
A semiconductor test structure, the semiconductor test structure comprising:
a substrate;
a first test layer disposed on the substrate; the first test layer comprises a plurality of first test strips which are arranged at intervals, and the substrate is exposed between two adjacent first test strips;
a second test layer disposed on the first test layer and the exposed substrate; the second test layer comprises a plurality of second test strips arranged at intervals, and the orthographic projection of each second test strip on the substrate is overlapped with the orthographic projection part of at least one first test strip on the substrate.
In one embodiment, the substrate includes a first test zone and a second test zone, each of the first test strips in the first test zone extending in a first direction, each of the first test strips in the second test zone extending in a second direction, the first direction intersecting the second direction.
In one embodiment, the distance between two adjacent first test strips in the first test zone and the distance between two adjacent first test strips in the second test zone is a first critical dimension.
In one embodiment, each of the second test strips within the first test zone extends along a third direction that intersects the first direction; each of the second test strips within the second test zone extends in a fourth direction that intersects the second direction.
In one embodiment, the second direction is perpendicular to the first direction, the third direction is perpendicular to the first direction, and the fourth direction is perpendicular to the second direction.
In one embodiment, the first test zone includes a first sub-test zone and a second sub-test zone, the second test zone includes a third sub-test zone and a fourth sub-test zone, the length of the first test strip within the first sub-test zone is less than the length of the first test strip within the second sub-test zone, and the length of the first test strip within the third sub-test zone is less than the length of the first test strip within the fourth sub-test zone.
In one embodiment, the second test strip in the first sub-test zone extends to the second sub-test zone and the second test strip in the third sub-test zone extends to the fourth sub-test zone.
In one embodiment, the second sub-test zone and the fourth sub-test zone each comprise a sparse zone and a dense zone, the distance between two adjacent second test strips in the sparse zone being greater than the distance between two adjacent second test strips in the dense zone.
In one embodiment, the length of the second test strip in the sparse zone is less than the length of the second test strip in the dense zone.
In one embodiment, the second test strips in the sparse zone are arranged in an array, two adjacent rows of the second test strips are arranged in a staggered manner, and two adjacent columns of the second test strips are arranged in a staggered manner.
In another aspect, the present application also provides a semiconductor device.
The semiconductor device comprises a chip area and a test area, wherein the test area is provided with the semiconductor test structure.
The semiconductor test structure and the semiconductor device are characterized in that a first test layer comprising a plurality of first test strips arranged at intervals is arranged on a substrate, and a second test layer comprising a plurality of second test strips arranged at intervals is arranged on the first test layer, wherein the orthographic projection of the second test strips on the substrate is overlapped with the orthographic projection part of at least one first test strip on the substrate. Because the formed polysilicon gate lines are etched again, when the polysilicon gate lines are disconnected, the etched areas extend from one polysilicon gate line to the other polysilicon gate line through the intervals between the polysilicon gate lines, and at least two polysilicon gate lines are disconnected, and the difference of the etched areas affects the size of the etched areas to cause errors. The pattern sizes of the overlapping region and the non-overlapping region formed by the second test strip overlapped on the first test strip can be respectively represented, so that the pattern sizes formed by the interval etching of the polysilicon gate lines and the polysilicon gate lines can be reflected, and the actual pattern sizes formed by the etching process of the polysilicon gate lines can be reflected.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a polysilicon gate line etching process in one embodiment;
FIG. 2 is a cross-sectional view of one of the etched areas of FIG. 1 after the photoresist layer is applied;
FIG. 3 is a top view of the material layer of FIG. 2 after being etched through;
FIG. 4 is a schematic diagram of a related art critical dimension test strip;
FIG. 5 is a schematic diagram of a critical dimension test strip according to one embodiment of the present application;
FIG. 6 is a schematic diagram of a critical dimension test strip according to one embodiment of the present application;
FIG. 7 is a schematic diagram of a critical dimension test strip according to one embodiment of the present application;
FIG. 8 is a schematic diagram of a critical dimension test strip according to one embodiment of the present application;
FIG. 9 is a schematic diagram of a critical dimension test strip according to one embodiment of the present application;
FIG. 10 is a schematic diagram of a critical dimension test strip according to one embodiment of the present application;
FIG. 11 is a schematic diagram of a critical dimension test strip according to one embodiment of the present application;
FIG. 12 is a schematic diagram of a critical dimension test strip according to one embodiment of the present application;
fig. 13 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
Reference numerals illustrate:
100. a silicon substrate, 110, a polysilicon gate line, 120, an etched region, 130, a first oxide layer, 140, an insulating structure, 141, a second oxide layer, 142, a nitride layer, 143, a third oxide layer, 151, an organic distribution layer, 152, a bottom anti-reflective coating, 153, photoresist, 161, one test strip, 162, another test strip, 170, a chip, 180, a critical dimension test strip, 181, a test structure, 182, a test layer, 183, a test strip, 184, a fill layer;
210. a substrate 220, a first test strip, 230, a second test strip;
310. a first test region 311, a first sub-test region 312, a second sub-test region 3121, a first sparse region 3122, a first dense region 320, a second test region 321, a third sub-test region 322, a fourth sub-test region 3221, a second sparse region 3222, a second dense region;
1010. semiconductor device, 1020, die, 1030, semiconductor test structure.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
As described in the background art, as process nodes continue to move toward smaller dimensions, a new polysilicon gate line etching process is added to break the polysilicon gate lines. Referring to fig. 1, a plurality of polysilicon gate lines 110 are arranged horizontally at equal intervals, and one polysilicon gate line 110 includes a plurality of etching regions 120 for disconnecting the polysilicon gate lines 110. The extension direction of the etching region 120 is perpendicular to the extension direction of the polysilicon gate line 110. When the pitch of the polysilicon gate lines 110 is shortened, the etching region 120 cannot be formed simultaneously with the polysilicon gate lines 110 due to the accuracy limitation of the photolithography process, so that the polysilicon gate lines 110 are formed separately, and then the etching region 120 is formed by adding a new etching step to disconnect the polysilicon gate lines 110.
In practical application, when the polysilicon gate line is disconnected, a material layer such as photoresist is paved. Fig. 2 is a cross-sectional view of an etched region of fig. 1 after a photoresist layer is deposited, as shown in fig. 2, a polysilicon gate line 110 is disposed on a silicon substrate 100, and a first oxide layer 130 is further disposed between the silicon substrate 100 and the polysilicon gate line 110 to form a gate oxide layer. The polysilicon gate line 110 is provided with a plurality of insulating structures 140 spaced apart from each other, and each insulating structure 140 includes a second oxide layer 141, a nitride layer 142, and a third oxide layer 143 sequentially stacked on the polysilicon gate line 110. An organic distribution layer (english: organic Distribution Layer, abbreviated as ODL) 151, a Bottom Anti-reflective coating (english: bottom Anti-Reflective Coating, abbreviated as BARC) 152, and a Photoresist (PR) 153 are further sequentially stacked on the polysilicon gate line 110 exposed between the insulating structures 140 and the insulating structures 140.
After the material layers such as photoresist are paved, the material layers such as photoresist in the etching area are etched through by utilizing the photoetching technology, so that patterning of the material layers is realized. Fig. 3 is a top view of the material layer in fig. 2 after being etched through, as shown in fig. 3, the photoresist 153, the bottom anti-reflection coating 152 and the organic distribution layer 151 in the etching region 120 are sequentially removed by using a photolithography technique, so as to expose the third oxide layer 143 on the top of the insulating structure 140 and the polysilicon gate line 110 between the insulating structures 140.
To monitor the pattern width of the patterned material layer in the etched region, the critical dimension test strips include two types of test strips, one 161 corresponding to the polysilicon gate line 110 and the other 162 corresponding to the etched region 120, as shown in fig. 3.
Fig. 4 is a schematic structural diagram of a related art critical dimension test strip, as shown in fig. 4, a plurality of chips 170 are formed on a silicon substrate 100 at intervals, each chip 170 is provided with a plurality of polysilicon gate lines 110 and a plurality of etching regions 120 (not shown in fig. 4) as shown in fig. 1, and a critical dimension test strip 180 is located between two adjacent chips 170. Critical dimension test strip 180 includes test structures 181 that monitor etched region 120. The test structure 181 includes two test layers 182, each of the two test layers 182 includes a plurality of test strips 183 corresponding to the etching region 120, the test strips 183 are spaced apart from each other, a filling layer 184 corresponding to the polysilicon gate line 110 is disposed around the test strip 183 in one of the test layers 182, and no filling layer 184 is disposed around the test strip 183 in the one of the test layers 182. Such a test structure 181 does not accurately reflect the actual pattern size formed by the polysilicon gate line etching process.
For the reasons described above, in one embodiment, as shown in fig. 5, the present application provides a semiconductor test structure including a substrate 210, a first test layer, and a second test layer. The first test layer is disposed on the substrate 210, and the first test layer includes a plurality of first test strips 220 disposed at intervals, and the substrate 210 is exposed between two adjacent first test strips 220. The second test layer is disposed on the first test layer 220 and the exposed substrate 210, the second test layer including a plurality of second test strips 230 disposed at a distance from each other, an orthographic projection of each second test strip 230 on the substrate 210 coinciding with an orthographic projection portion of at least one first test strip 220 on the substrate 210.
Specifically, the base 210 includes a substrate. The material of the substrate may be silicon in a single crystal, polycrystalline or amorphous structure, silicon germanium (SiGe), silicon On Insulator (SOI) or the like. The upper surface of the substrate also includes an oxide layer. The first test layer includes a polysilicon layer and the second test layer includes a region for etching the first test layer. The distance of the first test strip 220 is set according to the actual requirements of the spacing between two adjacent polysilicon gate lines on the wafer. The line width of the first test strip 220 is set according to the actual requirements of the line width of the polysilicon gate lines on the wafer.
In the above embodiment, the first test layer including the plurality of first test strips disposed at a distance from each other is disposed on the substrate, and the second test layer including the plurality of second test strips disposed at a distance from each other is disposed on the first test layer, wherein the orthographic projection of the second test strips on the substrate coincides with the orthographic projection portion of the at least one first test strip on the substrate. Because the formed polysilicon gate lines are etched again, when the polysilicon gate lines are disconnected, the etched areas extend from one polysilicon gate line to the other polysilicon gate line through the intervals between the polysilicon gate lines, and at least two polysilicon gate lines are disconnected, and the difference of the etched areas affects the size of the etched areas to cause errors. The pattern sizes of the overlapping region and the non-overlapping region formed by the second test strip overlapped on the first test strip can be respectively represented, so that the pattern sizes formed by the interval etching of the polysilicon gate lines and the polysilicon gate lines can be reflected, and the actual pattern sizes formed by the etching process of the polysilicon gate lines can be reflected.
In one embodiment, as shown in FIG. 6, the substrate includes a first test zone 310 and a second test zone 320. Each first test strip 220 within the first test zone 310 extends in a first direction and each first test strip 220 within the second test zone 320 extends in a second direction, the first direction intersecting the second direction.
Illustratively, the second direction is perpendicular to the first direction.
Specifically, the line widths and line pitches of the first test strips 220 of the first test region 310 and the second test region 320 are identical, and the pattern structures formed by the first test strips 220 arranged at intervals are identical. The first test strip 220 within the first test zone 310 may be deflected generally 90 counter-clockwise or 90 clockwise to form the second test zone 320.
Illustratively, the first test strip 220 in the first test zone 310 extends in an up-down direction and the first test strip 220 in the second test zone 320 extends in a left-right direction.
In this embodiment, the extending directions of the corresponding first test strips in the first test area and the second test area are different, and the photolithography in different directions affects the size of the formed pattern when the wafer is subjected to photolithography, so that the size of the formed pattern in the actual pattern on the wafer can be tested.
In one embodiment, as shown in FIG. 7, the distance L1 between two adjacent first test strips 220 in the first test zone 310 and the distance L2 between two adjacent first test strips 220 in the second test zone 320 are the first critical dimension.
Specifically, the distance between adjacent first test strips 220, i.e., the first critical dimension, reflects the actual line spacing between polysilicon gate lines of the wafer.
In this embodiment, the line spacing between the actual polysilicon gate lines of the wafer can be obtained by measuring the distance between the first test strips of the first test area and the distance between the first test strips of the second test area, so as to ensure that the line spacing of the polysilicon gate lines is controlled within a certain range, so as not to reduce the quality of the electronic component.
In one embodiment, as shown in FIG. 8, each second test strip 230 within the first test zone 310 extends along a third direction that intersects the first direction; each of the second test strips 230 within the second test zone 320 extends in a fourth direction that intersects the second direction.
Illustratively, the third direction is perpendicular to the first direction and the fourth direction is perpendicular to the second direction.
Specifically, each second test strip 230 in the first test zone 310 is perpendicular to each first test strip 220, and as such, each second test strip 230 in the second test zone 320 is perpendicular to each first test strip 220. The pattern structure of the second test strip 230 and the first test strip 220 in the first test area 310 is the same as the pattern structure of the second test area 320.
Illustratively, the second test strip 230 of the first test zone 310 extends in a left-right direction and the first test strip 220 of the first test zone 310 extends in an up-down direction. The second test strip 230 of the second test zone 320 extends in the up-down direction, and the first test strip 220 of the second test zone 320 extends in the left-right direction.
In this embodiment, the second test strips in the first test area and the second test area are kept perpendicular to the extending direction of the first test strip, so that the situation that the etching direction of the polysilicon gate line in the actual wafer is perpendicular to the extending direction of the polysilicon gate line is met, and the actual pattern size formed on the wafer after the etching of the polysilicon gate line can be monitored.
In one embodiment, as shown in FIG. 9, the first test zone 310 includes a first sub-test zone 311 and a second sub-test zone 312, the second test zone 320 includes a third sub-test zone 321 and a fourth sub-test zone 322, the length of the first test strip 220 within the first sub-test zone 311 is less than the length of the first test strip 220 within the second sub-test zone 312, and the length of the first test strip 220 within the third sub-test zone 321 is less than the length of the first test strip 220 within the fourth sub-test zone 322.
Specifically, the length of the first test strip 220 of the first sub-test zone 311 is equal to the length of the first test strip 220 of the third sub-test zone 321, and the length of the first test strip 220 of the second sub-test zone 312 is equal to the length of the first test strip 220 of the fourth sub-test zone 322.
In this embodiment, by providing the first test strips with different lengths in the first sub-test area and the second sub-test area, and the third sub-test area and the fourth sub-test area, the area of the structure diagram of the critical dimension test strip can be saved while reflecting the actual pattern dimension.
In one embodiment, as shown in FIG. 10, the second test strip 230 in the first sub-test zone 311 extends to the second sub-test zone 312, and the second test strip 230 in the third sub-test zone 321 extends to the fourth sub-test zone 322.
Specifically, the second test strip 230 located at the center of the first sub-test zone 311 extends to the center of the second sub-test zone 312, and the second test strip 230 extending to the second sub-test zone 312 intersects the first test strip 220 of the second sub-test zone 312. Wherein the centers of the first sub-test area 311 and the second sub-test area 312 are located on the same straight line. Likewise, the second test strip 230 located at the center of the third sub-test zone 321 extends to the center of the fourth sub-test zone 322, and the second test strip 230 extending to the fourth sub-test zone 322 intersects the first test strip 220 of the fourth sub-test zone 322. Wherein the centers of the third sub-test area 321 and the fourth sub-test area 322 are located on the same straight line.
In one embodiment, as shown in FIG. 11, the second sub-test zone 312 and the fourth sub-test zone 322 each include a sparse zone and a dense zone, with the distance between two adjacent second test strips 230 in the sparse zone being greater than the distance between two adjacent second test strips 230 in the dense zone.
Specifically, the sparse region includes a first sparse region 3121 and a second sparse region 3221, and the dense region includes a first dense region 3122 and a second dense region 3222. Wherein the distances of two adjacent second test strips 230 in the first sparse region 3121 and the second sparse region 3221 are equal. The distances of two adjacent second test strips 230 in first dense area 3122 and second dense area 3222 are equal.
In this embodiment, since the density of the design pattern may affect the actual size of the wafer after photolithography, by setting the sparse region and the dense region in the second sub-test region and the fourth sub-test region, the sizes of the patterns of the sparse region and the dense region on the actual wafer can be correspondingly reflected.
In one embodiment, as shown in FIG. 12, the length of the second test strip 230 in the sparse zone is less than the length of the second test strip 230 in the dense zone.
Specifically, the first sparse zone 3121 and the first dense zone 3122 within the second subtest zone are exemplified. The second test strips 230 in the first sparse zone 3121 have a length L3 and the second test strips 230 in the first dense zone 3122 have a length L4. Wherein L3 is less than L4.
In this embodiment, by arranging the second test strips with different lengths in the sparse region and the dense region, the actual pattern size on the wafer when the polysilicon gate lines are etched with different lengths can be obtained correspondingly.
In one embodiment, with continued reference to fig. 12, the second test strips 230 in the sparse zone are arranged in an array, and two adjacent rows of second test strips 230 are staggered, and two adjacent columns of second test strips 230 are staggered.
Specifically, in the first row of the first sparse zone 3121, the second test strips 230 of length L3 are arranged equidistantly, and a first one of the second test strips 230 of the second row is centered on the same line as two adjacent second test strips 230 of the first row.
In this embodiment, by arranging the second test strips in the sparse region in a staggered manner, it is ensured that a sufficient space is left between the second test strips in different rows and different columns, so as to reflect the actual pattern size of the sparse region on the wafer.
In one embodiment, as shown in fig. 13, based on the same inventive concept, there is also provided a semiconductor device 1010 including a chip region and a test region, the test region being provided with a semiconductor test structure 1030.
Specifically, the chip region includes a plurality of die 1020 arranged in an array. The die is a chip with complete functions cut from the processed wafer. The free area between the plurality of dice 1020 is a test area that includes a plurality of semiconductor test structures 1030. Further, semiconductor test structures 1030 are provided at both the center and edges of semiconductor device 1010.
In the semiconductor manufacturing process, when the polysilicon gate line etching is performed on the wafer 1020 in the chip area, the semiconductor test structure 1030 in the test area is etched at the same time. Because the integrated circuit pattern on the surface of the die 1020 is very complex, the critical dimension after patterning is not easily measured directly, and the critical dimension of the actual pattern on the die 1020 is deduced by measuring the pattern dimension on the semiconductor test structure 1030.
In this embodiment, the chip area and the test area are disposed on the semiconductor device, and the pattern size of the die in the chip area can be obtained by measuring the pattern size of the semiconductor test structure in the test area.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the foregoing embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the foregoing embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (11)
1. A semiconductor test structure, the semiconductor test structure comprising:
a substrate;
a first test layer disposed on the substrate; the first test layer comprises a plurality of first test strips which are arranged at intervals, and the substrate is exposed between two adjacent first test strips;
a second test layer disposed on the first test layer and the exposed substrate; the second test layer comprises a plurality of second test strips arranged at intervals, and the orthographic projection of each second test strip on the substrate is overlapped with the orthographic projection part of at least one first test strip on the substrate.
2. The semiconductor test structure of claim 1, wherein the substrate comprises a first test region and a second test region, each of the first test strips in the first test region extending in a first direction, each of the first test strips in the second test region extending in a second direction, the first direction intersecting the second direction.
3. The semiconductor test structure of claim 2, wherein a distance between two adjacent first test strips in the first test zone and a distance between two adjacent first test strips in the second test zone are a first critical dimension.
4. The semiconductor test structure of claim 2, wherein each of the second test strips within the first test region extends along a third direction, the third direction intersecting the first direction; each of the second test strips within the second test zone extends in a fourth direction that intersects the second direction.
5. The semiconductor test structure of claim 4, wherein the second direction is perpendicular to the first direction, the third direction is perpendicular to the first direction, and the fourth direction is perpendicular to the second direction.
6. The semiconductor test structure of claim 4, wherein the first test zone comprises a first sub-test zone and a second sub-test zone, the second test zone comprises a third sub-test zone and a fourth sub-test zone, a length of the first test strip within the first sub-test zone is less than a length of the first test strip within the second sub-test zone, and a length of the first test strip within the third sub-test zone is less than a length of the first test strip within the fourth sub-test zone.
7. The semiconductor test structure of claim 6, wherein the second test strip in the first sub-test zone extends to the second sub-test zone and the second test strip in the third sub-test zone extends to the fourth sub-test zone.
8. The semiconductor test structure of claim 6, wherein the second sub-test region and the fourth sub-test region each comprise a sparse region and a dense region, a distance between two adjacent second test strips in the sparse region being greater than a distance between two adjacent second test strips in the dense region.
9. The semiconductor test structure of claim 8, wherein a length of the second test strip in the sparse zone is less than a length of the second test strip in the dense zone.
10. The semiconductor test structure of claim 9, wherein the second test strips in the sparse zone are arranged in an array, and two adjacent rows of the second test strips are arranged in a staggered manner, and two adjacent columns of the second test strips are arranged in a staggered manner.
11. A semiconductor device comprising a chip area and a test area, wherein the test area is provided with a semiconductor test structure according to any of claims 1-10.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070177066A1 (en) * | 2006-01-27 | 2007-08-02 | Au Optronics Corp. | Display panel |
| CN210743940U (en) * | 2020-01-06 | 2020-06-12 | 长江存储科技有限责任公司 | Electromigration test structure |
| KR20200097566A (en) * | 2019-02-08 | 2020-08-19 | 충남대학교산학협력단 | Semiconductor device having test pattern |
| CN112103202A (en) * | 2020-11-10 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN112420671A (en) * | 2020-11-10 | 2021-02-26 | 普迪飞半导体技术(上海)有限公司 | Orthogonal grid test structure, test device, method and system |
| CN115706073A (en) * | 2021-08-16 | 2023-02-17 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
-
2023
- 2023-06-16 CN CN202310714630.4A patent/CN116454070B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070177066A1 (en) * | 2006-01-27 | 2007-08-02 | Au Optronics Corp. | Display panel |
| KR20200097566A (en) * | 2019-02-08 | 2020-08-19 | 충남대학교산학협력단 | Semiconductor device having test pattern |
| CN210743940U (en) * | 2020-01-06 | 2020-06-12 | 长江存储科技有限责任公司 | Electromigration test structure |
| CN112103202A (en) * | 2020-11-10 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN112420671A (en) * | 2020-11-10 | 2021-02-26 | 普迪飞半导体技术(上海)有限公司 | Orthogonal grid test structure, test device, method and system |
| CN115706073A (en) * | 2021-08-16 | 2023-02-17 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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