CN116884955A - Semiconductor structure and testing method - Google Patents

Abstract

The present disclosure provides a semiconductor structure and a test method. The semiconductor structure comprises a substrate, wherein a first chip area and a cutting channel area are arranged on the substrate, and the cutting channel area is positioned outside the first chip area; the rewiring layer is arranged on the substrate and comprises a test wire; the test assembly comprises a plurality of test contact pads, the test assembly is arranged on the first chip area, and the test wire is in contact with the plurality of test contact pads.

Description

Semiconductor structure and testing method

Technical Field

The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a testing method.

Background

The rewiring layer (Re-Distribution Layer, abbreviated as RDL) can change the location of electrical contacts of an integrated circuit, so that the integrated circuit can be adapted to a richer packaging format and is therefore widely used in integrated circuits.

Current integrated circuits are typically prepared based on semiconductor wafers. In an actual manufacturing process, the wafer is typically divided into chip regions and scribe line regions located between the chip regions. The integrated circuit is prepared on the chip area, and when the wafer is divided, adjacent chip areas need to be divided along the dicing channel area. In addition, the scribe line region is also used to set a mark or test structure. During testing, the test probes may be in electrical contact with the test structures in the scribe line region, and the rewiring layer also needs to be connected to the test structures in the scribe line region in order to perform the test. However, to accommodate sufficient test structures and re-routing layers, the dicing street areas are often designed to be relatively wide, resulting in a relatively limited area of the wafer that can be used to fabricate integrated circuits.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a semiconductor structure that can reduce test elements and re-routing layers in scribe line regions in order to further reduce the size of the scribe line regions and thereby increase the area of the wafer that can be used for the fabrication of integrated circuits.

According to some embodiments of the present disclosure, there is provided a semiconductor structure, comprising:

the substrate is provided with a first chip area and a cutting channel area, and the cutting channel area is positioned outside the first chip area;

a rewiring layer disposed on the substrate, the rewiring layer comprising a test wire;

the test assembly comprises a plurality of test contact pads, the test assembly is arranged on the first chip area, and the test wires are in contact arrangement with the plurality of test contact pads.

In some embodiments of the present disclosure, a second chip region is further disposed on the substrate, the first chip region and the second chip region are disposed at intervals, the scribe line region is disposed between the first chip region and the second chip region, and at least a portion of the test wire is further disposed on the second chip region.

In some embodiments of the disclosure, the test wire includes a main body portion and two connection portions, the main body portion is disposed on the second chip region, the connection portions are disposed on the dicing street region in a straddling manner, two ends of the connection portions are respectively disposed on the first chip region and the second chip region, and two ends of the connection portions are respectively disposed in contact with the test contact pad and the main body portion.

In some embodiments of the disclosure, the second chip region has a second edge adjacent to the second chip region, the body portion is elongated and the extending direction of the body portion is the same as the extending direction of the second edge.

In some embodiments of the present disclosure, the length of the body portion is greater than 30 μm.

In some embodiments of the disclosure, the second chip regions are two, the two second chip regions are respectively disposed on two opposite sides of the first chip region, the test wires and the test assemblies are correspondingly two, the two test wires are respectively electrically connected to the two test assemblies, and at least part of the two test wires are respectively disposed on the two second chip regions.

In some embodiments of the present disclosure, the test wire is integrally disposed on the first chip region, and the test wire is disposed on one side of the test assembly.

In some embodiments of the present disclosure, the first chip region has a first edge adjacent to the scribe line region, a plurality of the test contact pads are disposed side by side, and a side by side direction of the plurality of the test contact pads is parallel to an extending direction of the first edge.

In some embodiments of the present disclosure, the semiconductor structure further includes a seal ring disposed under the test contact pad.

In some embodiments of the present disclosure, the test component is disposed in the rewiring layer.

Further, the present disclosure also provides a test method, which includes the steps of:

providing a semiconductor structure as described in any of the embodiments above;

a test signal is provided to the test contact pad and is conducted through the test wire to the test element.

The semiconductor structure provided by the present disclosure includes a substrate, a test component, and a rewiring layer. The test assembly comprises a plurality of test contact pads, and the test assembly is arranged on the first chip area. The rewiring layer comprises a test wire which is electrically connected with the test contact pad. The semiconductor structure changes the setting position of the test assembly, and the semiconductor structure is arranged on the first chip area outside the dicing channel area, so that the test assembly can be removed from the dicing channel area when the test wire and the test assembly work normally, the size of the dicing channel area is further reduced, and the area on the wafer, which can be used for preparing integrated circuits, is increased.

The foregoing description is only an overview of the present invention, and is intended to provide a better understanding of the present invention, as it is embodied in the following description, with reference to the preferred embodiments of the present invention and the accompanying drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and that other embodiments of the drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic top view of a semiconductor structure;

FIG. 2 is a schematic cross-sectional view of the structure shown at AA' in FIG. 1;

FIG. 3 is a schematic top view of another semiconductor structure;

FIG. 4 is a schematic top view of another semiconductor structure;

wherein, each reference sign and meaning are as follows:

11. a substrate; 12. a conductive pattern layer; 13. a support layer; 14. a rewiring layer; 15. a seal ring; 16. a dielectric layer; 101. a first chip region; 1010. a first edge; 102. cutting the road area; 103. a second chip region; 1030. a second edge; 111. testing the contact pad; 120. testing the wire; 121. a connection part; 122. a main body portion; 201. a first chip region; 202. cutting the road area; 211. testing the contact pad; 220. testing the wire; 301. a first chip region; 302. cutting the road area; 303. a second chip region; 311. testing the contact pad; 320. testing the wire; 321. a connection part; 322. a main body.

Detailed Description

In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The disclosed embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature, and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

Chips are typically prepared on a wafer basis. In the production of chips, wafer acceptance testing (Wafer Acceptance Testing, WAT for short) is also often required for wafers on which integrated circuits are fabricated. Wafer acceptance testing refers to electrical measurement of chips on a wafer to verify whether the process at each stage on the chip can meet the requirements. Wafer acceptance testing includes various tests, such as chemical, physical, or performance tests, that confirm whether the chip meets the requirements of a design specification or contract. In order to facilitate wafer acceptance testing, it is also generally necessary to provide a test assembly including a test contact pad for contacting an external electrode, a test element for performing an electrical measurement, and a test wire connecting the test contact pad and the test element. In the conventional art, since a chip area is generally used only for disposing functional parts and corresponding circuits, structures and marks for testing and the like are disposed on a scribe line area.

Fig. 1 of the present disclosure is a schematic top view of a semiconductor structure, and fig. 2 is a schematic cross-sectional view along AA' of the semiconductor structure in fig. 1. Referring to fig. 1 and 2, the semiconductor structure includes a substrate 11, a test component, and a rewiring layer 14. The substrate 11 is provided with a first chip area 101 and a dicing street area 102, and the dicing street area 102 is located outside the first chip area 101. The test assembly includes a plurality of test contact pads 111, and the plurality of test contact pads 111 in the test assembly are disposed on the first chip area 101. The redistribution layer 14 is disposed on the substrate 11, and the redistribution layer 14 includes a test wire 120, where the test wire 120 is electrically connected to the plurality of test contact pads 111.

The substrate 11 may include a semiconductor wafer, which may include silicon, germanium, a silicon-germanium alloy, gallium arsenide, or silicon carbide. Further, in the present disclosure, a specific circuit structure may be included in the substrate 11, which may be a circuit structure capable of storing information or a circuit structure capable of performing a logic operation, which may include at least one electronic device such as one or more of a transistor and a capacitor. The rewiring layer 14 may be electrically connected to the circuit structure, with certain nodes of the circuit structure being routed to specific sites.

The present disclosure provides a semiconductor structure including a substrate 11, a test component, and a rewiring layer 14. The test assembly includes a plurality of test contact pads 111, and the test assembly is disposed on the first chip area 101. The rewiring layer 14 includes a test wire 120, and the test wire 120 is electrically connected to the test contact pad 111. The semiconductor structure of the present disclosure changes the placement position of the test component, and places the test component on the first chip area 101 located outside the scribe line area 102, so that the test component can be removed from the scribe line area 102 while ensuring the normal operation of the test wire 120 and the test component, so as to further reduce the size of the scribe line area 102, thereby increasing the area on the wafer that can be used for preparing integrated circuits.

Referring to fig. 2, in some examples of this embodiment, the semiconductor structure may further include a conductive pattern layer 12 and a support layer 13. Wherein the conductive pattern layer 12 may be disposed on the substrate 11. The conductive pattern layer 12 may include a plurality of electrical connection lines arranged at intervals. The support layer 13 may cover a portion of the conductive pattern layer 12 and fill in the gaps between adjacent electrical connection lines. The support layer 13 may have a flat surface, and a via hole exposing a portion of the conductive pattern layer 12 may be provided in the support layer 13, and a re-wiring layer 14 may be provided on the support layer 13 and in the via hole so as to achieve electrical connection between the outside and the conductive pattern layer 12. The support layer 13 can provide a flatter surface, and can also serve as an insulating space between the conductive pattern layer 12 and the redistribution layer 14 to facilitate placement of the redistribution layer 14.

In some examples of this embodiment, the material of the conductive pattern layer 12 may include a metallic material, for example, the material of the conductive pattern layer 12 may include one or more of aluminum, copper, nickel, silver, gold, and cobalt. The material of the support layer 13 may include an insulating material, for example, the material of the support layer 13 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride.

Referring to fig. 1 and 2, in some examples of this embodiment, test components may also be disposed in the rewiring layer 14. The placement of test components in the rewiring layer 14 means: the test contact pads 111 in the test assembly and the test wires 120 in the rewiring layer 14 may be located on the same layer, which allows the test contact pads 111 and the test wires 120 to have the same or similar spacing from the substrate 11, and the test contact pads 111 and the rewiring layer 14 including the test wires 120 can be prepared in the same process.

It is understood that the rewiring layer 14 may be disposed on the first chip region 101 and the dicing street region 102. In some examples of this embodiment, the redistribution layer 14 may include functional conductive patterns. The functional conductive pattern may be electrically connected to the conductive pattern layer 12 on the first chip region 101.

Referring to fig. 1 and 2, in some examples of this embodiment, the semiconductor structure may further include a seal ring 15. A seal ring 15 may be disposed in the first chip region 101 and adjacent to or in close proximity to the scribe line region 102 to protect circuit structures located within the first chip region 101. Further, a sealing ring 15 may be disposed under the test contact pad 111 to avoid the test contact pad 111 and the test wire 120.

In some examples of this embodiment, the seal ring 15 may be spaced from the dicing street 102. Further, the spacing between the seal ring 15 and the scribe line region 102 may be 2 μm to 10 μm. For example, the spacing between the seal ring 15 and the scribe line region 102 may be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 8 μm, or 10 μm, or the spacing between the seal ring 15 and the scribe line region 102 may be in a range between any two of the above.

Referring to fig. 1 and 2, in some examples of this embodiment, the semiconductor structure may further include a patterned dielectric layer 16, and an opening may be provided in the dielectric layer 16. The opening of the dielectric layer 16 may be used to define the location of the rewiring layer 14, for example, the test wires 120 in the rewiring layer 14 and the test components may be disposed within the opening of the dielectric layer 16.

In some examples of this embodiment, the material of dielectric layer 16 may be an insulating material. Further, the material of the dielectric layer 16 may be an inorganic insulating material or an organic insulating material. The inorganic insulating material may be silicon oxide, silicon nitride or silicon oxynitride, and the organic insulating material may be polyimide. In this embodiment, the material of the dielectric layer 16 may be an organic insulating material, and the dielectric layer 16 also has the function of providing a planarized surface.

In some examples of this embodiment, one test assembly may include two test contact pads 111, with test wire 120 connected to both test contact pads 111, at which time both test contact pads 111 may be used to test the resistive properties of test wire 120 to characterize whether test wire 120 is acceptable. It will be appreciated that the test wire 120 is located on the rewiring layer 14, and thus the resistive properties of the test wire 120 obtained by the reference test may be used to represent the resistive properties of the rewiring layer 14 as a whole.

In some examples of this embodiment, the test assembly may include more than three test contact pads 111, where two test contact pads 111 are connected to the test wire 120, and at least one test contact pad is further disposed between the two test contact pads 111 connected to the test wire 120. This can increase the pitch between the two test contact pads 111 connected to the test wire 120.

It will be appreciated that, in the actual testing process, the resistance value measured from the test wire 120 may have an error, and if the resistance of the test wire 120 itself is small, the error has a large influence on the result, which is not beneficial to determine whether the process is normal. Therefore, in designing the test wire 120, it is necessary to make the test wire 120 have a sufficient length in order to obtain more remarkable resistance.

To reduce test errors for more reference resistive performance, the test wire 120 may have a longer length so that the test wire 120 itself has a more pronounced resistance. In some examples of this embodiment, the length of the test wire 120 may be ≡90 μm. Further, the length of the test wire 120 may be 90 μm to 500 μm. For example, the length of the test wire 120 may be 90 μm, 150 μm, 200 μm, 300 μm, 400 μm, or 500 μm, or the length of the test wire 120 may be in a range between any two of the above. Controlling the length of the test wire 120 within the above-described range can make the test wire 120 have a resistance more suitable for measurement.

Longer test wires 120 also means that more space is required for placement of the test wires 120. Referring to fig. 1 and 2, in some examples of this embodiment, at least a portion of the test wire 120 may be disposed on the scribe line region 102. It can be appreciated that by disposing a portion of the test wire 120 on the scribe line region 102, the test wire 120 can be disposed using the space of the scribe line region 102 to save the area of the first chip region 101.

Further, referring to fig. 1 and 2, in some examples of this embodiment, a second chip region 103 is further disposed on the substrate 11, the first chip region 101 and the second chip region 103 are disposed at intervals, the scribe line region 102 is disposed between the first chip region 101 and the second chip region 103, and at least part of the test wire 120 is further disposed on the second chip region 103. The test wire 120 is extended to the second chip area 103, so that the area of the first chip area 101 and the dicing street area 102 can be further saved. Since the scribe line region 102 also requires a denser design of marks or other test structures, the space on the second chip region 103 may be primarily utilized to obtain longer test leads 120 without substantially affecting the scribe line region 102.

It will be appreciated that since the test contact pads 111 and the test elements are disposed on the first chip region 101 with the dicing street region 102 spaced apart between the first chip region 101 and the second chip region 103, the test wires 120 must also be disposed on the dicing street region 102 to achieve connection with the test contact pads 111 and the test elements when the test wires 120 are disposed on the second chip region 103.

Referring to fig. 1, in some examples of this embodiment, the test wire 120 includes a main body 122 and two connection parts 121, the main body 122 is disposed on the second chip region 103, the connection parts 121 are disposed across the scribe line region 102, two ends of the connection parts 121 are disposed on the first chip region 101 and the second chip region 103, and two ends of the connection parts 121 are disposed in contact with the test contact pads 111 and the main body 122, respectively. Further, both ends of the connection part 121 may be disposed between the two test contact pads 111 and the body part 122, respectively, and both ends of the body part 122 may be disposed between the two connection parts 121.

The connecting portion 121 straddles the scribe line region 102 refers to an area where two ends of the connecting portion 121 may be flush with two side edges of the scribe line region 102 or located outside the corresponding edges, respectively. Both ends of the connection part 121 may be respectively contacted to the test component located in the first chip region 101 and the body part 122 located in the second chip region 103. In this example, by providing the connection portion 121 straddling the scribe line region 102, the influence of the test wire 120 on the scribe line region 102 can be reduced as much as possible. In addition, by providing the test component in the first chip region 101 and providing the main body portion 122 of the test wire 120 in the second chip region 103, the space of the first chip region 101 and the second chip region 103 near the dicing street region 102 can be fully utilized, thereby minimizing the occupation of the test component and the test wire 120 to the chip region.

Referring to fig. 1, in some examples of this embodiment, the second chip region 103 has a second edge 1030 adjacent to the second chip region 103, the body portion 122 may be elongated, and the extension direction of the body portion 122 is the same as the extension direction of the second edge 1030, and the interval between the body portion 122 and the second edge 1030 is 50 μm or less. Wherein, the distance between the main body 122 and the second edge 1030 is the distance between the side of the main body 122 near the second edge 1030 and the second edge 1030. For example, the spacing between the body portion 122 and the second edge 1030 may be 0 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, or the spacing between the body portion 122 and the second edge 1030 may be within a range between any two of the above. Wherein when the spacing between the body portion 122 and the second edge 1030 is 0 μm, it means that a side of the body portion 122 near the second edge 1030 is located on the second edge 1030. It will be appreciated that the provision of specific functional conductive patterns in the rewiring layer 14 located on the second chip area 103 is also required, and by providing a spacing between the body portion 122 and the second edge 1030 of less than 50 μm, it is possible to introduce a portion of the test wire 120 onto the second chip area 103 while minimizing the impact on the design of the functional conductive patterns in the rewiring layer 14.

Referring to fig. 1, in some examples of this embodiment, the connection portion 121 may be perpendicular to the extending direction of the scribe line region 102 to minimize the space occupied by the connection portion 121 on the scribe line region 102. Further, the connection portion 121 is perpendicular to the extending direction of the main body portion 122.

Further, in some examples of this embodiment, the line width of the test wire 120 may be 5 μm to 7 μm. For example, the line width of the test wire 120 may be 5 μm, 5.5 μm, 6 μm, 6.5 μm, or 7 μm, or the line width of the test wire 120 may be in a range between any two of the above lengths.

It will be appreciated that in this embodiment, the test wire 120 may be composed of two connection parts 121 and a body part 122 located between the two connection parts 121, and thus, the length of the test wire 120 may be the sum of the lengths of the two connection parts 121 and the length of the body part 122.

Referring to fig. 1 and 2, in some examples of this embodiment, the length of the body portion 122 of the test wire 120 may be greater than 30 μm, it being understood that the length of the body portion 122 should be less than the length of the second chip region 103. Further, the length of the main body portion 122 of the test wire 120 may be 50 μm to 400 μm. For example, the length of the main body 122 may be 50 μm, 100 μm, 150 μm, 200 μm, 300 μm, or 400 μm, or the length of the main body 122 may be in a range between any two of the above.

Referring to fig. 1 and 2, in some examples of this embodiment, first chip region 101 has a first edge 1010 adjacent to the dicing lane. The plurality of test contact pads 111 are disposed side by side, and a side by side direction of the plurality of test contact pads 111 is parallel to an extending direction of the first edge 1010. By controlling the side-by-side direction of the plurality of test contact pads 111 and the extending direction of the first edge 1010 to be parallel, it helps to simplify the wiring difficulty of the test wire 120 and to minimize the influence of introducing the test wire 120 and the test component to the first chip area 101.

Further, in some examples of this embodiment, the minimum spacing between the test contact pad 111 and the first edge 1010 is below 50 μm. For example, the pitch between the test contact pad 111 and the first edge 1010 is 0 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, or the pitch between the test contact pad 111 and the first edge 1010 may be within a range between any two of the above. Wherein when the spacing between the test contact pad 111 and the first edge 1010 is 0 μm, it means that the test contact pad 111 is disposed next to the first edge 1010 of the first chip area 101. It will be appreciated that the provision of specific functional conductive patterns in the redistribution layer 14 on the first chip region 101 is also required, and by providing a spacing between the test contact pad 111 and the first edge 1010 below 50 μm, the design of the functional conductive patterns in the redistribution layer 14 can be as little affected as possible while introducing the test contact pad 111 onto the second chip region 103.

Referring to fig. 1 and 2, in some examples of this embodiment, there may be a plurality of test assemblies, and the plurality of test assemblies may be disposed on the first chip region 101 side by side, and the side by side direction of the plurality of test assemblies is parallel to an edge of the first chip region 101 adjacent to the dicing streets. Further, the test contact pads 111 of the plurality of test assemblies may each be disposed proximate the first edge 1010.

In some examples of this embodiment, the material of the test contact pad 111 may include a metallic material. For example, the material of the test contact pad 111 may include one or more of aluminum, copper, nickel, silver, gold, and cobalt. The material of the test wire 120 may also include a metallic material. For example, the material of the test wire 120 may include one or more of aluminum, copper, nickel, silver, gold, and cobalt.

Fig. 3 is a schematic top view of another semiconductor structure. Referring to fig. 3, the semiconductor structure in this embodiment still includes a substrate, a redistribution layer, and a test component, where a first chip region 201 and a scribe line region 202 are disposed on the substrate, and the scribe line region 202 is located outside the first chip region 201. The redistribution layer is disposed on the substrate, and the redistribution layer includes a test wire 220. The test assembly includes a plurality of test contact pads 211, the test assembly is disposed on the first chip area 201, and the test wires 220 are disposed in contact with the plurality of test contact pads 211.

In this embodiment, the test wires 220 are integrally disposed on the first chip region 201. It will be appreciated that this can eliminate the need for the test wire 220 to occupy space on the scribe line region 202, but this also requires more space on the first chip region 201. Further, the test wire 220 may be disposed at one side of the test assembly. For example, the test wire 220 may be disposed on a side of the test wire remote from the scribe line region 202.

Fig. 4 is a schematic top view of another semiconductor structure. Referring to fig. 4, the semiconductor structure in this embodiment still includes a substrate, a redistribution layer, and a test component, where a first chip region 301 and a scribe line region 302 are disposed on the substrate, and the scribe line region 302 is located outside the first chip region 301. The redistribution layer is disposed on the substrate, and the redistribution layer includes a test wire 320. The test assembly includes a plurality of test contact pads 311, the test assembly is disposed on the first chip area 301, and the test wires 320 are disposed in contact with the plurality of test contact pads 311.

In this embodiment, there are two second chip regions 303, and the two second chip regions 303 are disposed on two sides of the first chip region 301, respectively. Correspondingly, there are two test assemblies and test wires 320, and two test assemblies and two test wires 320 are disposed corresponding to two second chip areas 303, respectively. Referring to fig. 4, one of the test wires 320 is at least partially located on one of the second chip regions 303, and the other test wire 320 is at least partially located on the other of the second chip regions 303. Further, the first chip region 301 has two edges adjacent to the two second chip regions 303, respectively, and two test components may be disposed near the two edges, respectively.

Referring to fig. 4, in this embodiment, the test wire 320 may include a connection portion 321 and a body portion 322. The specific arrangement of the connecting portion 321 and the main body portion 322 may refer to the arrangement in fig. 1.

Further, the present disclosure also provides a method for preparing the semiconductor structure, which may include the following steps.

Step S1, providing a substrate, wherein a first chip region cutting channel region is arranged on the substrate, and the cutting channel region is positioned outside the first chip region.

Step S2, preparing a rewiring layer and a testing component on the substrate. The rewiring layer comprises a test wire, the test assembly comprises a plurality of test contact pads, the test assembly is arranged on the first chip area, and the test wire is in contact with the plurality of test contact pads.

In the embodiments of the present disclosure, the technical effects achieved by the method for manufacturing a semiconductor structure are similar to those of the foregoing embodiments of the semiconductor structure, and will not be described in detail herein.

The semiconductor structure provided in the above embodiments of the present disclosure may be used as a whole or after being divided along the scribe line region. For example, the present disclosure also provides a memory device comprising a semiconductor structure as in any of the embodiments described above. Alternatively, the memory device may include a substructure that is divided along scribe lines in the semiconductor structure described above. In the semiconductor structure shown in fig. 1 or 4, if divided along the scribe line region, a substructure containing the first chip region or a substructure containing the second chip region may be obtained, and the substructure containing the first chip region or the substructure containing the second chip region may participate in the fabrication of the memory device.

Further, the present disclosure also provides a test method, including the steps of: providing the semiconductor structure of the embodiment, providing a test signal to one of the test contact pads, and conducting the test signal to the other test contact pad through the test wire to obtain the resistance value of the test wire; judging whether the manufacturing process of the rewiring layer is normal or not through the resistance value. It can be understood that in this step, a technician can preset a reference resistance range according to the resistance of the test wire when the process is normal, and when the resistance obtained by the test is within the reference resistance range, it is indicated that the process of the re-wiring layer is normal. And when the resistance value obtained by the test is out of the range of the resistance value, the abnormal processing technology of the rewiring layer is indicated.

Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

It should be understood that the steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the preparation process may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the sub-steps or stages are performed is not necessarily sequential, and may be performed in turn or alternately with at least a portion of the sub-steps or stages of other steps or steps.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

Claims (10)

1. A semiconductor structure, comprising:

the substrate is provided with a first chip area and a cutting channel area, and the cutting channel area is positioned outside the first chip area;

a rewiring layer disposed on the substrate, the rewiring layer comprising a test wire;

the test assembly comprises a plurality of test contact pads, the test assembly is arranged on the first chip area, and the test wires are in contact arrangement with the plurality of test contact pads.

2. The semiconductor structure of claim 1, wherein a second die region is further disposed on the substrate, the first die region and the second die region are spaced apart, the scribe line region is disposed between the first die region and the second die region, and at least a portion of the test wire is further disposed on the second die region.

3. The semiconductor structure of claim 2, wherein the test wire comprises a main body portion and two connection portions, the main body portion is disposed on the second chip region, the connection portions are disposed across the scribe line region, two ends of the connection portions are disposed on the first chip region and the second chip region, and two ends of the connection portions are disposed in contact with the test contact pad and the main body portion, respectively.

4. The semiconductor structure of claim 3, wherein the second chip region has a second edge adjacent to the second chip region, the body portion is elongated and has an extension direction that is the same as an extension direction of the second edge.

5. The semiconductor structure of claim 3, wherein the length of the body portion is greater than 30 μm.

6. The semiconductor structure of claim 2, wherein there are two second chip regions, two second chip regions are respectively disposed on two opposite sides of the first chip region, there are two corresponding test wires and two corresponding test assemblies, two test wires are respectively electrically connected to two corresponding test assemblies, and at least portions of two test wires are respectively disposed on two second chip regions.

7. The semiconductor structure of claim 1, wherein the test wire is integrally disposed on the first die region, the test wire being disposed on one side of the test assembly.

8. The semiconductor structure of any one of claims 1-7, wherein the first chip region has a first edge adjacent to the scribe line region, a plurality of the test contact pads are arranged side by side, and a side by side direction of the plurality of the test contact pads is parallel to an extending direction of the first edge.

9. The semiconductor structure of any one of claims 1-8, wherein the test component is disposed in the redistribution layer; and/or the number of the groups of groups,

the semiconductor structure further includes a seal ring disposed under the test contact pad.

10. A method of testing comprising the steps of:

providing a semiconductor structure as claimed in any one of claims 1 to 9;

providing a test signal to one of the test contact pads, and conducting the test signal to the other test contact pad through the test wire to obtain the resistance value of the test wire;

judging whether the manufacturing process of the rewiring layer is normal or not through the resistance value.