JP2001223319A - Semiconductor mounting structure and semiconductor chip set used therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a manufacturing cost in mounting a plurality of semiconductor chips on a board and to accelerate a transmitting speed of a signal. SOLUTION: The semiconductor chips 301, 302 are used without isolating from each other. Original pads of both the chips are electrically connected by rewiring to form a solder bump on a new pad on the rewiring. The chips 301, 302 are mounted on the board as one chip to constitute a semiconductor package. Since the electric connection between the chips is conducted by the rewiring, a connecting distance becomes short, and an electric signal can be rapidly transmitted. Since it is not necessary to provide the solder bump for connecting the chips to each other, its manufacturing cost can be reduced, and connecting positions of the board are reduced to improve reliability of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting structure for mounting a semiconductor chip on a substrate and a semiconductor chip set used for the same.

[0002]

2. Description of the Related Art As a mounting structure for mounting a semiconductor chip on a substrate, for example, there is a chip scale package disclosed in Japanese Patent Application Laid-Open No. 10-284538. FIG.
4, FIG. 15 is a diagram showing a configuration of a semiconductor chip in the chip scale package. FIG. 14 is a plan view showing a solder bump connecting a semiconductor chip to a substrate,
FIG. 15 is an enlarged cross-sectional view taken along the line AA in FIG.

Reference numeral 101 denotes a semiconductor chip, and reference numeral 103 denotes an original pad formed on the outer periphery of the semiconductor chip 101. The insulating layer 109 is formed on the surface of the semiconductor chip 101 except for the portion of the original pad 103.
A rewiring 104 connected to the original pad 103 is formed on the original pad 103, and a new pad 105 is formed on the rewiring 104. Except for the new pad 105, the surface of the semiconductor chip 101 is covered with a protective film 114, and a solder bump 113 is formed on the new pad 105.

When a semiconductor chip is mounted on a circuit board without using the above-described rewiring, original pads are connected to the circuit board by wire bonding. In this mounting by wire bonding, since an impact is applied to the original pad, the original pad 103 is provided at the outer peripheral position of the semiconductor chip, and the semiconductor element is not arranged therebelow.

In such a semiconductor chip, the positions of the solder bumps can be rearranged by forming rewiring and providing new pads on the surface of the semiconductor chip as described above. By rearranging the solder bumps, the external connection terminals on the board and the solder bumps can be directly connected.

Some chip scale packages use a plurality of semiconductor chips depending on the circuit configuration. When such a chip scale package is configured by the above-described semiconductor chip, the following structure can be considered. FIGS. 16 and 17 are views showing the structure of a chip scale package in which two semiconductor chips configured as described above are mounted on a substrate. FIG. 16 is a plan view as viewed from the semiconductor chip, and FIG. 17 is an enlarged partial cross-sectional view taken along the line BB in FIG. In FIG. 16, the semiconductor chips are indicated by virtual lines.

The semiconductor chips 203 and 204 are mounted on the substrate 201 on which the solder bumps 205 and 206 are rearranged in a grid pattern and the connection terminals 202 are formed at the same pitch as these to form a chip scale package.
By arranging the solder bumps on the surface of the semiconductor chip, connection can be made without providing a wiring pattern on the substrate 201. Here, the semiconductor chips 203 and 204
Are connected to the substrate 201 in independent configurations, so that the connection between the semiconductor chips 203 and 204 is made via the substrate 201. Therefore, the substrate 201 is coated with a coating layer 209 for the purpose of protecting the substrate surface,
A wiring 207 for connecting between the semiconductor chips is formed.

[0008]

However, since the connection between the plurality of semiconductor chips is made via the substrate as described above, it is necessary to provide the semiconductor chips with solder bumps for the connection. The number of bumps increases,
There is a problem that the increase in the number of connection points with the substrate limits the improvement in reliability such as occurrence of connection failure. In view of the above problems, an object of the present invention is to provide a highly reliable semiconductor mounting structure and a semiconductor chip set used for the same, which reduce the number of connection points with a substrate.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor package for mounting a plurality of semiconductor chips electrically connected to each other on a substrate.
The plurality of semiconductor chips are formed on the same wafer, and a re-wiring between the plurality of semiconductor chips is formed on a surface of the plurality of semiconductor chips to perform electrical connection between the semiconductor chips. The plurality of semiconductor chips are separated from the wafer without being divided from each other, and are attached to the substrate as a chip set.

According to a second aspect of the present invention, a new pad is set at a different position from an original pad to which the semiconductor chip is connected to a circuit, and the connection between the new pad and the original pad is made by the semiconductor chip. The re-wiring is performed on the surface, and the new pad positions correspond to the external connection terminals on the substrate.

According to a third aspect of the present invention, there is provided a semiconductor chip set comprising a plurality of semiconductor chips electrically connected to each other and mounted on a substrate, wherein the plurality of semiconductor chips are formed on the same wafer. An arbitrary group of adjacent semiconductor chips is separated from the wafer without being divided from each other from the large number of semiconductor chips, and all the semiconductor chips in the vertical and horizontal adjacent directions are included in the large number of semiconductor chips on the wafer. A plurality of vertical wirings and horizontal wirings extending over the wirings are formed in a grid pattern, and predetermined intersections between the vertical wirings and the horizontal wirings are electrically connected.

According to a fourth aspect of the present invention, in the semiconductor chip set, a pad for connection to a substrate is provided at the predetermined intersection. In particular, according to the invention of claim 5, a transistor is formed on each of the plurality of semiconductor chips, the horizontal wiring is composed of an X-directional source wiring, an X-directional drain wiring and an X-directional gate wiring, the vertical wiring is a Y-directional source wiring, and a Y-directional wiring. A source region of the transistor is connected to an intersection of the X-direction source wiring and the Y-direction source wiring as a predetermined intersection, and a source pad is provided.
The drain region of the transistor is connected to the intersection of the direction drain wiring and the Y direction drain wiring, and a drain pad is provided. The gate region of the transistor is connected to the intersection of the X direction gate wiring and the Y direction gate wiring. In addition, a gate pad is provided.

According to a sixth aspect of the present invention, the gate region of the transistor is connected to the intersection of the X-direction gate wiring and the Y-direction gate wiring via the gate rearrangement wiring, and the X-direction source wiring, the X-direction drain wiring and the X-direction drain wiring are connected. The gate wirings are provided at equal intervals from each other, and the Y-direction source wiring, the Y-direction drain wiring, and the Y-direction gate wiring are also provided at equal intervals.

According to a seventh aspect of the present invention, a bump is formed at a predetermined intersection electrically connected between the vertical wiring and the horizontal wiring, and a bump is formed at all intersections which are not electrically connected. It was assumed.

[0015]

According to the first aspect of the present invention, a plurality of semiconductor chips are mounted on a substrate as a chip set formed on the surface of the semiconductor chip without re-dividing the semiconductor chips and rewiring for electrical connection between the semiconductor chips. As compared with the connection via the substrate, the connection distance is shorter and the stray capacitance is smaller, so that the effect of improving the signal transmission speed can be obtained. Further, bumps for connection between the semiconductor chips are not required, the number of portions connected to the substrate is reduced, the possibility of causing a problem such as poor connection is reduced, and the reliability of connection is improved.

According to a second aspect of the present invention, in addition to the effects of the first aspect, a new pad position is set in correspondence with an external connection terminal on the substrate, and the connection between the new pad and the original pad is performed by a semiconductor chip. Since rewiring is performed on the surface, bumps are formed on the original pads and connected to the substrate, and signals can be transmitted at high speed with a small size compared to a configuration in which a wiring pattern on the substrate is connected to an external connection terminal.

According to a third aspect of the present invention, a plurality of vertical wirings and horizontal wirings extending over all the semiconductor chips in the vertical and horizontal adjacent directions are formed in a lattice pattern on the wafer, and the vertical wirings and the horizontal wirings are formed. A predetermined set of intersections is electrically separated from a number of semiconductor chips, and an arbitrary group of adjacent semiconductor chips is separated without being divided into a chip set. Even if you set
All of the transistors and the like formed on each semiconductor chip can be connected in parallel by the above vertical wiring and horizontal wiring. Thus, the rewiring formed by the same photomask can cope with any specification of the number of semiconductor chips, and the manufacturing cost is reduced. Further, since the rewiring pattern has a simple lattice shape, a high-density layout can be performed without worrying about interference with an adjacent wiring.

According to the fourth aspect of the present invention, since the connection pad with the substrate is provided at the predetermined intersection, it functions as a positioning mark at the time of bump formation. In particular, the source wirings in the X direction and the Y direction, respectively,
By connecting the corresponding region of the transistor to the intersection of the drain wiring and the gate wiring and providing the pad, the electrical connection distance from each region of the transistor to the pad is also reduced.

In the invention according to claim 6, since the vertical wiring and the horizontal wiring of the rewiring are provided at equal intervals from each other, there is no possibility that the high density is hindered by a part of the adjacent wirings, and the pad spacing is reduced. Standardization is also easy. According to the seventh aspect of the present invention, bumps are formed not only on the pads connected to regions such as transistors, but also on the intersections of the vertical wiring and the horizontal wiring that are not electrically connected. It functions as distributed heat radiating means and stabilizes the operating characteristics of the semiconductor chip.

[0020]

Embodiments of the present invention will be described below. 1 and 2 are diagrams showing a configuration of a semiconductor chip according to the first embodiment. FIG. 1 is a plan view of a semiconductor chip viewed from a solder bump side, and FIG.
It is sectional drawing of CC section in FIG. Semiconductor chip 30
Reference numerals 1 and 302 are formed on the same wafer by the same semiconductor manufacturing process. Semiconductor chips 301 and 302
May be the same or different. In a general semiconductor manufacturing process, dicing is performed along the scribe line area 303, but in this embodiment, dicing is not performed, and the semiconductor chips 301 and 302 are used as an integrated chip set.

Original pads 311 and 317 are formed on the surfaces of the semiconductor chips 301 and 302, respectively. On the surfaces of the semiconductor chips 301 and 302 including the scribe line region 303, an insulating layer 315 is set thicker than the original pads 311 and 317, and the original pads 311 and 317 are formed by rewirings 307 and 308 formed on the insulating layer 315. , Are connected through windows provided corresponding to the respective pads.

The rewiring 308 is formed on the surface of the same semiconductor chip to make an electrical connection in the same circuit. The rewiring 307 is formed across the semiconductor chips 301 and 302 across the scribe line area 303, and makes electrical connection between the semiconductor chips. A new pad 306 is formed at the position of the original pad 311. Except for the new pad 306, an insulating layer 316 is formed on the surfaces of the semiconductor chips 301 and 302 including the scribe line area 303. A solder bump 305 for connection is formed.

As shown in FIG. 3, a large number of semiconductor chips 301 and 302 having such a connection structure are collectively formed on one wafer 401 in the same semiconductor process manufacturing process. A scribe line area 404 is set in a direction parallel to the orientation flat 402, and scribe line areas 403 and 405 are alternately set in a direction perpendicular to the orientation flat.
The scribe line area 403 includes the semiconductor chip 301,
It serves as a dividing line for 302.

By dicing the scribe line regions 404 and 405, the semiconductor chips 301 and 30 can be diced.
2 are separated from the wafer as a chipset. By mounting the semiconductor chips 301 and 302 thus formed on a substrate having external connection terminals having the same pitch as the solder bumps 305, a chip scale package can be formed without providing a wiring pattern on the substrate.

According to the above configuration, re-wirings 307 and 308 are formed on the surfaces of a number of adjacent semiconductor chips 301 and 302 on the wafer, including scribe line regions 403, for making electrical connection between the semiconductor chips. When dicing, the scribe line area 403 is excluded from the dicing target, and the two semiconductor chips are separated from the wafer as a chip set. Therefore, the electrical connection between the semiconductor chips is achieved by the rewiring 307 formed on the surface of the semiconductor chip. This eliminates the need for independent solder bumps for connection between semiconductor chips.

Therefore, compared with the case where the original pads are provided with solder bumps and connected to the substrate, and the connection between the semiconductor chips is made by the wiring pattern on the substrate, the number of connection points with the substrate is reduced, and the connection failure such as connection failure is reduced. The possibility of occurrence is reduced, and a highly reliable chip scale package can be configured. In addition, because the connection distance is shorter, the stray capacitance is smaller, the signal transmission time is shorter, etc.
Signal transmission is also speeded up.

In this embodiment, the new pad 306 is formed at the position of the original pad 311. However, the new pad 306 is re-wired from the original pad to the insulating layer.
A new pad can be formed on the rewiring. For example, by arranging new pads in a grid and forming solder bumps in a grid, it is possible to connect to a substrate on which external connection terminals are arranged in the same grid without a wiring pattern.

Next, an example of applying the above structure to an actual electronic circuit will be described. FIG. 4 is a diagram showing a circuit configuration of a MOS transistor. The diode 502 is connected to the MOS transistor 501. That is, the anode and the cathode of the diode 502 are connected to the source and the drain of the MOS transistor 501, respectively. When an electric surge is applied to the drain of the MOS transistor 501, the diode 502 serves to absorb the surge noise. A semiconductor chip including the diode 502 and forming the MOS transistor 501 is mounted on a substrate to form a chip scale package. External connection terminals 503 and 50 respectively connected to the gate, drain and source of the MOS transistor 501
4, 505 are provided on the substrate.

FIG. 5 shows a configuration in which the two MOS transistors of FIG. 4 are connected in parallel. MOS transistors 505 and 507 are respectively composed of diodes 506 and 50.
9 and both drains, sources, and gates are connected to each other. When two MOS transistors are connected in parallel in this manner, a drain current approximately twice as large as that of a single MOS transistor can be passed. Similarly, if four MOS transistors are connected in parallel, a drain current about four times as large can be generated. Conventionally, in such a circuit, two or four semiconductor chips of a single MOS transistor shown in FIG. 4 are mounted on a substrate, and connection between the semiconductor chips is performed by a wiring pattern on the substrate, and each gate, The drain and the source are connected to the external connection terminals 510, 511, 512.

FIGS. 6 and 7 show, as a first embodiment, the configuration of a semiconductor chip when the above two MOS transistors are connected in parallel. FIG. 6 is a plan view of the semiconductor chip viewed from the solder bump side, with the insulating layer on the surface removed. FIG. 7 is a sectional view taken along the line EE in FIG. Here, two semiconductor chips 701 and 702 forming a MOS transistor including a diode are formed adjacently on the same wafer, and are cut out as a chip set without being separated from each other.

In each semiconductor chip, a p-type region 13 serving as a drain region and a high-concentration p-type region 14 surrounding the p-type region 13 are formed in the n-type region 12 of the wafer substrate. The back surface in contact with the n-type region 12 is a high-concentration n-type layer 11. A high-concentration n-type region 15 reaching the high-concentration n-type layer 11 is provided in a columnar shape around the high-concentration p-type region 14. The portion of the n-type region 12 surrounding the high-concentration p-type region 14 forms a source region, and the high-concentration n-type layer 11
The high-concentration n-type region 15 is a source lead region. The p-type region 13 and the high-concentration p-type region 14 form a diode.

On the surface of the wafer substrate, an n-type region 16 is formed in a ring shape from the p-type region 13 to the high-concentration p-type region 14.
Are formed to form a drain region, and a p-type region 17 is provided as a channel on the outer peripheral side thereof. On the surface of the wafer substrate on which these regions are formed, the channel p
A gate oxide film 18 is formed in a ring shape facing mold region 17, and a polysilicon layer 19 is provided on gate oxide film 18 to form a gate region. Gate oxide film 1
8 and the polysilicon layer 19 are surrounded by an insulating layer 20.
High concentration n-type region 15 and n-type region 1 penetrating through insulating layer 20
6, contacts 21, 22, and 23 are formed to be connected to the polysilicon layer 19, respectively. The source pad 717, the drain pad 716, and the gate pad 7 are connected to these contacts.
15 are formed.

On the insulating layers of the semiconductor chips 701 and 702 including the scribe line area 706, the rewiring 703,
704 and 705 are formed, and both the source region (source extraction, high-concentration n-type region 15), the drain region (n-type region 16), and the gate region (polysilicon layer 19) are connected to each other between the pads. In FIG. 6, the internal gate region is indicated by a solid line. Then, the wirings 703 and 70
4 and 705, a plurality of pads 717, 716, and 715 are formed, and solder bumps 628, 626, and 625 are formed here.
Are formed. Rewiring 703 except for solder bumps,
704 and 705 are covered with the insulating film 22.

By mounting the semiconductor chips 701 and 702 on a substrate, a drain current approximately twice as large as that of a single MOS transistor can be generated without providing a wiring pattern on the substrate. Thus, two MOS
Since the connection between the transistors is performed by rewiring on the surface of the semiconductor chip, the connection distance between the circuits is shortened, and the speed of signal transmission can be increased as compared with the connection via the substrate.

FIG. 8 shows, as a second embodiment, a wafer formed by connecting in parallel four semiconductor chips on which MOS transistors are formed including diodes.
The cross-sectional structure from the insulating layer 20 where the MOS transistor is formed to the high-concentration n-type layer 11 is the same as that shown in FIG. Rewiring lines 805, 806, 807 are formed on the surfaces of the semiconductor chips 801, 802, 803, and 804 including the scribe line regions 808, 809, and the respective gate regions, source regions, and drain regions are connected to each other.

Scribe line areas 810, 811 and 8
By dicing the wafer along the lines 12 and 813, four semiconductor chips connected in parallel to each other are separated as a chip set. By mounting the semiconductor chip having the four connected to the substrate in this manner, it is possible to flow about four times as many drains as a single MOS transistor without providing a wiring pattern on the substrate. Since the connection between the semiconductor chips is performed by rewiring formed on the surface of the semiconductor chip in the same manner as described above, the same effects as those in FIGS. 6 and 7 can be obtained.

Further, by using a semiconductor chip of a large number of MOS transistors formed on a wafer and connecting the semiconductor chips by rewiring formed on the surface thereof, the semiconductor chips can be cut and used in accordance with a required drain current. Can also. For example, a device for connecting four semiconductor chips is formed on a wafer, and a scribe line region 808, 809 is diced to form a chip set including two MOS transistor semiconductor chips. Also in this case, since the connection between the semiconductor chips has already been made, a chip scale package can be configured without providing a wiring pattern on the substrate.

Next, a second embodiment will be described. The rewiring described above is a limited wiring pattern in which only the MOS transistors of a group of semiconductor chips to be packaged in one package are connected in parallel in the first embodiment. Rewiring is performed by forming a large number of semiconductor chips on a wafer and then performing wiring patterning thereon. When the wiring pattern changes according to the package specifications (the number of semiconductor chips or the number of MOS transistors), the wiring patterning is performed. It is necessary to set and create a dedicated photomask limited to each package specification each time. Therefore, the second embodiment eliminates the need for changing the photomask as a common wiring pattern regardless of the number of semiconductor chips to be packaged.

FIG. 9 is an overall plan view of a semiconductor chip formed on a wafer according to the second embodiment as viewed from the solder bump side. A plurality of semiconductor chips 850, 850, 850,.
Are formed on the same wafer by the same semiconductor manufacturing process. An insulating layer is provided on the surface of each semiconductor chip 850 including the scribe line regions 852 and 854, and a rewiring is formed in the insulating layer.

The rewiring is performed by three horizontal wirings 860 of an X-direction source wiring 861, an X-direction drain wiring 862, and an X-direction gate wiring 863, which extend horizontally at an interval from each other for each semiconductor chip 850. The vertical wiring 870 includes three vertical wirings 870 vertically extending at intervals with a Y-direction source wiring 871, a Y-direction drain wiring 872, and a Y-direction gate wiring 873. The vertical wiring 870 of the vertically adjacent semiconductor chip crosses the scribe line 852 and continues through each semiconductor chip, and the horizontal wiring 860 of the horizontally adjacent semiconductor chip crosses the scribe line 854 and continues through each semiconductor chip.

In each semiconductor chip 850, the X-direction source wiring 861 and the Y-direction source wiring 871 are electrically connected at the intersection, and are connected to the source region of the MOS transistor at the intersection. Similarly, the X-direction drain wiring 862 and the Y-direction drain wiring 872 are electrically connected at the intersection, and are connected to the drain region at the intersection. Also, the X-direction gate wiring 86
3 and the Y-direction gate wiring 873 are electrically connected at the intersection thereof, and the intersection and the gate region are connected by the gate rearrangement wiring 865. Then, pads 881, 882, 883 are formed on each of the electrically connected intersections, and solder bumps 885, 886, 88 are formed on these pads.
7 are formed.

FIGS. 10 and 11 show, as a third example according to this embodiment, an enlarged concrete structure of two adjacent semiconductor chip portions. 10 is a plan view as viewed from the solder bump side, FIG. 11A is a cross-sectional view taken along the line FF in FIG. 10, FIG. 11B is a cross-sectional view taken along the line HH, and FIG. It is. FIG. 10 shows the vertical wiring and the horizontal wiring and the gate region by removing the insulating layer on the surface.
Each semiconductor chip 850 forms a p-type region 33 serving as a drain region and a high-concentration p-type region 34 surrounding the p-type region 33 adjacent to the p-type region 33 in the n-type region 32 of the wafer substrate. The back surface in contact with the region 32 is a high-concentration n-type layer 31.

A high-concentration n-type region 35 reaching the high-concentration n-type layer 31 is provided in a column shape or a ring shape surrounding the high-concentration p-type region 34 outside the high-concentration p-type region 34. The n-type region portion 32 surrounding the high-concentration p-type region 34 forms a source region, and the high-concentration n-type layer 31 and the high-concentration n-type region 35
Is a source extraction region.

An insulating layer 40 is provided on the surface of the wafer substrate. Inside the insulating layer, a gate oxide film 38 is formed in a ring shape facing the high-concentration p-type region 34 as a channel. A polysilicon layer 39 overlying the film 38;
Are provided to form a gate region. The gate oxide film 38 and the polysilicon layer 39 are surrounded by the gate insulating film 36. Note that, as in the first embodiment, p
A diode is formed by the mold region 33 and the high-concentration p-type region 34.

X-direction source wiring 861, X-direction drain wiring 862, and X-direction gate wiring 863 of the horizontal wiring,
Vertical wiring Y-direction source wiring 871, Y-direction drain wiring 872 and Y-direction gate wiring 873 are provided in the insulating layer 40, and as shown in FIGS. 11 (a), (b) and (c). The wirings (871, 872, 873) and the horizontal wirings (861, 862, 863) are arranged at different distances from the surface of the insulating layer 40 so as not to cross each other. In order to facilitate understanding, FIG.
In (c), the p-type region 33 and the high-concentration p-type region 34 are depicted in the same manner as in (b).

As shown in FIG. 11A, an X-direction source wiring 861 and a Y-direction source wiring 871 are connected by a contact 51 at an intersection in a plan view.
At this connection site, a source pad 881 is formed on the surface of the insulating layer 40. X direction source wiring 86
1 and a source lead-out region (high-concentration n-type region 35) are connected by a contact 50, and a Y-direction source wiring 871 and a pad 881 are connected by a contact 52, respectively, and a solder bump 885 is provided on the pad 881.

Further, as shown in FIG. 11B, the X-direction drain wiring 862 and the Y-direction drain wiring 872 are connected by the contact 55 at the intersection in the plan view, and the insulating layer 40 is A drain pad 882 is formed on the surface. The X-direction drain wiring 862 and the drain region (p-type region 33) are connected by the contact 54, and the Y-direction drain wiring 872 and the pad 882 are connected by the contact 56, respectively, and a solder bump 886 is provided on the pad 882.

Similarly, as shown in FIG.
The directional gate wiring 863 and the Y-directional gate wiring 873 are connected by the contact 60 at the intersection in the plan view, and a pad 883 for a gate is formed on the surface of the insulating layer at this connection part. A gate rearrangement wiring 86 is provided between the intersection of the X direction gate wiring 863 and the Y direction gate wiring 873 and the gate region (polysilicon layer 39).
5, the gate rearrangement wiring 865 and the gate region are connected by the contact 58, the gate rearrangement wiring 865 and the X-direction gate wiring 863 are connected by the contact 59, and the Y-direction gate wiring 873 and the pad 883 are connected by the contact 61, respectively. On the pad 883, a solder bump 887 is provided.

The rewiring structure in the above semiconductor chip is formed by the following basic procedure. After a plurality of single MOS transistors are formed on a wafer substrate by a normal semiconductor process, (1) First, a source region (lead source, high-concentration n-type region 35) and a drain region (p-type region 3) are formed on the surface protective film.
3) A contact hole with the gate region (polysilicon layer 39) is formed. (2) Copper plating is performed on this, patterning is performed, contacts 50, 54, 58 are formed in the contact holes, and then polyimide is applied to the entire surface.

(3) Next, an opening is formed in the polyimide contact region by patterning, and the X-direction source wiring 861, the X-direction drain wiring 862, and the X-direction gate wiring 863 of the horizontal wiring are formed by copper film formation by photolithography. It is formed by connecting to a contact. (4) Further, copper plating is performed, patterning is performed, contacts 51, 55, and 60 are formed on the horizontal wiring, and polyimide is applied to the entire surface. (5) Then, as in the case of the horizontal wiring, an opening is formed in the polyimide contact region by patterning, and the Y-directional source wiring 87 of the vertical wiring is formed by copper film formation by photolithography.
1, formed by connecting a Y-direction drain wiring 872 and a Y-direction gate wiring 873 to corresponding contacts.

(6) Further, copper plating and patterning are performed to form contacts 52, 56 and 61 on the vertical lines, and polyimide is applied to the entire surface. (7) Subsequently, an opening is formed in the polyimide contact region by patterning, and the contacts 52, 56, and 6 are formed by copper film formation.
The pads 881, 882, and 883 connected to No. 1 are formed to form source, drain, and gate pads. (8) Then, the solder ball is connected to the intersection of the above-described X-direction source wiring 861 and Y-direction source wiring 871 on each pad,
X direction drain wiring 862 and Y direction drain wiring 872
, The X direction gate wiring 863 and the Y direction gate wiring 8
The solder bumps 885, 88
6, 887.

If the contact hole with the gate region formed in the step (1) cannot be made to coincide with the intersection of the X-direction gate wiring 863 and the X-direction gate wiring 873 as in this embodiment, Before the horizontal wiring of (3), one end is connected to the contact 58 by the same method as in the steps (3) and (4).
And the other end is extended to a position corresponding to the intersection of the X-direction gate wiring 863 and the Y-direction gate 873 wiring to form a gate rearrangement wiring 865. The insulating layer 40 is made of polyimide that is applied a plurality of times as an interlayer insulating film. As this insulating layer, a PSG film or a silicon nitride film may be used instead, and only the outermost surface may be made of polyimide.

When the number of semiconductor chips to be packaged in one package is arbitrarily set and diced and cut out from the wafer on which the MOS transistors and wirings are formed as described above, the number of set semiconductor chips is However, the source, drain and gate of each MOS transistor of the group of semiconductor chips are
0 and the horizontal wiring 860 are connected in parallel, and the solder bumps 885 and 88 for connection to the mounting board are provided.
6, 887 are provided in each of the semiconductor chips 850 to obtain a chip scale package.

The X-directional source wiring 861 of the horizontal wiring,
X direction drain wiring 862 and X direction gate wiring 86
3 do not intersect in parallel with each other through a plurality of semiconductor chips adjacent in the horizontal direction, and similarly, the Y-direction source wiring 871, the Y-direction drain wiring 872, and the Y-direction gate wiring 873 of the vertical wiring also have a plurality of vertically adjacent semiconductor chips. Since the semiconductor chips do not cross each other in parallel, regardless of the wafer size or the size of each semiconductor chip, it is easy to set the photomask used for forming the wiring in steps (3) and (5), and one package. It is not necessary to change the photomask even if the number of semiconductor chips to be formed is changed arbitrarily. This reduces manufacturing costs.

Further, since the horizontal wiring and the vertical wiring are connected at the intersections which are orthogonal to each other, they are connected at the shortest distance.
The transmission time of the electric signal is reduced. Since the pads are provided at the intersections of the horizontal wiring and the vertical wiring, it is easy to standardize the pad positions, and also serve as positioning marks when providing solder bumps, and the solder bumps are arranged in a grid-like arrangement with the mounting board. Can be easily handled.

FIGS. 12 and 13 show a fourth embodiment, in which a solder bump for heat dissipation is further provided in the previous embodiment. FIG. 12 is a plan view seen from the solder bump side, and FIG.
12A is a sectional view taken along the line KK in FIG. 12, and FIG.
FIG. 3C is a cross-sectional view of an L part, and FIG. In addition,
FIG. 12 shows vertical wiring and horizontal wiring by removing the insulating layer on the surface,
And a gate. 13 (a) and 13 (c), the source, the drain, the gate and the high-concentration p-type region are illustrated in the same manner as in FIG. 13 (b).

In particular, as shown in FIG. 12, the respective pads 881, 88 for the source, the drain and the gate are provided.
Reference numerals 2 and 883 denote the intersections of the X-direction source wiring 861 and the Y-direction source wiring 871, the intersections of the X-direction drain wiring 862 and the Y-direction drain wiring 872, and the X-direction gate wiring 863 and the Y-direction gate, respectively, as in the previous embodiment. Solder bumps 885, 886, and 887 are provided at the intersections of the wirings 873 and these pads are provided.

Further, in this embodiment, the intersection of the vertical wiring and the horizontal wiring other than the point where the pads 881, 882, 883 are provided in each semiconductor chip, that is, the X-direction source wiring 861 and the Y-direction drain wiring 872, Each intersection of the Y-direction gate wiring 873 and the X-direction drain wiring 86
2, Y-direction source wiring 871 and Y-direction gate wiring 8
A solder bump 890 is provided at each intersection of the X-direction gate wiring 863, the Y-direction source wiring 871, and the Y-direction drain wiring 872. Other configurations are the same as the previous embodiment.

In the present embodiment having such a configuration, in addition to the effects of the previous embodiment, the added solder bumps 890 are provided.
Along with source, drain and gate pads,
Heat dissipation means uniformly distributed on the surface of the semiconductor chip to stabilize the operating characteristics of the semiconductor chip. Also,
If the wiring intervals of vertical wiring and horizontal wiring are made equal, all solder bumps will be arranged at a common pitch interval,
There is no risk that the high density is hindered by some of the adjacent wirings, and the solder bump arrangement is standardized.

In each of the above embodiments, the rewiring is formed on the semiconductor chip and the connection between the semiconductor chips is performed. However, it is needless to say that the wiring pattern is formed on the substrate and the semiconductor This does not preclude the use of a conventional connection structure for connecting chips. By using them together, a more complicated connection can be made.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line CC in FIG.

FIG. 3 is a diagram showing an arrangement of semiconductor chips on a wafer.

FIG. 4 is a diagram showing a circuit configuration of a MOS transistor.

FIG. 5 is a diagram showing a circuit configuration in which two MOS transistors are connected in parallel;

FIG. 6 is a plan view of the semiconductor chip showing the first embodiment.

FIG. 7 is a sectional view taken along the line EE in FIG. 6;

FIG. 8 is a plan view of a semiconductor chip showing a second embodiment.

FIG. 9 is an overall plan view according to the second embodiment.

FIG. 10 is a plan view of a semiconductor chip showing a third embodiment.

11 is a cross-sectional view of the FF portion, the HH portion, and the JJ portion in FIG.

FIG. 12 is a plan view of a semiconductor chip showing a fourth embodiment.

13 is a cross-sectional view of a KK portion, an LL portion, and an MM portion in FIG.

FIG. 14 is a plan view showing a configuration of a conventional example.

15 is a cross-sectional view taken along the line AA in FIG.

FIG. 16 is a plan view showing a configuration of a semiconductor package using a plurality of semiconductor chips.

FIG. 17 is a sectional view taken along the line BB in FIG. 16;

[Explanation of symbols]

11, 31 high-concentration n-type layer 12, 16, 32 n-type region 13, 17, 33 p-type region 14, 34 high-concentration p-type region 15, 35 high-concentration n-type region 16 n-type region 18, 38 Gate oxide film 19, 39 Polysilicon layer 20, 40 Insulating layer 21, 22, 23 Contact 36 Gate insulating film 50, 51, 52, 54, 55, 56, 58, 59, 6
0, 61 Contact 301, 302 Semiconductor chip 303 Scribe line area 305 Solder bump 306 New pad 307, 308 Rewiring 311, 317 Original pad 315, 316 Insulating layer 401 Wafer 402 Orientation flat 403, 404, 405 Scribe line area 501, 506 , 607 MOS transistors 502, 508, 509 Diodes 503, 504, 505, 510, 511, 512
External connection terminal 625, 626, 628 Solder bump 701, 702 Semiconductor chip 703, 704, 705 Rewiring 706 Scribe line area 715, 716, 717 Pad 850 Semiconductor chip 852, 854 Scribe line 860 Horizontal wiring 861 X direction source wiring 862 X Direction drain wiring 863 X direction gate wiring 870 Vertical wiring 871 Y direction source wiring 872 Y direction drain wiring 873 Y direction gate wiring 865 Gate rearrangement wiring 881, 882, 883 Pad 885, 886, 887, 890 Solder bump

Claims (7)

[Claims] 1. A semiconductor package in which a plurality of semiconductor chips electrically connected to each other are mounted on a substrate, wherein the plurality of semiconductor chips are formed on the same wafer, and the plurality of semiconductor chips are provided on a surface of the plurality of semiconductor chips. Re-wiring is formed between the semiconductor chips, and electrical connection between the semiconductor chips is performed, the plurality of semiconductor chips are separated from the wafer without being divided from each other, and attached to the substrate as a chip set. Semiconductor mounting structure characterized by the above-mentioned. 2. In the semiconductor chip, a new pad is set at a different position from an original pad connected to a circuit, and the connection between the new pad and the original pad is
2. The semiconductor mounting structure according to claim 1, wherein rewiring is performed on a surface of the semiconductor chip, and the new pad position is made to correspond to an external connection terminal on the substrate. 3. A semiconductor chip set including a plurality of semiconductor chips electrically connected to each other and mounted on a substrate, wherein the plurality of semiconductor chips are selected from a number of semiconductor chips formed on the same wafer. A group of adjacent semiconductor chips is separated from the wafer without being divided from each other.
Rewiring composed of a plurality of vertical wirings and horizontal wirings extending over all the semiconductor chips in adjacent vertical and horizontal directions is formed in a grid pattern, and predetermined intersections of the vertical wirings and the horizontal wirings are electrically connected. A semiconductor chip set characterized by the following. 4. The semiconductor chip set according to claim 3, wherein a pad for connection to a substrate is provided at the predetermined intersection. 5. A transistor is formed on each of the plurality of semiconductor chips, the horizontal wiring includes an X-direction source wiring, an X-direction drain wiring, and an X-direction gate wiring, and the vertical wiring includes a Y-direction source wiring and a Y-direction. It comprises a drain wiring and a Y-directional gate wiring, and as the predetermined intersection, at an intersection of an X-directional source wiring and a Y-directional source wiring,
A source region of the transistor is connected, a source pad is provided, and a drain region of the transistor is connected to an intersection of the X-direction drain wiring and the Y-direction drain wiring, and a drain pad is provided. 5. The semiconductor chip set according to claim 4, wherein a gate region of the transistor is connected to an intersection of the wiring and the Y-direction gate wiring, and a gate pad is provided. 6. A gate region of the transistor is connected to an intersection of an X-direction gate wiring and a Y-direction gate wiring via a gate rearrangement wiring, and the X-direction source wiring, the X-direction drain wiring, and the X-direction gate wiring are connected to each other. 6. The semiconductor chip set according to claim 5, wherein the Y-direction source wiring, the Y-direction drain wiring, and the Y-direction gate wiring are provided at equal intervals. 7. A bump is formed at a predetermined intersection electrically connected between the vertical wiring and the horizontal wiring, and bumps are formed at all intersections which are not electrically connected. The semiconductor chip set according to claim 3, 4, 5, or 6.