KR100271631B1 - Align key manufacturing wafer of semiconductor - Google Patents

Align key manufacturing wafer of semiconductor Download PDF

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KR100271631B1
KR100271631B1 KR1019970046070A KR19970046070A KR100271631B1 KR 100271631 B1 KR100271631 B1 KR 100271631B1 KR 1019970046070 A KR1019970046070 A KR 1019970046070A KR 19970046070 A KR19970046070 A KR 19970046070A KR 100271631 B1 KR100271631 B1 KR 100271631B1
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South Korea
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vernier
wafer
process vernier
scale
alignment
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KR1019970046070A
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Korean (ko)
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KR19990024743A (en
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이동규
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김영환
현대반도체주식회사
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: A structure of an align key for manufacturing a semiconductor wafer is provided to increase efficiency in using a space, by simultaneously measuring an alignment in X and Y directions by using a pair of verniers. CONSTITUTION: A previous process vernier(100) is widthwise formed on a wafer. A present process vernier(200) is formed on a mask, and has a scale broader than that of the previous process vernier by a predetermined interval so that the present process vernier is located in a position for aligning the present process vernier in the previous process vernier. The interval between the lower scale part of the previous process vernier and the upper scale part of the present process vernier becomes broader gradually as it goes from the center to the right by a predetermined ratio, and becomes overlapped gradually as it goes from the center to the left. An alignment is measured in X and Y directions by using a pair of verniers.

Description

반도체 웨이퍼 제조용 얼라인 키 형성구조{ALIGN KEY MANUFACTURING WAFER OF SEMICONDUCTOR}Alignment key formation structure for semiconductor wafer manufacturing {ALIGN KEY MANUFACTURING WAFER OF SEMICONDUCTOR}

본 발명은 반도체 웨이퍼 제조용 얼라인 키 형성구조에 관한 것으로, 특히 공간이용 효율을 향상시켜서 디바이스의 고집적화 설계를 가능토록 하는데 적합한 반도체 웨이퍼 제조용 얼라인 키 형성구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alignment key forming structure for semiconductor wafer fabrication, and more particularly, to an alignment key forming structure for semiconductor wafer fabrication suitable for enabling high integration design of devices by improving space utilization efficiency.

일반적으로 제조공정이 진행중인 웨이퍼의 스크라이브 레인 상에는 각종 얼라인 키들이 형성되어 있다. 즉, W검 TEG, 식각 모니터링 키 및 각 장비의 버니어 키등이다. 이러한 얼라인 키들은 주어진 공간 안에서 형성되어야 하므로 고집적화되는 최근의 디바이스 추세에서는 설계상의 어려움이 있는 것이 사실이다.Generally, various alignment keys are formed on a scribe lane of a wafer in which a manufacturing process is in progress. That is, W gum TEG, etch monitoring key and vernier key of each equipment. Since these alignment keys must be formed within a given space, it is true that there is a design difficulty in the recent trend of highly integrated devices.

도 1은 종래 웨이퍼에 X,Y축 사전공정 버니어가 형성된 상태를 보인 평면도로서, 도시된 바와 같이, 종래에는 웨이퍼(W)의 스크라이브 레인 상에 가로방향으로 X축 사전공정 버니어(1)가 형성되어 있고, 그 X축 사전공정 버니어(1)의 주변에 세로방향으로 Y축 사정공정 버니어(11)가 형성되어 있다.1 is a plan view showing a state in which the X, Y-axis preprocessing vernier is formed on a conventional wafer, as shown in the prior art, the X-axis preprocessing vernier 1 is formed on the scribe lane of the wafer W in a horizontal direction. The Y-axis assessment process vernier 11 is formed in the vertical direction around the X-axis preprocess vernier 1.

그리고, 상기 X,Y축 사전공정 버니어(1)(11)는 각각 3.90μm간격으로 형성된 10개의 눈금(2)(12)이 형성되어 있고, 그 눈금(2)(12)의 후단부에는 각각 연결부(3)(13)가 형성되어 있다.In addition, the X, Y axis pre-process vernier (1) (11) is formed with ten graduations (2) (12) formed at intervals of 3.90μm, respectively, and each of the rear ends of the graduations (2) (12) The connecting parts 3 and 13 are formed.

또한, 상기 연결부(3)(13)의 중앙 상단부에는 센타점(4)(14)이 각각 형성되어 있고, 양단부에는 +,- 표시가 각각 되어 있다.In addition, center points 4 and 14 are formed at upper ends of the connecting parts 3 and 13, respectively, and both ends are marked with + and-marks.

도 2는 종래 마스크에 X,Y축 버니어가 형성된 상태를 보인 평면도로서, 도시된 바와 같이, 종래에는 마스크(M)에 상기 X축 사전공정 버니어(1)에 얼라인 하기 위한 X축 현공정 버니어(21)가 가로방향으로 형성되어 있고, 그 X축 현공정 버니어(21)의 주변에 세로방향으로 Y축 현공정 버니어(31)가 형성되어 있다.Figure 2 is a plan view showing a state in which the X, Y-axis vernier is formed in the conventional mask, as shown in the prior art, X-axis current process vernier for aligning the X-axis pre-process vernier (1) in the mask (M) (21) is formed in the horizontal direction, and the Y-axis current process vernier 31 is formed in the longitudinal direction around the X-axis current process vernier 21. As shown in FIG.

그리고, 상기 X,Y축 현공정 버니어(21)(31)는 각각 4.00μm 간격으로 형성된 10개의 눈금(22)(32)이 형성되어 있고, 그 눈금(22)(32)의 후단부에는 각각 연결부(23)(33)가 형성되어 있으며, 그 연결부(23)(33)의 중앙 상단부에는 센타점(24)(34)이 각각 형성되어 있다.In addition, the X, Y-axis current process vernier (21) (31) is formed with ten scales (22) 32 formed at intervals of 4.00 µm, respectively, and the rear ends of the scales (22) 32, respectively. The connection parts 23 and 33 are formed, and center points 24 and 34 are formed in the upper end part of the connection parts 23 and 33, respectively.

상기와 같이 형성되어 있는 버니어들을 이용하여 웨이퍼에 마스크를 얼라인 하는 동작을 도 3을 참조하여 설명하면 다음과 같다.An operation of aligning a mask on a wafer using verniers formed as described above will be described with reference to FIG. 3.

웨이퍼 척의 상면에 웨이퍼(W)를 얹어 놓은 상태에서 장비에 마스크(M)를 설치한 다음, 웨이퍼(W)의 스크라이브 레인 상에 형성되어 있는 X,Y축 사전공정 버니어(1)(11)에 마스크(M)의 X,Y축 현공정 버니어(21)(31)를 도 3과 같이 얼라인한다.The mask M is installed in the apparatus with the wafer W placed on the upper surface of the wafer chuck, and then the X and Y axis pre-process vernier 1, 11 formed on the scribe lane of the wafer W. The X and Y axis current process vernier 21 and 31 of the mask M are aligned as shown in FIG.

즉, 상기 X,Y축 사전공정 버니어(1)(11)의 눈금간격과 X,Y축 현공정 버니어(21)(31)의 눈금간격의 차이는 0.1μm의 차이가 있기 때문에 X,Y축 사전공정 버니어(1)(11)의 센타점(4)(14)에서 + 또는 - 방향으로 어떤 눈금(2)(12)에 X,Y축 현공정 버니어(21)(31)의 어떤 눈금(22)(32)이 일치하였는가를 확인하여 규정치 이내에 들어오면 얼라인을 종료하고 노광을 실시하게 된다.That is, the difference between the scale intervals of the X, Y-axis pre-process vernier (1) 11 and the scale intervals of the X, Y-axis current process vernier (21) (31) is 0.1 μm difference, so the X, Y-axis Any scale of the X, Y axis current process vernier 21, 31 at any scale (2) 12 in the + or-direction at the center point (4) (14) of the preprocess vernier (1) (11) ( 22) (32) is checked to see if they match, and when it is within the specified value, alignment is terminated and exposure is performed.

그러나, 상기와 같은 종래 반도체 웨이퍼 제조용 얼라인 키는 웨이퍼(W)와 마스크(M)에 반드시 X축 버니어(1)(21)와 Y축 버니어(11)(31)를 함께 형성하여야 하기 때문에 이 2쌍의 측정용 버니어를 형성함에 따라 공간을 많이 차지하게 되어 디바이스의 고집적화에 저해되는 문제점이 있었다.However, in the conventional semiconductor wafer manufacturing alignment key as described above, the X-axis vernier (1) 21 and the Y-axis vernier (11) (31) must be formed together on the wafer (W) and the mask (M). The formation of two pairs of measurement vernier takes up a lot of space, there is a problem that inhibits the high integration of the device.

상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 1쌍의 버니어를 이용하여 XY방향의 얼라인을 동시에 측정하도록 하여 공간이용효율을 향상시킴과 동시에 정렬정밀도를 향상시키도록 하는데 적합한 반도체 웨이퍼 제조용 얼라인 키 형성구조를 제공함에 있다.An object of the present invention devised in view of the above problems is to manufacture a semiconductor wafer suitable for improving alignment efficiency in the XY direction using a pair of vernier at the same time to improve space utilization efficiency and alignment accuracy. It is to provide an alignment key forming structure.

도 1은 종래 웨이퍼에 X,Y축 버니어가 형성된 상태를 보인 평면도.1 is a plan view showing a state in which the X, Y-axis vernier is formed on a conventional wafer.

도 2는 종래 마스크에 X,Y축 버니어가 형성된 상태를 보인 평면도.Figure 2 is a plan view showing a state in which the X, Y-axis vernier is formed in a conventional mask.

도 3은 종래 웨이퍼에 마스크를 얼라인하는 상태를 보인 평면도.3 is a plan view illustrating a state in which a mask is aligned with a conventional wafer.

도 4는 본 발명 반도체 웨이퍼 제조용 얼라인 키 형성구조를 보인 평면도.Figure 4 is a plan view showing an alignment key forming structure for manufacturing a semiconductor wafer of the present invention.

* * 도면의 주요 부분에 대한 부호의 설명 * ** * Explanation of symbols for the main parts of the drawing * *

100 : 전공정 버니어 101 : 눈금100: front process vernier 101: scale

101a: 하단부 102 : 연결부101a: lower part 102: connection part

103 : 센타점 200 : 현공정 버니어103: center point 200: current process vernier

201 : 눈금 201a : 상단부201: graduation 201a: upper part

202 : 연결부 203 : 센타점202: connecting portion 203: center point

상기와 같은 본 고안의 목적을 달성하기 위하여 웨이퍼에 형성되는 전공정 버니어를 가로방향으로 형성하고, 마스크에 형성되며 전공정 버니어 눈금간격 보다 일정간격 넓게 눈금간격이 형성된 현공정 버니어를 상기 전공정 버니어에 얼라인 할 수 있도록 대향되는 위치에 형성하며, 상기 전공정 버니어의 눈금 하단부와 현공정 버니어의 눈금 상단부의 간격은 센타점에서 우측으로 갈수록 일정비율로 점차적으로 넓어지고, 좌측으로 갈수록 일정비율로 점차적으로 중첩되도록 하여, 1쌍의 버니어를 이용하여 XY방향의 얼라인을 측정하도록 한 것을 특징으로 하는 반도체 웨이퍼 제조용 얼라인 키 형성구조가 제공된다.In order to achieve the object of the present invention as described above, the previous process vernier is formed on the wafer in the transverse direction, and the current process vernier is formed on the mask and has a predetermined interval wider than the previous process vernier scale interval. The gap between the lower end of the scale of the previous process vernier and the upper end of the scale of the current process vernier gradually widens at a constant ratio from the center point to the right, and at the constant ratio toward the left. There is provided an alignment key forming structure for manufacturing a semiconductor wafer, wherein the alignment key formation structure is measured such that the alignment in the XY direction is measured using a pair of vernier.

이하, 상기와 같은 본 발명 반도체 웨이퍼 제조용 얼라인 키 형성구조를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the alignment key forming structure for manufacturing a semiconductor wafer of the present invention as described above will be described in more detail with reference to an embodiment of the accompanying drawings.

도 4는 본 발명 반도체 웨이퍼 제조용 얼라인 키 형성구조를 보인 평면도로서, 도시된 바와 같이, 본 발명은 웨이퍼에 가로방향으로 전공정 버니어(100)를 형성하고, 그 전공정 버니어(100)의 하측에 마스크에 가로방향으로 형성된 현공정 버니어(200)을 얼라인할 수 있도록 되어 있다.4 is a plan view showing an alignment key forming structure for manufacturing a semiconductor wafer of the present invention. As shown in the drawing, the present invention forms a preprocessing vernier 100 in a transverse direction on a wafer, and the lower side of the preprocessing vernier 100. The current process vernier 200 formed in the transverse direction on the mask can be aligned.

상기 전공정 버니어(100)는 3.90μm의 간격으로 가로방향으로 10개의 눈금(101)들이 나열설치되어 있고, 그 눈금(101)들의 후단부에는 연결부(102)가 형성되어 있으며, 그 연결부(102)의 중앙에는 센타점(103)이 형성되어 있고, 상기 연결부(102)의 양단부에는 +.-표시가 되어 있다.The pre-process vernier 100 is provided with 10 graduations 101 arranged in the horizontal direction at intervals of 3.90μm, the connecting portion 102 is formed at the rear end of the graduations 101, the connection portion 102 A center point 103 is formed at the center of the cross-section, and both ends of the connecting portion 102 are marked with + .-.

상기 현공정 버니어(200)는 4.00μm의 간격으로 10개의 눈금(201)들이 가로방향으로 나열설치되어 있고, 그 눈금(201)들의 후단부에는 연결부(202)가 형성되어 있으며, 그 연결부(202)의 중앙에는 센타점(203)이 형성되어 있다.In the current process vernier 200, ten scales 201 are arranged in a horizontal direction at intervals of 4.00 μm, and connecting portions 202 are formed at rear ends of the scales 201 and the connecting portions 202. The center point 203 is formed in the center of the figure.

그리고, 상기 전공정 버니어(100)의 눈금(101) 하단부(101a)와 현공정 버니어(200)의 눈금(201) 상단부(201a)의 간격은 센타점(103)(203)에서 우측으로 갈수록 0.1μm씩 점차적으로 넓어지고, 좌측으로 갈수록 0.1μm씩 점차적으로 중첩되도록 설계되어 있다.The interval between the lower end portion 101a of the scale 101 and the upper end portion 201a of the scale 201 of the current process vernier 200 is 0.1 from the center points 103 and 203 toward the right. It gradually widens by μm, and it is designed to gradually overlap by 0.1μm toward the left side.

즉, 전공정 버니어(100)의 눈금(101) 하단부(101a)와 현공정 버니어(200)의 눈금(201) 상단부(201a)가 일치되는 곳을 읽어서 Y축 방향의 얼라인 정도를 판단할 수 있도록 되어 있다.That is, the alignment degree in the Y-axis direction can be determined by reading a position where the lower end portion 101a of the scale 101 of the pre-process vernier 100 and the upper end 201a of the scale 201 of the current process vernier 200 coincide with each other. It is supposed to be.

상기와 같이 구성되어 있는 본 발명 반도체 웨이퍼 제조용 얼라인 키 형성구조의 작용을 설명하면 다음과 같다.Referring to the operation of the alignment key forming structure for manufacturing a semiconductor wafer of the present invention configured as described above is as follows.

먼저, 웨이퍼 척의 상면에 웨이퍼를 얹어 놓고, 마스크를 장착한 다음, 웨이퍼에 형성되어 있는 전공정 버니어(100)에 마스크에 형성되어 있는 현공정 버니어(200)을 얼라인한다.First, the wafer is placed on the upper surface of the wafer chuck, the mask is mounted, and the current process vernier 200 formed on the mask is aligned with the preprocess vernier 100 formed on the wafer.

즉, X축방향의 오버레이 값은 전공정 버니어(100)의 눈금(101)과 현공정 버니어(200)의 눈금(201)이 일치하는 곳을 읽고, Y축방향의 오버레이 값은 전공정 버니어(11)의 눈금(101) 하단부(101a)와 현공정 버니어(200)의 상단부(201a)가 일치하는 곳을 읽어서, 규정치내에 들어오도록 얼라인 한다.That is, the overlay value in the X-axis direction reads where the scale 101 of the front process vernier 100 and the scale 201 of the current process vernier 200 coincide, and the overlay value in the Y axis direction is the front process vernier ( 11, the lower end portion 101a of the scale 101 and the upper end portion 201a of the current process vernier 200 are read and aligned so as to enter the prescribed value.

도 4와 같은 상태는 전공정 버니어(100)의 센타점(103)에 위치한 눈금(101)과 현공정 버니어(200)의 센타점(203)에 위치한 눈금(201)이 X축 방향으로 일치되고, 그 센타점(103)(203)에 위치한 전공정 버니어(11)의 눈금(101) 하단부(101a)와 현공정 버니어(200)의 상단부(201a)가 일치되므로 오버레이 값은 X:0, Y:0이다As shown in FIG. 4, the scale 101 located at the center point 103 of the previous process vernier 100 and the scale 201 located at the center point 203 of the current process vernier 200 coincide in the X-axis direction. Since the lower end portion 101a of the graduation 101 of the previous process vernier 11 positioned at the center points 103 and 203 coincides with the upper end 201a of the current process vernier 200, the overlay value is X: 0, Y. Is 0

이상에서 상세히 설명한 바와 같이 본 발명 반도체 웨이퍼 제조용 얼라인 키 형성구조는 웨이퍼에 형성하는 전공정 버니어를 가로방향으로 형성하고, 마스크에 형성하는 현공정 버니어를 X,Y오버레이 값을 확인할 수 있도록 상기 전공정 버니어의 하측에 형성하여, 종래와 같이 웨이퍼와 마스크에 각각 X,Y축 버니어를 형성하는 경우보다 공간을 적게 차지하게 되어 공간이용효율을 향상시키게 되고, 따라서 디바이스의 고집적화 설계가 가능해지는 효과가 있다.As described in detail above, the alignment key forming structure for manufacturing a semiconductor wafer of the present invention forms a preprocessing vernier to be formed on the wafer in a horizontal direction, and the current process vernier to be formed on a mask to check the X and Y overlay values. Formed on the lower side of the process vernier, it takes up less space than in the case of forming the X and Y axis vernier on the wafer and the mask as in the prior art, thereby improving the space utilization efficiency, thus enabling the high integration design of the device. have.

Claims (2)

웨이퍼에 형성되는 전공정 버니어를 가로방향으로 형성하고, 마스크에 형성되며 전공정 버니어 눈금간격 보다 일정간격 넓게 눈금간격이 형성된 현공정 버니어를 상기 전공정 버니어에 얼라인 할 수 있도록 대향되는 위치에 형성하며, 상기 전공정 버니어의 눈금 하단부와 현공정 버니어의 눈금 상단부의 간격은 센타점에서 우측으로 갈수록 일정비율로 점차적으로 넓어지고, 좌측으로 갈수록 일정비율로 점차적으로 중첩되도록 하여, 1쌍의 버니어를 이용하여 XY방향의 얼라인을 측정하도록 한 것을 특징으로 하는 반도체 웨이퍼 제조용 얼라인 키 형성구조.The front process vernier formed on the wafer is formed in the horizontal direction, and the current process vernier formed on the mask and formed with a predetermined interval wider than the previous process vernier scale interval is formed at a position opposite to the previous process vernier. The interval between the lower end of the scale of the front vernier and the upper end of the current vernier gradually widens at a constant ratio from the center point to the right, and gradually overlaps at a constant ratio toward the left. An alignment key forming structure for manufacturing a semiconductor wafer, wherein the alignment in the XY direction is measured by using the same. 제 1항에 있어서, 상기 전공정 버니어의 눈금과 현공정 버니어의 눈금 후단부에는 각각 연결부가 형성되어 있고, 그 연결부의 중앙에는 각각 센타점이 형성되어 있으며, 상기 연결부의 양단부에는 +,-표시가 되어 있는 것을 특징으로 하는 반도체 웨이퍼 제조용 얼라인 키 형성구조.According to claim 1, wherein the front end vernier and the current step vernier of the rear end of the graduation is formed, respectively, the center of the connection is formed with a center point, respectively, the ends of the connection is +,- An alignment key forming structure for manufacturing a semiconductor wafer, wherein the alignment key is formed.
KR1019970046070A 1997-09-06 1997-09-06 Align key manufacturing wafer of semiconductor KR100271631B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140149A (en) * 2015-08-04 2015-12-09 中国电子科技集团公司第十三研究所 Method for measuring vertical alignment error of wafer at high accuracy
CN105140150A (en) * 2015-08-04 2015-12-09 中国电子科技集团公司第十三研究所 Method for transverse alignment error of high-precision measurement chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235484A (en) * 1994-02-24 1995-09-05 Nec Corp Semiconductor device and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235484A (en) * 1994-02-24 1995-09-05 Nec Corp Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140149A (en) * 2015-08-04 2015-12-09 中国电子科技集团公司第十三研究所 Method for measuring vertical alignment error of wafer at high accuracy
CN105140150A (en) * 2015-08-04 2015-12-09 中国电子科技集团公司第十三研究所 Method for transverse alignment error of high-precision measurement chip

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