JPS60136326A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the highly accurate size measurement to be made easily and with high precision only with a microscope, by forming minute reference patterns in a row and further forming a second row of reference patterns with the deviation of a desired amplitude in a different process from that of a pattern to be measured. CONSTITUTION:Reference pattern rows 1 and 2 consisting of reference patterns 1a-1u and 2a-2u each consisting of a minute block are formed such that the patterns are deviated in one direction by a minimum amplitude delta depending on the producing accuracy, for example by 0.1mum. If a pattern to be measured 3 has the left edge coincident with the left edge of the reference pattern 1k in the reference pattern row 1 and the right edge coincident with the reference pattern 2k, for example, the pattern to be measured 3 is determined to have a width of a patch (d), that is 3mum. If the right edge of the pattern 3 is coincident with the reference pattern 2n, however, the width is determined to be 3.3mum.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor technology and also to technology that is effective when applied to dimension measurement on semiconductor chips, for example, technology that is effective when applied to dimension measurement of fine patterns in semiconductor integrated circuit devices. Regarding technology.

[Background Art] Conventionally, the dimensions of fine patterns such as the gate width of MOSFET on a semiconductor chip on which a semiconductor integrated circuit is formed have been measured using a special-purpose microscope constructed by combining a metallurgical microscope, an industrial TV left camera, a monitor device, etc. This was done using a measuring device. As such a measuring device, there is, for example, Hitachi Electronics Department's "Telecon" (registered trademark).

In this measuring device, a fine pattern to be measured on a wafer is first found at an appropriate low magnification, and then the objective lens is changed to a high magnification and displayed on a monitor device.

Thereafter, as shown in FIG. 1, the cursors B1 and B2 displayed on the monitor screen A are moved to match the edges eI and e2 of the pattern P to be measured. Then, the distance between the cursors B1 and B2 is automatically displayed as a measurement dimension on a display window provided in the device.

However, in the above measuring device, optical magnification using a metallurgical microscope and electrical magnification using a TV camera and monitor device are performed simultaneously. Therefore, since the magnification may fluctuate due to fluctuations in the electrical system, it is necessary to periodically correct the magnification of the electrical system. Furthermore, since each lens of a microscope has different characteristics, when changing the magnification by changing the objective lens, there is an inconvenience that it is necessary to calibrate the measured value using a calibration cloth prepared in advance for each objective lens.

[Objective of the Invention] The object of the invention is to easily measure the dimensions of fine patterns on wafers on which semiconductor integrated circuits are formed using only a microscope without using highly accurate and expensive measuring equipment. It is an object of the present invention to provide a dimension measurement technique for a semiconductor device that enables highly accurate measurement without requiring work such as correction of magnification or calibration of ill'l constant values.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, this invention forms a block-shaped minute reference pattern in a row by shifting the minimum dimension determined by the mask creation accuracy in a process different from that of the pattern to be measured, and this reference pattern row is different from the pattern to be measured. A second pattern made of the same reference pattern shifted by the desired dimension.
By providing a scale pattern configured by forming a reference pattern row, and forming a pattern to be measured so as to overlap with the scale pattern, one edge of the pattern to be measured matches the standard belonging to the first reference pattern row. The dimensions of the pattern to be measured can be easily determined by simply counting the number of blocks between the pattern and the reference pattern belonging to the second reference pattern row with which the other edge of the pattern to be measured coincides with the other edge of the pattern to be measured. This achieves the above-mentioned object of making it possible to easily perform highly accurate dimensional measurements with just one tool.

The present invention will be described in detail below along with implementation and examples.

[Embodiment] FIG. 2 shows an embodiment in which the present invention is applied to a semiconductor integrated circuit device.

In the figure, l and 2 are reference pattern rows consisting of reference patterns 1a-1u and 2a-2u, each formed in a microblock shape in a process different from that of the micropattern to be measured, and each reference pattern 1a=1u. are formed in a row, shifted by a minimum dimension δ determined by the precision of creating a mask for forming this reference pattern. In other words, when the mask creation accuracy is 1 μrn and the reference pattern is formed by performing 1/10 reduction projection using this mask, the reference pattern 1a is shifted by 0.1 μm in one direction. ~1u is formed. Similarly for the reference pattern row 2, each of the reference patterns 28 to 2u
are formed shifted by 0.1 μrn in the same direction as the reference patterns 1a to 1U.

Further, the reference pattern rows 1 and 2 are formed so as to be shifted from each other by a predetermined dimension 1 of the fine pattern to be measured. For example, when it is desired to measure a fine pattern processed to a width of 3 μm, the reference pattern row 1 and the reference pattern row 2 are formed with a difference of 3 μrn.

Note that, although not particularly limited, the above reference pattern rows 1 and 2
In order to minimize the area occupied by the scale pattern consisting of the reference patterns 1a to 1u and 2a to
The width and pitch in the pitch direction (vertical direction in the drawing) of 2u are, for example, the minimum processing dimension of the process (1.5 to 2 μ■ r
i) is formed. In addition, each reference pattern 1a~
Although the horizontal widths of 1u and 2a to 2u are not particularly limited, they are formed to be smaller than the pitch between the reference pattern rows I and 2, and slightly larger than the above-mentioned vertical width.

Then, the edge of the fine pattern 3 to be measured is placed on the scale pattern consisting of the reference pattern rows 1 and 2.
It is formed so as to coincide with one side of the reference pattern 1 at the center of the scale pattern.

For example, when it is desired to measure the width of a polysilicon gate in an MO3 integrated circuit, as shown in FIG. and 2a-2u
is formed. Then, a pattern to be measured 3 made of a polysilicon layer designed to have the same dimensions as the polysilicon gate is formed over the reference patterns la to lu and 2a to 2u made of the LOGO3.

Furthermore, in this embodiment, although not particularly limited, LOG
An alignment margin of ±0.5 μm is provided for the misalignment between the mask forming the scale pattern made of O3 and the mask forming the pattern to be measured 3, and ±0.5 μm is provided for the variation due to the process of the pattern to be measured 3. In order to be able to measure up to a range of ±1.0 μm, each reference pattern row has a total of 21 reference patterns, 10 on each side around reference pattern lk (and 2k), covering a total range of ±1.0 μm. 1 and 2.

Next, a method for measuring the dimensions of the pattern to be measured 3 in the above embodiment will be explained.

As described above, the pattern to be measured 3 formed on the scale pattern has no positional deviation, and for example, as shown in FIG. 2, the left edge of the pattern to be measured 3 and the reference pattern lk belonging to the reference pattern row l When the left edge matches the left edge, the left edge of the pattern to be measured 3 corresponds to the reference pattern row 2.
Assume that the left end of the reference pattern 2n, which is three frames away from the reference pattern 2k belonging to .

In the above case, if the right edge of the pattern to be measured 3 matches the reference pattern 2k, the width l of the pattern to be measured 3
is the pitch d between the pre-formed reference pattern rows 1 and 2.
That is, it can be seen that in this case it is 3 μm. On the other hand, when the right edge of the pattern to be measured 3 matches the reference pattern 211 as described above, the reference pattern 2
The deviation between 1 and 20 is 0.3 .mu.m, which is obtained by multiplying the number of blocks 3 between them by 0.1 .mu.m of the deviation between one block.

Moreover, in this case, the lower part of the reference pattern 2, that is, the base 11I! Since it matches the reference pattern 2n in the direction away from the left end of pattern 1, it can be seen that the dimensional error of pattern 3 to be measured is 0.3 μm in the positive direction. Therefore, the width of the pattern to be measured 3 is 3.3 μm.

On the other hand, when the left edge of the pattern to be measured 3 coincides with the left edge of the reference pattern 1, the right edge of the pattern to be measured 3 coincides with the reference pattern 2g, which is 4 blocks above the reference pattern 2, for example. If they match, the error in the width of pattern 3 to be measured is 0.4μ in the negative direction.
m, so it is immediately clear that the width of the pattern to be measured 3 is 2.6 μm.

In the above case, the left edge of the pattern to be measured 3 coincides with the left edge of the reference pattern lk, but
Jll, even if it matches a pattern other than city pattern 1, similarly, the difference between the reference pattern with which the left edge of measured pattern 3 matches and the reference pattern with which the right edge matches at that time. The size error can be determined by counting the number of blocks and multiplying it by the pitch.

In this way, according to the above embodiment, the measurement dimensions can be determined simply by counting the number of blocks between the reference patterns in which the edges on the left and right sides of the pattern to be measured coincide with each other. Dimension measurements can be performed. Moreover, measurement is not related to magnification as long as it is possible to detect the coincidence between the edge of the pattern to be measured and the edge of the reference pattern, so there is no possibility of variation in magnification due to changes in the objective lens of the microscope or fluctuations in the electrical system of the TV camera and monitor device. Accurate measurements can be made even when

In addition, in semiconductor integrated circuits, the size measurement of the fine pattern described above is often performed during the process, but in this case, the scale pattern described above is formed for each chip, and then the wafer is A sufficient quality check can be carried out by measuring the above-mentioned 5 to 10 appropriate locations using the scale pattern. As a result, PQC (Process Quality Control) can be made more precise and quality can be expected to be improved, and the time required to complete a product can be shortened by simplifying the measurement described above, making it possible to reduce costs.

Furthermore, in the above embodiment, the reference patterns la~1
Even if an error occurs in the dimensions of u and, for example, the reference pattern 1a in FIG. Since they are formed at the same time, the reference patterns 28 to 2u are also all formed in the same size as the reference patterns 18 to 1u. Therefore, as long as the edges of the reference patterns 18 to lu and 2a to 2u are measured using the same edge (the left edge in the example) as described above, the relative distance between the reference pattern rows l and 2 is (misalignment)
are the same, and there is no risk of measurement error.

Moreover, in the above embodiment, the reference pattern lk.

2k as a reference, 10 reference patterns are formed on the top and bottom at a pitch of 0.1 μm, so if the pattern to be measured 3 is within ±0.5 μm based on the left edge of the reference patterns lk and 2, Even if misalignment occurs within the range, the dimensional error can be measured with an accuracy of 0.1 μm within an error range of ±0.5.

However, the number of reference pattern rows is <2 as in the above embodiment.
The number is not limited to one, and any number can be set between the pitch of each pattern and the measurement error range.

Also, the pitch of the reference pattern is 0.1μ as in the example.
The pitch is not limited to m, and can be set to a pitch according to the processing accuracy that can be realized on the semiconductor substrate, depending on the mask creation accuracy and the like.

Further, in the above embodiment, the case where the width of a polysilicon gate is measured has been described, but the present invention can also be applied to measurement of other fine patterns such as the width of an aluminum wiring.

In that case, the deviation between the reference pattern rows ① and 2 may be set to the desired wiring width of the aluminum wiring, instead of being 3μ as in the above embodiment.

In the above case, if the dimension l of the fine pattern to be measured is smaller than the minimum distance between the reference pattern rows l and 2 due to the processing accuracy of the reference pattern, as shown in FIG. Reference patterns la~1 belonging to reference pattern sequence l
u and reference patterns 28 to 2u belonging to reference pattern row 2
The reference pattern rows 1 and 2 may be arranged alternately so that the deviation between the reference pattern rows 1 and 2 is narrower than the width of the reference pattern.

Further, in the above embodiment, the scale pattern consisting of the reference pattern is formed of an oxide film of LOGO8.
It may be formed of a field oxide film formed by isoplanar technology or an insulating film or a protective film such as a nitride film other than an oxide film. Alternatively, as shown in Figure 5, in the case where aluminum two-layer wiring technology is applied, PSG film (phosphorus
When forming a through hole (opening for contact between the IW aluminum wiring and the second layer aluminum wiring) in the glabella insulating film 6 such as silicate glass film), a reference pattern is used for the PSG film 6. - Open openings 7, 7 in a pattern corresponding to the row of lines, and use this as a mask to etch the underlying oxide film 5 like LOGO 8, forming block-shaped recesses 8, 8 in one row, respectively. A scale pattern may be constructed using this recess 8 as a reference pattern.

In the above embodiment, the reference pattern rows 1 and 2 are arranged linearly together in one place, but the reference pattern rows are divided at positions as shown by chain lines D-D in FIG. They may be provided in parallel or may be formed at separate locations apart from each other.

Even if they are separated in this way, the relative relationship between the scale pattern and the pattern to be measured, which are formed by the same process, is not related to the position where they are formed, and thus does not affect measurement accuracy in any way. Therefore, the scale pattern can be constructed using any blank area on the semiconductor substrate, and there is no risk of increasing the chip size.

[Effect] In a process different from that of the pattern to be measured, a block-shaped minute reference pattern is formed in a row by shifting the minimum dimension determined by the mask creation accuracy, and this reference pattern row is the same as the desired dimension of the pattern to be measured. Since the scale pattern is previously provided on the semiconductor substrate by forming a second reference pattern row consisting of similar reference patterns shifted by the same amount, even if an error occurs in the dimensions of the reference patterns themselves, the pitch between the two By forming the pattern to be measured so that it overlaps with the pattern that does not deviate, the reference pattern belonging to the first reference pattern row with which one edge of the pattern to be measured coincides with that of the other pattern to be measured. By simply counting the number of blocks between the reference pattern belonging to the second reference pattern row with matched edges, the dimensions of the pattern to be measured can be easily determined. Dimension measurements can be easily performed.

As a result, PQC in the process becomes highly accurate, making it possible to improve quality, and by simplifying measurement, the time required to complete the product is shortened, making it possible to reduce costs.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the scale pattern is formed in a step before the pattern to be measured, but it is also possible to form it in a step after the pattern to be measured. Furthermore, the reference pattern array may not be composed of a plurality of reference patterns, but may be a continuous body having step-shaped edges.

[Field of Application] This invention is applicable not only to MO5 integrated circuits and bipolar integrated circuits, but also to all semiconductor devices that require microfabrication.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an example of a method for measuring dimensions of a fine pattern, FIG. 2 is an explanatory diagram showing an example of a method for measuring dimensions of a fine pattern according to the present invention, and FIG. 3 is an explanatory diagram showing an example of a method for measuring dimensions of a fine pattern. FIG. 4 is an explanatory diagram showing another example of the scale pattern; FIG. 5 is a cross section showing another example of the structure of the reference pattern. It is a diagram. 1.2...Reference pattern row, ■a~lu, 2a~2
u...Reference pattern, 3...Pattern to be measured,
4...Semiconductor substrate, 5...Insulating film (LOGO8
), 6... Insulating film (PSG film) 7... Opening,
8... Concavity.

Claims (1)

[Claims] 1. Among the fine patterns formed on the main surface of the semiconductor substrate, a plurality of fine reference patterns are arranged at equal pitches in a process different from the formation process of the pattern whose dimensions are to be measured. A semiconductor device characterized in that a second reference pattern row is provided at a distance from the reference pattern row approximately equal to the dimension of the pattern to be measured. 2. The semiconductor device according to claim 1, wherein the reference pattern is constituted by an insulating film formed on a semiconductor substrate. 3. The semiconductor device according to claim 1, wherein the reference pattern is constituted by an opening or a recess formed in an insulating film formed on a semiconductor substrate.