CN101577291B - High-voltage semiconductor element device - Google Patents
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- CN101577291B CN101577291B CN2008100958617A CN200810095861A CN101577291B CN 101577291 B CN101577291 B CN 101577291B CN 2008100958617 A CN2008100958617 A CN 2008100958617A CN 200810095861 A CN200810095861 A CN 200810095861A CN 101577291 B CN101577291 B CN 101577291B
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Abstract
The invention provides a high-voltage semiconductor element device which comprises a first type doped semiconductor substrate and a second type doped epitaxial semiconductor arranged on the first typedoped semiconductor substrate, wherein a first type doped region is arranged in the second type doped epitaxial semiconductor; a thick doped drain electrode region is formed in the second type dopedepitaxial semiconductor, and an isolation region and a channel region are arranged between the thick doped drain electrode region and the first type doped region; a second type deep-thick doped regionextends to the first type doped semiconductor substrate from the thick doped drain electrode region; a pair of specially-shaped thick doped source electrode regions is arranged in the first type doped region, and a grid is arranged on the channel region; a grid dielectric layer is arranged between the grid and the channel region; and the high-voltage semiconductor element device is isolated fromother elements by the first type deep-thick doped region. The device has the advantages of vertical and horizontal double-diffused transistors, promotes the breakdown voltage by adopting a two-dimensional and three-dimensional reduce surface field structure, enhances the voltage endurance capacity of the transistors and achieves better surface field effect.
Description
Technical field
The invention relates to a kind of semiconductor device, particularly relevant for being particularly to a kind of PIN diode device and manufacture method thereof.
Background technology
The high-voltage semiconductor element technology is applicable to high voltage and high-power integrated circuit fields.Tradition high-voltage semiconductor element is mainly used in and is higher than or the element application field of 18V on the whole.The advantage of high voltage device technology has been widely used in fields such as display drive IC element, power supply unit, electrical management, communication, auto electronic or Industry Control for meeting cost benefit and easily being compatible to other technologies.
The tradition high-power components has rectilinear (VDMOSFET) and horizontal (LDMOSFET) basically, and wherein transversary is representative with the double-diffused metal oxide semiconductor field-effect transistor, and vertical structure is representative with the channel grid power transistor.
6,194, No. 761 N-type raceway groove vertical proliferation metal oxide semiconductor transistors that disclose of United States Patent (USP) US.In the rectilinear double-diffused metal oxide semiconductor field-effect transistor of tradition (VDMOSFET) element, its junction field effect transistor (junction field effect transistor is called for short JFET) effect of utilizing the exhaustion region border of two P-type body doped regions and epitaxial loayer to be produced toward middle pinching is controlled the vertical conducting size of current.
Fig. 1 is the generalized section that shows tradition plan vertical proliferation metal-oxide semiconductor (MOS) (pseudo-VDMOS) transistor unit.In Fig. 1, high pressure pseudo-VDMOS transistor unit 10 comprises that a P-type doped semiconductor substrate 11, one N-type doped epitaxial semiconductor 13 are formed in this P-type doped semiconductor substrate 11.The dense doping of one N-type disposal area 23 is arranged at 13 of P-type doped semiconductor substrate 11 and N-type doped epitaxial semiconductor.Two P-type body doped regions 31,37 are formed at respectively in the N-type doped epitaxial semiconductor 13, and it is at interval with a channel region.One dense doped drain region 21 is formed in this N-type doped epitaxial semiconductor 13, and and P-type body doped region 37 between every with an isolated area 15.The dense doped region 25 of one N-moldeed depth extends to the dense doping of N-type disposal area 23 from this dense doped drain region 21.In P-type body doped region 31,37, form the dense doping source region 33A of a pair of abnormal shape, 33B respectively, and a grid 39 is arranged on this channel region, it is at interval with a gate dielectric.This high-voltage semiconductor element device is to isolate other elements with dense doped region 17 of a pair of P-type and the dense doped region 19 of a pair of P-moldeed depth.When element operation, dense doped drain region 21 connects drain voltage VDD, and dense doping source region 33A, 33B are connected source voltage VSS with grid 39, and current path is represented with bold dashed lines.The advantage of this pseudo-VMOS transistor power component 10 is easily compatible with other cmos elements, yet by the element area that the dense doped region 19 of P-moldeed depth is isolated, occupies too much area, makes it be difficult for integrating with other semiconductor elements.
6,531, No. 355 horizontal proliferation metal oxide semiconductor transistor (LDMOS) elements that disclose of United States Patent (USP) US.The basic principle of operation of tradition LDMOSFET is identical with other any MOSFET, all is to utilize grid voltage Come to produce the electric current of raceway groove control flows between source electrode and drain electrode.
Fig. 2 is the generalized section that shows traditional horizontal diffused metal oxide emiconductor (LDMOS) transistor unit.In Fig. 2, high-pressure horizontal diffused metal oxide emiconductor (LDMOS) transistor unit 50 comprises that a P-type doped semiconductor substrate 51, one N-type doped epitaxial semiconductor 53 are formed in this P-type doped semiconductor substrate 51.One P-type body doped region 67 is formed in the N-type doped epitaxial semiconductor 53.The dense doped region 65 of one N-moldeed depth is formed in the N-type doped epitaxial semiconductor 53.One dense doped drain region 61 is formed in the dense doped region 65 of this N-moldeed depth, and and P-type body doped region 67 between every with an isolated area 55 and a channel region.The dense doping source region 63A of a pair of abnormal shape, 63B form in the P-type body doped region 67, and a grid 69 is arranged on this channel region, and it is at interval with a gate dielectric.This high-voltage semiconductor element device is to isolate other elements with dense doped region 57 of a pair of P-type and the dense doped region 59 of a pair of P-moldeed depth.When element operation, dense doped drain region 61 connects drain voltage VDD, and dense doping source region 63A, 63B connect source voltage VSS, and grid 69 connection grid voltage VG, and current path is represented with bold dashed lines.The advantage of this LDVMOS transistor power component 50 is to make easily and easy and existing cmos semiconductor technology is integrated.Yet it is to increase near the drift region length of drain electrode that LDMOSFET increases withstand voltage mode, has therefore wasted many areas.Moreover the surface field of double-diffused transistor (SurfaceField) has also limited transistorized voltage endurance capability.
In view of this, industry is badly in need of a kind of high-voltage semi-conductor power component, takes into account the high pressure resistant property of VDMOS and ldmos transistor element and reduces class interval of element significantly.
Summary of the invention
In view of this, for the shortcoming that overcomes above-mentioned prior art and reach and have the advantage that the element microization is brought concurrently.The embodiment of the invention provides a high pressure (high power) semiconductor device, keeps transistorized voltage endurance capability and reduces element spacing, to enlarge process window to promote the technology yields.
The same attitude of the present invention is to provide a kind of high-voltage semiconductor element device, comprising: one first type doped semiconductor substrate; One second type doped epitaxial semiconductor is in this first type doped semiconductor substrate; One first type body doped region is in this second type doped epitaxial semiconductor; One dense doped drain region in this second type doped epitaxial semiconductor, and with this first type body doped region at interval with an isolated area and a channel region; The dense doped region of one second moldeed depth extends to this first type doped semiconductor substrate from this dense doped drain region; The dense doping source region of a pair of abnormal shape is arranged in this first type body doped region; And one grid be arranged on this channel region, it is at interval with a gate dielectric; Wherein this high-voltage semiconductor element device system isolates other elements with the dense doped region of one first type.
Another sample attitude of the present invention is to provide a kind of high-voltage semiconductor element device, comprising: a P-type doped semiconductor substrate; One N-type doped epitaxial semiconductor is in this P-type doped semiconductor substrate; The dense doping of one N-type disposal area is arranged between this P-type doped semiconductor substrate and this N-type doped epitaxial semiconductor; One P-type body doped region is in this N-type doped epitaxial semiconductor; One dense doped drain region in this N-type doped epitaxial semiconductor, and with this P-type body doped region at interval with an isolated area and a channel region; The dense doped region of one N-moldeed depth extends to this P-type doped semiconductor substrate from this dense doped drain region; The dense doping source region of a pair of abnormal shape is arranged in this P-type body doped region; And one grid be arranged on this channel region, it is at interval with a gate dielectric; Wherein this high-voltage semiconductor element device system isolates other elements with the dense doped region of a pair of P-type.
This high-voltage semiconductor element device has the advantage of vertical and horizontal double-diffused transistor concurrently, has used two and three dimensions Reduce Surface Field principle to promote breakdown voltage, has promoted the transistor voltage endurance capability.And, reach better surface field result by two and three dimensions Reduce Surface Field structure.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 is the generalized section that shows tradition plan vertical proliferation metal-oxide semiconductor (MOS) (pseudo-VDMOS) transistor unit;
Fig. 2 is the generalized section that shows traditional horizontal diffused metal oxide emiconductor (LDMOS) transistor unit;
Fig. 3 is the generalized section according to the LDMOS-FET device of one embodiment of the invention;
Fig. 4 is the generalized section of LDMOS-FET device according to another embodiment of the present invention;
Fig. 5 A is the top view that shows the LDMOSFET element of prior art; And
Fig. 5 B and Fig. 5 C show the top view of the LDMOSFET element of the embodiment of the invention.
Drawing reference numeral:
Known portions (Fig. 1～Fig. 2)
10～high pressure pseudo-VDMOS transistor unit;
The substrate of 11～P-type doped semiconductor;
13～N-type doped epitaxial semiconductor;
15～isolated area;
The dense doped region of 17～P-type;
The dense doped region of 19～P-moldeed depth;
21～dense doped drain region;
The dense doping of 23～N-type disposal area;
The dense doped region of 25～N-moldeed depth;
31,37～P-type body doped region;
33A, 33B～dense doping source region of a pair of abnormal shape;
39～grid;
50～high-pressure horizontal diffused metal oxide emiconductor (LDMOS) transistor unit;
The substrate of 51～P-type doped semiconductor;
53～N-type doped epitaxial semiconductor;
55～isolated area;
The dense doped region of 57～P-type;
The dense doped region of 59～P-moldeed depth;
61～dense doped drain region;
The dense doped region of 65～N-moldeed depth;
67～P-type body doped region;
63A, 63B～dense doping source region of a pair of abnormal shape;
69～grid;
VDD～drain voltage;
VSS～source voltage;
VG～grid voltage.
The present invention's part (Fig. 3～Fig. 4 C)
100～high-voltage LDMOS-FET device;
110～the first type doped semiconductor substrates;
115～the second first type doped regions of floating;
120～the second type doped epitaxial semiconductor layers;
125～isolated area;
The dense doped region of 131～the first types;
The dense doped region of 135～the first moldeed depth;
137～dense doped drain region;
The dense doped region of 139～the second moldeed depth;
141～the first first type doped regions of floating;
143A, 143B～dense doping source region of a pair of abnormal shape;
145～the first type body doped regions;
149～grid;
200～high-voltage LDMOS-FET device;
The substrate of 210～P-type doped semiconductor;
The dense doping of 214～N-type disposal area;
220～N-type doped epitaxial semiconductor;
225～isolated area;
The dense doped region of 231～P-type;
The dense doped region of 235～P-moldeed depth;
237～dense doped drain region;
The dense doped region of 239～N-moldeed depth;
243A, 243B～dense doping source region of a pair of abnormal shape;
245～P-type body doped region;
249～grid;
VDD～drain voltage;
VSS～source voltage;
VG～grid voltage;
300～known LDMOSFET element;
The dense doped region of 310～P-type;
320～drain electrode;
330A, 330B～source electrode;
P～class interval;
400A, 400B～LDMOSFET element;
410A, 410B～dense doped region of P-type;
420～dense doped drain region;
430A and 430B～dense doped source.
Embodiment
Below describe and be accompanied by the example of graphic explanation in detail with each embodiment, as reference frame of the present invention.In graphic or specification were described, similar or identical part was all used identical figure number.And in graphic, the shape of embodiment or thickness can enlarge, and to simplify or convenient the sign.Moreover, graphic in the part of each element will it should be noted that to describe explanation respectively, the element that does not illustrate among the figure or describe, form known to those skilled in the art, in addition, only for disclosing the ad hoc fashion that the present invention uses, it is not in order to limit the present invention to certain embodiments.
The embodiment of the invention provides a kind of component of metal oxide semiconductor transistor in high voltage, have the advantage of vertical and horizontal double-diffused transistor concurrently, and used two and three dimensions Reduce Surface Field (being called for short RESURF) principle to promote breakdown voltage (breakdown voltage), promote the transistor voltage endurance capability.And by two and three dimensions RESURF structure, to reach better surface field result.
Fig. 3 is the generalized section according to the LDMOS-FET device of one embodiment of the invention.See also Fig. 3, one high-voltage LDMOS-FET device 100 comprises one first type doped semiconductor substrate 110, and silicon (SOI) substrate is for example arranged on bulk substrate of P-type monocrystalline silicon or the insulating barrier.One second type doped epitaxial semiconductor layer (for example N-type silicon epitaxy layer) 120 is formed in this first type doped semiconductor substrate 110.One first type body doped region 145 is in the second type doped epitaxial semiconductor 120.One dense doped drain region 137 is formed in this second type doped epitaxial semiconductor 120, and and the first type body doped region 145 between every with an isolated area 125 and a channel region.The dense doped region 139 of one second moldeed depth extends to this first type doped semiconductor substrate 110 from this dense doped drain region 137.Owing to form the dense doped region 139 of second moldeed depth between the dense doped drain region 137 and the first type doped semiconductor substrate 110, make this LDMOS FET element can bear higher voltage.The dense doping source region of a pair of abnormal shape (for example dense doped region 143A of N-type and the dense doped region 143B of P-type) is arranged in this first type body doped region 145.One grid 149 is arranged on this channel region, and it is at interval with a gate dielectric.It is to isolate other elements with dense doped region 131 of first type and the dense doped region 135 of first moldeed depth that this LDMOS FET element is put, and the dense doped region 135 of above-mentioned first moldeed depth extends to this first type doped semiconductor substrate from the dense doped region 131 of this first type.
According to the embodiment of the invention, above-mentioned high-voltage LDMOS-FET device 100 also comprises the one first first type doped region (floating first type doped region) 141 of floating, be arranged at isolated area 125 belows, and between channel region and dense doped drain region 137.This first floats the first type doped region 141 in order to the surperficial transverse current of resistance barrier, and reduces surface field with two-dimentional pattern, that is reaches the result of better reduction surface field by two-dimensional directional RESURF structure.
Moreover high-voltage LDMOS-FET device 100 can comprise also that the one second first type doped region 115 of floating is arranged in this first type doped semiconductor substrate 110, relatively the below of this dense doped drain region 137.This second first type doped region 115 of floating reduces surface field in order to three-dimensional pattern, that is reaches the result of better reduction surface field by three-dimensional RESURF structure.
When element operation, dense doped drain region 137 connects drain voltage VDD, and dense doping source region 143A, 143B connect source voltage VSS, and grid 149 connection source voltage VG, and current path is represented with bold dashed lines.It should be noted that the voltage VG that imposes on this grid is identical with the voltage that imposes on this drain electrode VDD.Perhaps, optionally, the voltage VG that imposes on this grid is different with the voltage VDD that imposes on this drain electrode.
Fig. 4 is the generalized section of LDMOS-FET device according to another embodiment of the present invention.See also Fig. 4, one high-voltage LDMOS-FET device 200 comprises that a P-type doped semiconductor substrate 210, one N-type doped epitaxial semiconductor 220 are in P-type doped semiconductor substrate 210.The dense doping of one N-type disposal area 214 is arranged between P-type doped semiconductor substrate 210 and the N-type doped epitaxial semiconductor 220.By being set, the dense doping of N-type disposal area 214 can make element ON state drain source electrode resistance (Rsdon) and breakdown voltage (breakdown voltage) reach optimization.
One P-type body doped region 245 is in N-type doped epitaxial semiconductor 220.One dense doped drain region 237 in N-type doped epitaxial semiconductor 220, and with P-type body doped region 245 at interval with an isolated area 225 and a channel region.The dense doped region 239 of one N-moldeed depth extends to the dense doping of this N-type disposal area 214 from this dense doped drain region 237.The dense doping source region of a pair of abnormal shape (for example dense doped region 243A of N-type and the dense doped region 243B of P-type) is arranged in this first type body doped region 245.One grid 249 is arranged on this channel region, and it is at interval with a gate dielectric.This LDMOS FET element is put with dense doped region 231 of first type and the dense doped region 235 of first moldeed depth and is isolated other elements, and the dense doped region 235 of above-mentioned first moldeed depth extends to this first type doped semiconductor substrate 210 from the dense doped region 231 of this first type.
According to the embodiment of the invention, the first type doped region of also optionally will floating is arranged at isolated area 225 belows, or be arranged in the first type doped semiconductor substrate 210, reach the result of better reduction surface field by two dimension (or three-dimensional) the RESURF structure of direction.
Fig. 5 A is the top view that shows the LDMOSFET element of prior art, shows the top view of the LDMOSFET element of the embodiment of the invention compared to Fig. 5 B and Fig. 5 C.See also Fig. 5 A, at the application of high voltage (100V), the scope of known LDMOSFET element 300 is by dense doped region 310 definition of P-type, and the class interval P that is made of drain electrode 320 and source electrode 330A, 330B is at least 40 microns (μ m).See also Fig. 5 B, according to one embodiment of the invention, the scope of LDMOSFET element 400A is by the dense doped region 410A definition of P-type, dense doped source 430A of P-type and 430B be annular region respectively around dense doped drain region 420, can be reduced to effectively less than 40 microns (μ m) by drain electrode 420 and the class interval P that constitutes of source electrode 430A, 430B.See also Fig. 5 C, according to another embodiment of the present invention, the scope of LDMOSFET element 400B is by the dense doped region 410B definition of P-type, the length of dense doped source 430A of P-type and 430B is identical with the length of dense doped drain region 420, and the class interval P that is made of drain electrode 420 and source electrode 430A, 430B can be reduced to effectively less than 40 microns (μ m).
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting scope of the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with defining of claim scope.
Claims (9)
1. a high-voltage semiconductor element device is characterized in that, described high-voltage semiconductor element device comprises:
One first type doped semiconductor substrate;
One second type doped epitaxial semiconductor is in the described first type doped semiconductor substrate;
One first type body doped region is in the described second type doped epitaxial semiconductor;
One dense doped drain region in the described second type doped epitaxial semiconductor, and with the described first type body doped region at interval with an isolated area and a channel region;
The one second first type doped region of floating is arranged in the described first type doped semiconductor substrate below of described relatively dense doped drain region;
The dense doped region of one second moldeed depth extends to the described first type doped semiconductor substrate from described dense doped drain region;
The dense doping source region of a pair of abnormal shape is arranged in the described first type body doped region; And
One grid is arranged on the described channel region, and it is at interval with a gate dielectric;
Wherein said high-voltage semiconductor element device is to isolate other elements with the dense doped region of one first type.
2. high-voltage semiconductor element device as claimed in claim 1 is characterized in that, described high-voltage semiconductor element device comprises that also the dense doping of one second type disposal area is arranged between described first type doped semiconductor substrate and the described second type doped epitaxial semiconductor.
3. high-voltage semiconductor element device as claimed in claim 1 is characterized in that, described high-voltage semiconductor element device comprises that also the one first first type doped region of floating is arranged at described isolated area below, between described channel region and described dense doped drain region.
4. high-voltage semiconductor element device as claimed in claim 3 is characterized in that, described first floats the first type doped region in order to the surperficial transverse current of resistance barrier, and reduces surface field with two-dimentional pattern.
5. high-voltage semiconductor element device as claimed in claim 1 is characterized in that, described second floats the first type doped region in order to three-dimensional pattern reduction surface field.
6. high-voltage semiconductor element device as claimed in claim 1 is characterized in that, the dense doping source region of described a pair of abnormal shape comprises dense doped source of one first type and the dense doped source of one second type.
7. high-voltage semiconductor element device as claimed in claim 6 is characterized in that, described high-voltage semiconductor element device comprises that also the dense doped region of one first moldeed depth extends to the described first type doped semiconductor substrate from the dense doped region of described first type.
8. high-voltage semiconductor element device as claimed in claim 6 is characterized in that, the length of the dense doped source of described first type is identical with the length of described dense doped drain region.
9. high-voltage semiconductor element device as claimed in claim 6 is characterized in that, the dense doped source of described first type is that an annular region is around described dense doped drain region.
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| CN2008100958617A CN101577291B (en) | 2008-05-06 | 2008-05-06 | High-voltage semiconductor element device |
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| CN2008100958617A CN101577291B (en) | 2008-05-06 | 2008-05-06 | High-voltage semiconductor element device |
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| CN101577291B true CN101577291B (en) | 2011-06-01 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102082177A (en) * | 2010-12-08 | 2011-06-01 | 四川长虹电器股份有限公司 | Bulk silicon LDMOS (Laterally Diffused Metal Oxide Semiconductor) device modulated in bulk electric field |
| CN106158921B (en) * | 2015-04-10 | 2019-07-23 | 无锡华润上华科技有限公司 | Has the transverse diffusion metal oxide semiconductor field effect pipe of RESURF structure |
| TWI635611B (en) * | 2017-09-25 | 2018-09-11 | 新唐科技股份有限公司 | High voltage semiconductor device |
| CN111146286B (en) * | 2018-11-05 | 2023-03-14 | 世界先进积体电路股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510275A (en) * | 1993-11-29 | 1996-04-23 | Texas Instruments Incorporated | Method of making a semiconductor device with a composite drift region composed of a substrate and a second semiconductor material |
| US6063674A (en) * | 1998-10-28 | 2000-05-16 | United Microelectronics Corp. | Method for forming high voltage device |
| US6194761B1 (en) * | 1998-02-10 | 2001-02-27 | Stmicroelectronics S.R.L. | VDMOS transistor protected against over-voltages between source and gate |
| US6531355B2 (en) * | 1999-01-25 | 2003-03-11 | Texas Instruments Incorporated | LDMOS device with self-aligned RESURF region and method of fabrication |
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2008
- 2008-05-06 CN CN2008100958617A patent/CN101577291B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510275A (en) * | 1993-11-29 | 1996-04-23 | Texas Instruments Incorporated | Method of making a semiconductor device with a composite drift region composed of a substrate and a second semiconductor material |
| US6194761B1 (en) * | 1998-02-10 | 2001-02-27 | Stmicroelectronics S.R.L. | VDMOS transistor protected against over-voltages between source and gate |
| US6063674A (en) * | 1998-10-28 | 2000-05-16 | United Microelectronics Corp. | Method for forming high voltage device |
| US6531355B2 (en) * | 1999-01-25 | 2003-03-11 | Texas Instruments Incorporated | LDMOS device with self-aligned RESURF region and method of fabrication |
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