US20140048877A1 - Lateral diffusion metal oxide semiconductor transistor structure - Google Patents
Lateral diffusion metal oxide semiconductor transistor structure Download PDFInfo
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- US20140048877A1 US20140048877A1 US13/585,801 US201213585801A US2014048877A1 US 20140048877 A1 US20140048877 A1 US 20140048877A1 US 201213585801 A US201213585801 A US 201213585801A US 2014048877 A1 US2014048877 A1 US 2014048877A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000009792 diffusion process Methods 0.000 title claims abstract description 4
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- 150000004706 metal oxides Chemical class 0.000 title 1
- 230000004888 barrier function Effects 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 17
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 14
- 229910052787 antimony Inorganic materials 0.000 claims description 9
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 9
- 230000003247 decreasing effect Effects 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 111
- 230000015556 catabolic process Effects 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 239000007943 implant Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Definitions
- the present invention relates to a semiconductor device, and more particularly to a lateral diffusion metal-oxide-semiconductor (LDMOS) transistor device.
- LDMOS lateral diffusion metal-oxide-semiconductor
- a LDMOS transistor device is characterized by low on-resistance and high breakdown voltage and is widespread applied in an integral part of modern day display panels, telecommunication systems, motor controllers, switch lock power supplies, inverters, and alike.
- a typical LDMOS transistor device is an asymmetric power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate and coplanar drain/source regions separated by a channel region which are fabricated in an epitaxial layer of a substrate.
- MOSFET metal-oxide-semiconductor field effect transistor
- the drain region is formed in a drift region which is fabricated by a lightly doped drain (LDD) implant process and used to isolate the drain and the channel regions.
- LDD lightly doped drain
- the drain region and the gate are laterally separated by a field oxide (FOX). While the LDMOS transistor device is operated in high voltage, electric field density around the drain region can be reduced due to the existence of the drift region and the FOX, such that the breakdown voltage of the LDMOS transistor device can be improved.
- LDD lightly doped drain
- the present invention provides a LDMOS transistor structure comprising a barrier layer, a semiconductor layer, a source, a first drain and a guard ring.
- the barrier layer with a first polarity is disposed in a substrate.
- the semiconductor layer with a second polarity is disposed on the barrier layer.
- the source has a first polarity region and a second polarity region both disposed in the semiconductor layer.
- the first drain is disposed in the semiconductor layer and has a drift region with the second polarity.
- the guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and surrounding the source and the drain, and is electrically connected to the source.
- the first polarity is n-type conductivity
- the second polarity is p-type conductivity
- the barrier layer comprises a tri-layer phosphorous/antimony/phosphorous (P/Sb/P) doping structure.
- the first polarity region and a second polarity region are disposed in an n-type well which is disposed in the semiconductor layer in a manner of getting in touch with the barrier layer.
- the n-type well comprises an n-body region and a high-voltage drift N-well (HVDNW) region, wherein the first polarity region and a second polarity region are disposed in the n-body region, and the n-body region is disposed in the HVDNW region.
- HVDNW high-voltage drift N-well
- the drift region has a doping concentration substantially greater than that of the semiconductor layer.
- the LDMOS transistor structure further comprises a first gate disposed on the semiconductor layer and partially straddling over a first field oxide (FOX), wherein the first gate and the first drain are separated from each other by the first FOX.
- FOX field oxide
- the LDMOS transistor structure further comprises a second drain disposed in the semiconductor layer and a second gate disposed over the semiconductor layer, wherein the second gate partially straddles over a second FOX by which the second gate and the second drain are separated from each other.
- the first drain and the second drain constitute a symmetric structure against the source, and the source serves as a common source of the first drain and the second drain.
- the second polarity region is separated into two parts by the first polarity region.
- the guard ring has a concentration decreasing gradually from a top surface of the semiconductor layer to the barrier.
- the guard ring is electrically connected to the source via an interconnection or a wire.
- the first polarity is p-type conductivity
- the second polarity is n-type conductivity
- the barrier layer comprises a tri-layer boron/Indium/boron (B/In/B) doping structure.
- a LDMOS transistor structure wherein a guard ring is formed in a semiconductor layer in a manner of getting in touch with a barrier layer disposed in the semiconductor layer and surrounding a source and a drain. Since the guard ring and the barrier have the same polarity and both of them are electrically connected with the source, thus an isolation structure with an electric potential identical to that of the source is formed in a manner of surrounding the LDMOS transistor, so as to prevent the parasitic circuit elements formed in the LDMOS transistor device from latching up with other integrated circuit element, such that the device punch-through problems due to critical dimension shrinkage can be solved. Meanwhile the on-resistance of the LDMOS transistor device can be decreased, the breakdown voltage of the LDMOS transistor device can be increased, and the performance of the LDMOS transistor device can be improved.
- FIG. 1 illustrates a cross-sectional view of a LDMOS transistor structure in accordance with one embodiment of the present invention
- FIG. 2 illustrates a cross-sectional view of a LDMOS transistor structure in accordance with another embodiment of the present invention.
- FIG. 3 illustrates a cross-sectional view of a LDMOS transistor structure in accordance with further embodiment of the present invention.
- a LDMOS transistor structure is provided by the present invention to solve device punch-through problems due to critical dimension shrinkage.
- the present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
- FIG. 1 illustrates a cross-sectional view of a LDMOS transistor structure 100 in accordance with one embodiment of the present invention.
- the LDMOS transistor structure 100 comprises a substrate 101 , a barrier layer 102 , a p-type semiconductor layer 103 , a gate 104 , a source 105 , a drain 106 , a FOX 107 , a guard ring 108 and a gate oxide layer 109 .
- the substrate 101 is a semiconductor substrate preferably is a silicon substrate.
- the barrier layer 102 is an n-type doping layer formed in the substrate 101 .
- the barrier layer 102 extends downward in to the substrate 101 from a surface 101 a of the substrate 101 ; and the barrier layer 102 comprises phosphorous and antimony dopants.
- the barrier layer 102 has a tri-layer P/Sb/P doping structure; the barrier layer 102 includes an antimony doping layer 102 a and two phosphorous doping layers 102 b and 102 c ; wherein the antimony doping layer 102 a has a doping concentration greater than that of the two phosphorous doping layers 102 b and 102 c sandwiching the antimony layer 102 a.
- the barrier layer 102 has a thickness about 3 ⁇ m, and the tri-layer P/Sb/P doping structure is formed by at least three separated doping processes which are performed to implant phosphorous dopants, antimony dopants and phosphorous dopants in sequence into the substrate 101 .
- the tri-layer P/Sb/P doping structure may be formed by steps as follows: A phosphorous doping layer is firstly formed in the substrate 101 , and the antimony doping layer 102 a is then formed in the phosphorous doping layer by implanting antimony dopants into the phosphorous doping layer, so as to divide the phosphorous doping layer into two parts (referred as the two phosphorous doping layers 102 b and 102 c ).
- the p-type semiconductor layer 103 is an epitaxial layer formed on the substrate 101 , wherein the epitaxial layer is disposed over and in contact with the barrier layer 102 .
- the p-type semiconductor layer 103 is doped with p-type dopants, such as boron ions, and has a thickness about 7 ⁇ m.
- the source 105 has a p-type region 105 a and an n-type region 105 b disposed in an n-type well 110 formed in the p-type semiconductor layer 103 in a manner of getting in touch with the barrier layer 102 .
- the n-type well 110 comprises an n-body region (referred as N-Body region) 110 a , a high-voltage drift N-well (referred as HVDNW region) 110 , wherein the N-Body region 110 a is disposed in the HVDNW region 110 b , and the p-type region 105 a and the n-type region 105 b are disposed in the N-Body region 110 a .
- the n-type region 105 b is a high concentration n-type doping region (referred as N+ region 105 b ), and the p-type region 105 a is a high concentration p-type doping region (referred as P+ region 105 a ).
- the N+ region 105 b has a doping concentration substantially greater than that of the N-Body region 110 a
- the N-Body region 110 a has a doping concentration substantially greater than that of the HVDNW region 110 b.
- the drain 106 is formed in the p-type semiconductor layer 103 and has a high concentration p-type doping region (referred as P+ region) 106 a and a p-type drift region (referred as P-Drift region) 106 b .
- P+ region p-type doping region
- P-Drift region p-type drift region
- the P+ region 106 a is disposed in the P-Drift region 106 b and has a doping concentration substantially greater than that of the P-Drift region 106 b .
- the P-Drift region 106 b has a doping concentration substantially greater than that of the p-type semiconductor layer 103 .
- the gate oxide layer 109 is blanket over the source 105 and a portion of the p-type semiconductor layer 103 .
- the FOX 107 is formed in the p-type semiconductor layer 103 and protrudes beyond a top surface 103 a of the p-type semiconductor layer 103 .
- the gate 104 is disposed on the gate oxide layer 109 and partially straddles over the FOX 107 , wherein the gate 104 and the drain 106 are separated from each other by the FOX 107 .
- the guard ring 108 is an n-type doping region extending downward in to the p-type semiconductor layer 103 from the top surface 103 a of the p-type semiconductor layer 103 in a manner of getting in touch with the barrier layer 102 and surrounding the source 105 and the drain 106 .
- the guard ring 108 is electrically connected to the source 105 via a conductive structure 111 , such as an interconnection or a wire.
- the guard ring 108 comprises a high concentration n-type doping region (referred as N+ region) 108 a , an n-type well (referred as N-Well region) 108 b , an n-type drift region (referred as N-Drift region) 108 c and a high-voltage drift N-well (referred as HVDNW region) 108 d.
- N+ region n-type doping region
- N-Well region n-type well
- N-Drift region n-type drift region
- HVDNW region high-voltage drift N-well
- the N+ region 108 a extends downwards in to the N-Well region 108 b from the top surface 103 a of the p-type semiconductor layer 103 ; the N-Well region 108 b is disposed in the N-Drift region 108 c ; and the N-Drift region 108 c is disposed in the HVDNW region 108 d .
- the N+ region 108 a has a doping concentration substantially greater than that of the N-Well region 108 b ; the doping concentration of the N-Well region 108 b is substantially greater than that of the N-Drift region 108 c ; and the doping concentration of the N-Drift region 108 c is substantially greater than that of the HVDNW region 108 d .
- the guard ring 108 has a concentration decreasing gradually from the top surface 103 a of the semiconductor layer 103 to the barrier 102 .
- the guard ring 108 and the barrier layer 102 has identical polarity and both of them are electrically connected to the source 105 , thus an isolation structure with an electric potential identical to that of the source 105 is formed in the p-type semiconductor layer 103 so as to prevent the parasitic circuit elements formed in the p-type semiconductor layer 103 from latching up with other integrated circuit element (not shown). Meanwhile the on-resistance of the LDMOS transistor structure 100 can be decreased, the breakdown voltage of the LDMOS transistor structure 100 can be increased, and the performance of the LDMOS transistor structure 100 can be improved.
- FIG. 2 illustrates a cross-sectional view of a LDMOS transistor structure 200 in accordance with another embodiment of the present invention.
- the physical structure of the LDMOS transistor structure 200 is generally similar to that of the LDMOS transistor structure 100 depicted in FIG. 1 .
- the difference therebetween is that the LDMOS transistor structure 200 further comprises a gate 204 and a drain 206 .
- the same elements may be indicated by the same numbers.
- the drain 106 and 206 constitute a symmetric structure against the source 105 , and the source 205 serves as the common source thereof.
- the source 205 comprises an n-type region 205 b and two p-type regions 205 a and 205 c disposed in the n-type well 110 formed in the p-type semiconductor layer 103 , wherein the two p-type regions 205 a and 205 c are separated by the n-type region 205 b .
- the n-type region 205 b is a high concentration n-type doping region (referred as N+ region 205 b ), and these two p-type region 205 a and 205 c are high concentration p-type doping regions (referred as P+ region 205 a and 205 c ).
- the N+ region 205 b has a doping concentration substantially greater than that of the N-Body region 110 a.
- the drain 206 is formed in the p-type semiconductor layer 103 and has a high concentration p-type doping region (referred as P+ region) 206 a and a p-type drift region (referred as P-Drift region) 206 b .
- the P+ region 206 a is disposed in the P-Drift region 206 b and has a doping concentration substantially greater than that of the P-Drift region 206 b .
- the P-Drift region 206 b has a doping concentration substantially greater than that of the p-type semiconductor layer 103 .
- the gate 204 is disposed on the gate oxide layer 109 and partially straddles over the FOX 107 , wherein the gate 204 and the drain 206 are separated from each other by the FOX 107 .
- an isolation structure with an electric potential identical to that of the source 205 is formed in the p-type semiconductor layer 103 , so as to prevent parasitic circuit elements formed therein from latching up with other integrated circuit element (not shown). Meanwhile the on-resistance of the LDMOS transistor structure 200 can be decreased, the breakdown voltage of the LDMOS transistor structure 200 can be increased, and the performance of the LDMOS transistor structure 200 can be improved.
- p-channel transistors described in the aforementioned embodiments are just illustrative; the applying scope of the present invention may not be limited. Thus the features and advantages of the present invention may be further applied by an n-channel transistor.
- FIG. 3 illustrates a cross-sectional view of a LDMOS transistor structure 300 in accordance with further embodiment of the present invention.
- the physical structure of the LDMOS transistor structure 300 is generally similar to that of the LDMOS transistor structure 200 depicted in FIG. 2 . The difference there between is that the LDMOS transistor structure 300 is an n-channel transistor structure rather than a p-channel transistor structure.
- the LDMOS transistor structure 300 comprises a substrate 301 , a barrier layer 302 , an n-type semiconductor layer 303 , two gates 304 and 314 , a source 305 , two drains 306 and 316 , a FOX 307 , a guard ring 308 and a gate oxide layer 309 .
- the barrier layer 302 is an n-type doping layer formed in the substrate 101 , wherein the barrier layer 302 comprises indium and boron dopants.
- the barrier layer 302 of the present embodiment is illustrated as a single layer structure (see FIG. 3 ), in some other embodiments of the present invention, the barrier layer 302 may otherwise comprise a tri-layer B/In/B doping structure, wherein the indium doping layer (not shown) has a doping concentration greater than that of the two boron doping layers (not shown) sandwiching the indium layer.
- the n-type semiconductor layer 303 is an epitaxial layer formed on the substrate 301 , wherein the epitaxial layer is disposed over and in contact with the barrier 302 .
- the source 305 comprises an p-type region 305 b and two n-type regions 305 a and 305 c disposed in an p-type well 310 formed in the n-type semiconductor layer 303 , wherein the p-type well 310 comprises an p-body region (referred as P-Body region) 310 a , a high-voltage drift p-well (referred as HVDPW region) 310 b .
- P-Body region p-body region
- HVDPW region high-voltage drift p-well
- the P-Body region 310 a is disposed in the HVDPW region 310 b , and the two n-type region 305 a and 305 c and the p-type region 305 b are disposed in the P-Body region 310 a , wherein the two n-type regions 305 a and 305 c are separated by the p-type region 305 b .
- the p-type region 305 b is a high concentration p-type doping region (referred as P+ region 305 b ), these two n-type region 305 a and 305 c are high concentration n-type doping regions (referred as N+ region 305 a and 305 c ); the P+ region 305 b has a doping concentration substantially greater than that of the P-Body region 310 a , and the concentration of the P-Body region 310 a is substantially greater than that of the HVDPW region 310 b.
- the drain 306 is formed in the n-type semiconductor layer 303 and has a high concentration n-type doping region (referred as N+ region) 306 a and an n-type drift region (referred as N-Drift region) 306 b , wherein the N+ region 306 a is disposed in the N-Drift region 306 b and has a doping concentration substantially greater than that of the N-Drift region 306 b .
- the N-Drift region 306 b has a doping concentration substantially greater than that of the n-type semiconductor layer 303 .
- the drain 316 is formed in the n-type semiconductor layer 303 and has a high concentration n-type doping region (referred as N+ region) 316 a and an n-type drift region (referred as N-Drift region) 316 b , wherein the N+ region 316 a is disposed in the N-Drift region 316 b and has a doping concentration substantially greater than that of the N-Drift region 316 b .
- the N-Drift region 316 b has a doping concentration substantially greater than that of the n-type semiconductor layer 303 .
- the gate oxide layer 309 is blanket over the source 305 and a portion of the n-type semiconductor layer 303 .
- the FOX 307 is formed in the n-type semiconductor layer 303 and protrudes beyond a top surface 303 a of the n-type semiconductor layer 303 .
- the gates 304 and 314 are respectively disposed on the gate oxide layer 309 and partially straddle over the FOX 307 by which the gate 304 and the drain 306 are separated from each other and so do the gate 314 and the drain 316 .
- the guard ring 308 is a p-type doping region extending downward in to the n-type semiconductor layer 303 from the top surface 303 a of the n-type semiconductor layer 303 in a manner of getting in touch with the barrier layer 302 and surrounding the source 305 and the drains 306 and 316 .
- the guard ring 308 is electrically connected to the source 305 via a conductive structure 311 , such as an interconnection or a wire.
- the guard ring 308 comprises a high concentration p-type doping region (referred as P+ region) 308 a , a p-type well (referred as P-Well region) 308 b , a p-type drift region (referred as P-Drift region) 308 c and a high-voltage drift p-well (referred as HVDPW region) 308 d.
- P+ region a high concentration p-type doping region
- P-Well region p-type well
- P-Drift region p-type drift region
- HVDPW region high-voltage drift p-well
- the P+ region 308 a extends downwards in to the P-Well region 308 b from the top surface 303 a of the n-type semiconductor layer 303 ; the P-Well region 308 b is disposed in the P-Drift region 308 c ; and the P-Drift region 308 c is disposed in the HVDPW region 308 d .
- the P+ region 308 a has a doping concentration substantially greater than that of the P-Well region 308 b ; the doping concentration of the P-Well region 308 b is substantially greater than that of the P-Drift region 308 c ; and the doping concentration of the P-Drift region 308 c is substantially greater than that of the HVDPW region 308 d.
- the guard ring 308 and the barrier layer 302 has identical polarity and both of them are electrically connected to the source 305 , thus an isolation structure with an electric potential identical to that of the source 305 is formed in the n-type semiconductor layer 303 , so as to prevent parasitic circuit elements formed in the n-type semiconductor layer 303 from latching up with other integrated circuit element (not shown). Meanwhile the on-resistance of the LDMOS transistor structure 300 can be decreased, and the breakdown voltage of the LDMOS transistor structure 300 can be increased, and the performance of the LDMOS transistor structure 300 can be improved.
- a LDMOS transistor structure wherein a guard ring is formed in a semiconductor layer in a manner of getting in touch with a barrier layer disposed in the semiconductor layer and surrounding a source and a drain. Since the guard ring and the barrier layer has the same polarity and both of them are electrically connected with the source, thus an isolation structure with an electric potential identical to that of the source is formed in a manner of surrounding the LDMOS transistor, so as to prevent the parasitic circuit elements formed in the LDMOS transistor device from latching up with other integrated circuit element, such that, the device punch-through problems due to critical dimension shrinkage can be solved. Meanwhile the on-resistance of the LDMOS transistor device can be decreased, the breakdown voltage of the LDMOS transistor device can be increased, and the performance of the LDMOS transistor device can be improved.
Abstract
A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.
Description
- The present invention relates to a semiconductor device, and more particularly to a lateral diffusion metal-oxide-semiconductor (LDMOS) transistor device.
- A LDMOS transistor device is characterized by low on-resistance and high breakdown voltage and is widespread applied in an integral part of modern day display panels, telecommunication systems, motor controllers, switch lock power supplies, inverters, and alike.
- A typical LDMOS transistor device is an asymmetric power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate and coplanar drain/source regions separated by a channel region which are fabricated in an epitaxial layer of a substrate. Wherein the drain region is formed in a drift region which is fabricated by a lightly doped drain (LDD) implant process and used to isolate the drain and the channel regions. The drain region and the gate are laterally separated by a field oxide (FOX). While the LDMOS transistor device is operated in high voltage, electric field density around the drain region can be reduced due to the existence of the drift region and the FOX, such that the breakdown voltage of the LDMOS transistor device can be improved.
- However, as the circuit critical dimensions continuing to shrinkage, parasitic circuit elements formed in the LDMOS transistor device may be more likely punch through due to the converse parasitic diode effect. Therefore, there is a need of providing an improved LDMOS transistor structure in order to obviate the drawbacks encountered from the prior art and improve the performance of the semiconductor device.
- In accordance with an aspect, the present invention provides a LDMOS transistor structure comprising a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both disposed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and surrounding the source and the drain, and is electrically connected to the source.
- In one embodiment of the present invention, the first polarity is n-type conductivity, and the second polarity is p-type conductivity.
- In one embodiment of the present invention, the barrier layer comprises a tri-layer phosphorous/antimony/phosphorous (P/Sb/P) doping structure.
- In one embodiment of the present invention, the first polarity region and a second polarity region are disposed in an n-type well which is disposed in the semiconductor layer in a manner of getting in touch with the barrier layer.
- In one embodiment of the present invention, the n-type well comprises an n-body region and a high-voltage drift N-well (HVDNW) region, wherein the first polarity region and a second polarity region are disposed in the n-body region, and the n-body region is disposed in the HVDNW region.
- In one embodiment of the present invention, the drift region has a doping concentration substantially greater than that of the semiconductor layer.
- In one embodiment of the present invention, the LDMOS transistor structure further comprises a first gate disposed on the semiconductor layer and partially straddling over a first field oxide (FOX), wherein the first gate and the first drain are separated from each other by the first FOX.
- In one embodiment of the present invention, the LDMOS transistor structure further comprises a second drain disposed in the semiconductor layer and a second gate disposed over the semiconductor layer, wherein the second gate partially straddles over a second FOX by which the second gate and the second drain are separated from each other.
- In one embodiment of the present invention, the first drain and the second drain constitute a symmetric structure against the source, and the source serves as a common source of the first drain and the second drain.
- In one embodiment of the present invention, the second polarity region is separated into two parts by the first polarity region.
- In one embodiment of the present invention, the guard ring has a concentration decreasing gradually from a top surface of the semiconductor layer to the barrier.
- In one embodiment of the present invention, the guard ring is electrically connected to the source via an interconnection or a wire.
- In one embodiment of the present invention, the first polarity is p-type conductivity, and the second polarity is n-type conductivity. In one embodiment of the present invention, the barrier layer comprises a tri-layer boron/Indium/boron (B/In/B) doping structure.
- In accordance with the aforementioned embodiments of the present invention, a LDMOS transistor structure is provided, wherein a guard ring is formed in a semiconductor layer in a manner of getting in touch with a barrier layer disposed in the semiconductor layer and surrounding a source and a drain. Since the guard ring and the barrier have the same polarity and both of them are electrically connected with the source, thus an isolation structure with an electric potential identical to that of the source is formed in a manner of surrounding the LDMOS transistor, so as to prevent the parasitic circuit elements formed in the LDMOS transistor device from latching up with other integrated circuit element, such that the device punch-through problems due to critical dimension shrinkage can be solved. Meanwhile the on-resistance of the LDMOS transistor device can be decreased, the breakdown voltage of the LDMOS transistor device can be increased, and the performance of the LDMOS transistor device can be improved.
- The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
-
FIG. 1 illustrates a cross-sectional view of a LDMOS transistor structure in accordance with one embodiment of the present invention; -
FIG. 2 illustrates a cross-sectional view of a LDMOS transistor structure in accordance with another embodiment of the present invention; and -
FIG. 3 illustrates a cross-sectional view of a LDMOS transistor structure in accordance with further embodiment of the present invention. - A LDMOS transistor structure is provided by the present invention to solve device punch-through problems due to critical dimension shrinkage. The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
-
FIG. 1 illustrates a cross-sectional view of aLDMOS transistor structure 100 in accordance with one embodiment of the present invention. TheLDMOS transistor structure 100 comprises asubstrate 101, abarrier layer 102, a p-type semiconductor layer 103, agate 104, asource 105, adrain 106, a FOX 107, aguard ring 108 and agate oxide layer 109. - The
substrate 101 is a semiconductor substrate preferably is a silicon substrate. Thebarrier layer 102 is an n-type doping layer formed in thesubstrate 101. In some embodiments of the present invention, thebarrier layer 102 extends downward in to thesubstrate 101 from asurface 101 a of thesubstrate 101; and thebarrier layer 102 comprises phosphorous and antimony dopants. In the present embodiment, thebarrier layer 102 has a tri-layer P/Sb/P doping structure; thebarrier layer 102 includes anantimony doping layer 102 a and twophosphorous doping layers antimony doping layer 102 a has a doping concentration greater than that of the twophosphorous doping layers antimony layer 102 a. - In some embodiments, the
barrier layer 102 has a thickness about 3 μm, and the tri-layer P/Sb/P doping structure is formed by at least three separated doping processes which are performed to implant phosphorous dopants, antimony dopants and phosphorous dopants in sequence into thesubstrate 101. Alternatively, in some other embodiments, the tri-layer P/Sb/P doping structure may be formed by steps as follows: A phosphorous doping layer is firstly formed in thesubstrate 101, and theantimony doping layer 102 a is then formed in the phosphorous doping layer by implanting antimony dopants into the phosphorous doping layer, so as to divide the phosphorous doping layer into two parts (referred as the twophosphorous doping layers - The p-
type semiconductor layer 103 is an epitaxial layer formed on thesubstrate 101, wherein the epitaxial layer is disposed over and in contact with thebarrier layer 102. In the present embodiment, the p-type semiconductor layer 103 is doped with p-type dopants, such as boron ions, and has a thickness about 7 μm. - The
source 105 has a p-type region 105 a and an n-type region 105 b disposed in an n-type well 110 formed in the p-type semiconductor layer 103 in a manner of getting in touch with thebarrier layer 102. In some embodiments of the present invention, the n-type well 110 comprises an n-body region (referred as N-Body region) 110 a, a high-voltage drift N-well (referred as HVDNW region) 110, wherein the N-Body region 110 a is disposed in theHVDNW region 110 b, and the p-type region 105 a and the n-type region 105 b are disposed in the N-Body region 110 a. In the present embodiment, the n-type region 105 b is a high concentration n-type doping region (referred asN+ region 105 b), and the p-type region 105 a is a high concentration p-type doping region (referred asP+ region 105 a). TheN+ region 105 b has a doping concentration substantially greater than that of the N-Body region 110 a, and the N-Body region 110 a has a doping concentration substantially greater than that of theHVDNW region 110 b. - The
drain 106 is formed in the p-type semiconductor layer 103 and has a high concentration p-type doping region (referred as P+ region) 106 a and a p-type drift region (referred as P-Drift region) 106 b. Wherein theP+ region 106 a is disposed in the P-Driftregion 106 b and has a doping concentration substantially greater than that of the P-Driftregion 106 b. Besides, the P-Driftregion 106 b has a doping concentration substantially greater than that of the p-type semiconductor layer 103. - The
gate oxide layer 109 is blanket over thesource 105 and a portion of the p-type semiconductor layer 103. The FOX 107 is formed in the p-type semiconductor layer 103 and protrudes beyond atop surface 103 a of the p-type semiconductor layer 103. Thegate 104 is disposed on thegate oxide layer 109 and partially straddles over the FOX 107, wherein thegate 104 and thedrain 106 are separated from each other by the FOX 107. - The
guard ring 108 is an n-type doping region extending downward in to the p-type semiconductor layer 103 from thetop surface 103 a of the p-type semiconductor layer 103 in a manner of getting in touch with thebarrier layer 102 and surrounding thesource 105 and thedrain 106. In some embodiments of the present invention, theguard ring 108 is electrically connected to thesource 105 via aconductive structure 111, such as an interconnection or a wire. In some embodiments of the present invention, theguard ring 108 comprises a high concentration n-type doping region (referred as N+ region) 108 a, an n-type well (referred as N-Well region) 108 b, an n-type drift region (referred as N-Drift region) 108 c and a high-voltage drift N-well (referred as HVDNW region) 108 d. - Wherein the
N+ region 108 a extends downwards in to the N-Well region 108 b from thetop surface 103 a of the p-type semiconductor layer 103; the N-Well region 108 b is disposed in the N-Drift region 108 c; and the N-Drift region 108 c is disposed in theHVDNW region 108 d. Besides, theN+ region 108 a has a doping concentration substantially greater than that of the N-Well region 108 b; the doping concentration of the N-Well region 108 b is substantially greater than that of the N-Drift region 108 c; and the doping concentration of the N-Drift region 108 c is substantially greater than that of theHVDNW region 108 d. In other words, theguard ring 108 has a concentration decreasing gradually from thetop surface 103 a of thesemiconductor layer 103 to thebarrier 102. - Since the
guard ring 108 and thebarrier layer 102 has identical polarity and both of them are electrically connected to thesource 105, thus an isolation structure with an electric potential identical to that of thesource 105 is formed in the p-type semiconductor layer 103 so as to prevent the parasitic circuit elements formed in the p-type semiconductor layer 103 from latching up with other integrated circuit element (not shown). Meanwhile the on-resistance of theLDMOS transistor structure 100 can be decreased, the breakdown voltage of theLDMOS transistor structure 100 can be increased, and the performance of theLDMOS transistor structure 100 can be improved. -
FIG. 2 illustrates a cross-sectional view of aLDMOS transistor structure 200 in accordance with another embodiment of the present invention. The physical structure of theLDMOS transistor structure 200 is generally similar to that of theLDMOS transistor structure 100 depicted inFIG. 1 . The difference therebetween is that theLDMOS transistor structure 200 further comprises agate 204 and adrain 206. For the purpose of clear description, thereinafter, the same elements may be indicated by the same numbers. - In the present embodiment, the
drain source 105, and thesource 205 serves as the common source thereof. Thesource 205 comprises an n-type region 205 b and two p-type regions 205 a and 205 c disposed in the n-type well 110 formed in the p-type semiconductor layer 103, wherein the two p-type regions 205 a and 205 c are separated by the n-type region 205 b. The n-type region 205 b is a high concentration n-type doping region (referred asN+ region 205 b), and these two p-type region 205 a and 205 c are high concentration p-type doping regions (referred asP+ region 205 a and 205 c). TheN+ region 205 b has a doping concentration substantially greater than that of the N-Body region 110 a. - The
drain 206 is formed in the p-type semiconductor layer 103 and has a high concentration p-type doping region (referred as P+ region) 206 a and a p-type drift region (referred as P-Drift region) 206 b. Wherein theP+ region 206 a is disposed in the P-Drift region 206 b and has a doping concentration substantially greater than that of the P-Drift region 206 b. Besides, the P-Drift region 206 b has a doping concentration substantially greater than that of the p-type semiconductor layer 103. Thegate 204 is disposed on thegate oxide layer 109 and partially straddles over theFOX 107, wherein thegate 204 and thedrain 206 are separated from each other by theFOX 107. - Along the same line as the
LDMOS transistor structure 100 indicated, an isolation structure with an electric potential identical to that of thesource 205 is formed in the p-type semiconductor layer 103, so as to prevent parasitic circuit elements formed therein from latching up with other integrated circuit element (not shown). Meanwhile the on-resistance of theLDMOS transistor structure 200 can be decreased, the breakdown voltage of theLDMOS transistor structure 200 can be increased, and the performance of theLDMOS transistor structure 200 can be improved. - It should be appreciated that the p-channel transistors described in the aforementioned embodiments are just illustrative; the applying scope of the present invention may not be limited. Thus the features and advantages of the present invention may be further applied by an n-channel transistor.
-
FIG. 3 illustrates a cross-sectional view of aLDMOS transistor structure 300 in accordance with further embodiment of the present invention. The physical structure of theLDMOS transistor structure 300 is generally similar to that of theLDMOS transistor structure 200 depicted inFIG. 2 . The difference there between is that theLDMOS transistor structure 300 is an n-channel transistor structure rather than a p-channel transistor structure. - The
LDMOS transistor structure 300 comprises asubstrate 301, abarrier layer 302, an n-type semiconductor layer 303, twogates source 305, twodrains 306 and 316, aFOX 307, aguard ring 308 and agate oxide layer 309. - The
barrier layer 302 is an n-type doping layer formed in thesubstrate 101, wherein thebarrier layer 302 comprises indium and boron dopants. Although thebarrier layer 302 of the present embodiment is illustrated as a single layer structure (seeFIG. 3 ), in some other embodiments of the present invention, thebarrier layer 302 may otherwise comprise a tri-layer B/In/B doping structure, wherein the indium doping layer (not shown) has a doping concentration greater than that of the two boron doping layers (not shown) sandwiching the indium layer. - The n-
type semiconductor layer 303 is an epitaxial layer formed on thesubstrate 301, wherein the epitaxial layer is disposed over and in contact with thebarrier 302. - The
source 305 comprises an p-type region 305 b and two n-type regions 305 a and 305 c disposed in an p-type well 310 formed in the n-type semiconductor layer 303, wherein the p-type well 310 comprises an p-body region (referred as P-Body region) 310 a, a high-voltage drift p-well (referred as HVDPW region) 310 b. The P-Body region 310 a is disposed in theHVDPW region 310 b, and the two n-type region 305 a and 305 c and the p-type region 305 b are disposed in the P-Body region 310 a, wherein the two n-type regions 305 a and 305 c are separated by the p-type region 305 b. In the present embodiment, the p-type region 305 b is a high concentration p-type doping region (referred asP+ region 305 b), these two n-type region 305 a and 305 c are high concentration n-type doping regions (referred asN+ region 305 a and 305 c); theP+ region 305 b has a doping concentration substantially greater than that of the P-Body region 310 a, and the concentration of the P-Body region 310 a is substantially greater than that of theHVDPW region 310 b. - The drain 306 is formed in the n-
type semiconductor layer 303 and has a high concentration n-type doping region (referred as N+ region) 306 a and an n-type drift region (referred as N-Drift region) 306 b, wherein theN+ region 306 a is disposed in the N-Drift region 306 b and has a doping concentration substantially greater than that of the N-Drift region 306 b. Besides, the N-Drift region 306 b has a doping concentration substantially greater than that of the n-type semiconductor layer 303. - The
drain 316 is formed in the n-type semiconductor layer 303 and has a high concentration n-type doping region (referred as N+ region) 316 a and an n-type drift region (referred as N-Drift region) 316 b, wherein theN+ region 316 a is disposed in the N-Drift region 316 b and has a doping concentration substantially greater than that of the N-Drift region 316 b. Besides, the N-Drift region 316 b has a doping concentration substantially greater than that of the n-type semiconductor layer 303. - The
gate oxide layer 309 is blanket over thesource 305 and a portion of the n-type semiconductor layer 303. TheFOX 307 is formed in the n-type semiconductor layer 303 and protrudes beyond atop surface 303 a of the n-type semiconductor layer 303. Thegates gate oxide layer 309 and partially straddle over theFOX 307 by which thegate 304 and the drain 306 are separated from each other and so do thegate 314 and thedrain 316. - The
guard ring 308 is a p-type doping region extending downward in to the n-type semiconductor layer 303 from thetop surface 303 a of the n-type semiconductor layer 303 in a manner of getting in touch with thebarrier layer 302 and surrounding thesource 305 and thedrains 306 and 316. Wherein, theguard ring 308 is electrically connected to thesource 305 via a conductive structure 311, such as an interconnection or a wire. In some embodiments of the present invention, theguard ring 308 comprises a high concentration p-type doping region (referred as P+ region) 308 a, a p-type well (referred as P-Well region) 308 b, a p-type drift region (referred as P-Drift region) 308 c and a high-voltage drift p-well (referred as HVDPW region) 308 d. - Wherein the
P+ region 308 a extends downwards in to the P-Well region 308 b from thetop surface 303 a of the n-type semiconductor layer 303; the P-Well region 308 b is disposed in the P-Drift region 308 c; and the P-Drift region 308 c is disposed in theHVDPW region 308 d. Besides, theP+ region 308 a has a doping concentration substantially greater than that of the P-Well region 308 b; the doping concentration of the P-Well region 308 b is substantially greater than that of the P-Drift region 308 c; and the doping concentration of the P-Drift region 308 c is substantially greater than that of theHVDPW region 308 d. - Since the
guard ring 308 and thebarrier layer 302 has identical polarity and both of them are electrically connected to thesource 305, thus an isolation structure with an electric potential identical to that of thesource 305 is formed in the n-type semiconductor layer 303, so as to prevent parasitic circuit elements formed in the n-type semiconductor layer 303 from latching up with other integrated circuit element (not shown). Meanwhile the on-resistance of theLDMOS transistor structure 300 can be decreased, and the breakdown voltage of theLDMOS transistor structure 300 can be increased, and the performance of theLDMOS transistor structure 300 can be improved. - In accordance with the aforementioned embodiments of the present invention, a LDMOS transistor structure is provided, wherein a guard ring is formed in a semiconductor layer in a manner of getting in touch with a barrier layer disposed in the semiconductor layer and surrounding a source and a drain. Since the guard ring and the barrier layer has the same polarity and both of them are electrically connected with the source, thus an isolation structure with an electric potential identical to that of the source is formed in a manner of surrounding the LDMOS transistor, so as to prevent the parasitic circuit elements formed in the LDMOS transistor device from latching up with other integrated circuit element, such that, the device punch-through problems due to critical dimension shrinkage can be solved. Meanwhile the on-resistance of the LDMOS transistor device can be decreased, the breakdown voltage of the LDMOS transistor device can be increased, and the performance of the LDMOS transistor device can be improved.
- While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Claims (14)
1. A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprising:
a barrier layer with a first polarity consisting of two first doping layers sandwiching a second doping layer disposed in a substrate, wherein the second doping layer has a doping concentration greater than that of the two first doping layers;
a semiconductor layer with a second polarity, disposed on the barrier layer;
a source, having a first polarity region and a second polarity region disposed in the semiconductor layer;
a first drain, disposed in the semiconductor layer and having a drift region with the second polarity; and
a guard ring with the first polarity, extending downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and surrounding the source and the drain, and electrically connected to the source.
2. The LDMOS transistor structure according to claim 1 , wherein the first polarity is n-type conductivity; and the second polarity is p-type conductivity.
3. The LDMOS transistor structure according to claim 2 , wherein the barrier layer comprises a tri-layer phosphorous/antimony/phosphorous (P/Sb/P) doping structure.
4. The LDMOS transistor structure according to claim 2 , wherein the first polarity region and a second polarity region are disposed in an n-type well which is disposed in the semiconductor layer in a manner of getting in touch with the barrier layer.
5. The LDMOS transistor structure according to claim 4 , wherein the n-type well comprises an n-body region and a high-voltage drift N-well (HVDNW) region; the first polarity region and a second polarity region are disposed in the n-body region, and the n-body region is disposed in the HVDNW region.
6. The LDMOS transistor structure according to claim 1 , wherein the drift region has a doping concentration substantially greater than that of the semiconductor layer.
7. The LDMOS transistor structure according to claim 1 , further comprising a first gate disposed on the semiconductor layer and partially straddling over a first field oxide (FOX), wherein the first gate and the first drain are separated from each other by the first FOX.
8. The LDMOS transistor structure according to claim 7 , further comprising:
a second drain, disposed in the semiconductor layer; and
a second gate, disposed over the semiconductor layer and partially straddling over a second FOX, wherein the second gate and the second drain are separated from each other by the second FOX.
9. The LDMOS transistor structure according to claim 8 , wherein the first drain and the second drain constitute a symmetric structure against the source, and the source serves as a common source thereof.
10. The LDMOS transistor structure according to claim 9 , wherein the second polarity region is separated into two parts by the first polarity region.
11. The LDMOS transistor structure according to claim 1 , wherein the guard ring has a concentration decreasing gradually from a top surface of the semiconductor layer to the barrier.
12. The LDMOS transistor structure according to claim 1 , the guard ring is electrically connected to the source via an interconnection or a wire.
13. The LDMOS transistor structure according to claim 1 , wherein the first polarity is p-type conductivity; and the second polarity is n-type conductivity.
14. The LDMOS transistor structure according to claim 13 , wherein the barrier layer comprises a tri-layer boron/Indium/boron (B/In/B) doping structure.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI812995B (en) * | 2020-08-13 | 2023-08-21 | 大陸商杭州芯邁半導體技術有限公司 | Sic mosfet device and manufacturing method thereof |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9093494B2 (en) * | 2013-02-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Guard structure for semiconductor structure and method of forming guard layout pattern for semiconductor layout pattern |
US20150214361A1 (en) * | 2014-01-30 | 2015-07-30 | Macronix International Co., Ltd. | Semiconductor Device Having Partial Insulation Structure And Method Of Fabricating Same |
Family Cites Families (94)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4344081A (en) | 1980-04-14 | 1982-08-10 | Supertex, Inc. | Combined DMOS and a vertical bipolar transistor device and fabrication method therefor |
US4396999A (en) | 1981-06-30 | 1983-08-02 | International Business Machines Corporation | Tunneling transistor memory cell |
US4893160A (en) | 1987-11-13 | 1990-01-09 | Siliconix Incorporated | Method for increasing the performance of trenched devices and the resulting structure |
US4890146A (en) * | 1987-12-16 | 1989-12-26 | Siliconix Incorporated | High voltage level shift semiconductor device |
US4918333A (en) | 1988-10-31 | 1990-04-17 | Anderson Floyd E | Microprocessor having high current drive |
US4958089A (en) | 1988-12-20 | 1990-09-18 | Gazelle Microcircuits, Inc. | High output drive FET buffer for providing high initial current to a subsequent stage |
US5040045A (en) | 1990-05-17 | 1991-08-13 | U.S. Philips Corporation | High voltage MOS transistor having shielded crossover path for a high voltage connection bus |
US5268589A (en) | 1990-09-28 | 1993-12-07 | Siemens Aktiengesellschaft | Semiconductor chip having at least one electrical resistor means |
US5296393A (en) | 1990-11-23 | 1994-03-22 | Texas Instruments Incorporated | Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods |
IT1254799B (en) | 1992-02-18 | 1995-10-11 | St Microelectronics Srl | VDMOS TRANSISTOR WITH IMPROVED VOLTAGE SEALING CHARACTERISTICS. |
US5346835A (en) | 1992-07-06 | 1994-09-13 | Texas Instruments Incorporated | Triple diffused lateral resurf insulated gate field effect transistor compatible with process and method |
JP3203814B2 (en) | 1992-10-19 | 2001-08-27 | 富士電機株式会社 | Semiconductor device |
US5326711A (en) | 1993-01-04 | 1994-07-05 | Texas Instruments Incorporated | High performance high voltage vertical transistor and method of fabrication |
US5585294A (en) | 1994-10-14 | 1996-12-17 | Texas Instruments Incorporated | Method of fabricating lateral double diffused MOS (LDMOS) transistors |
US5534721A (en) | 1994-11-30 | 1996-07-09 | At&T Corp. | Area-efficient layout for high voltage lateral devices |
US5939763A (en) | 1996-09-05 | 1999-08-17 | Advanced Micro Devices, Inc. | Ultrathin oxynitride structure and process for VLSI applications |
US6624495B2 (en) | 1997-04-23 | 2003-09-23 | Altera Corporation | Adjustable threshold isolation transistor |
US6002156A (en) | 1997-09-16 | 1999-12-14 | Winbond Electronics Corp. | Distributed MOSFET structure with enclosed gate for improved transistor size/layout area ratio and uniform ESD triggering |
US5998301A (en) | 1997-12-18 | 1999-12-07 | Advanced Micro Devices, Inc. | Method and system for providing tapered shallow trench isolation structure profile |
GB9826291D0 (en) | 1998-12-02 | 1999-01-20 | Koninkl Philips Electronics Nv | Field-effect semi-conductor devices |
US5950090A (en) | 1998-11-16 | 1999-09-07 | United Microelectronics Corp. | Method for fabricating a metal-oxide semiconductor transistor |
US6424005B1 (en) | 1998-12-03 | 2002-07-23 | Texas Instruments Incorporated | LDMOS power device with oversized dwell |
US6165846A (en) | 1999-03-02 | 2000-12-26 | Zilog, Inc. | Method of eliminating gate leakage in nitrogen annealed oxides |
US6066884A (en) | 1999-03-19 | 2000-05-23 | Lucent Technologies Inc. | Schottky diode guard ring structures |
US6277757B1 (en) | 1999-06-01 | 2001-08-21 | Winbond Electronics Corp. | Methods to modify wet by dry etched via profile |
JP2001015741A (en) | 1999-06-30 | 2001-01-19 | Toshiba Corp | Field effect transistor |
JP3442009B2 (en) | 1999-09-24 | 2003-09-02 | 松下電器産業株式会社 | Structure of high voltage MOS transistor |
US6277675B1 (en) | 1999-10-28 | 2001-08-21 | United Microelectronics Corp. | Method of fabricating high voltage MOS device |
US6144538A (en) | 1999-12-20 | 2000-11-07 | United Microelectronics Corp. | High voltage MOS transistor used in protection circuits |
JP4200626B2 (en) | 2000-02-28 | 2008-12-24 | 株式会社デンソー | Method for manufacturing insulated gate type power device |
US6326283B1 (en) | 2000-03-07 | 2001-12-04 | Vlsi Technology, Inc. | Trench-diffusion corner rounding in a shallow-trench (STI) process |
US6297108B1 (en) | 2000-03-10 | 2001-10-02 | United Microelectronics Corp. | Method of forming a high voltage MOS transistor on a semiconductor wafer |
US6351017B1 (en) | 2000-03-22 | 2002-02-26 | Advanced Micro Devices, Inc. | High voltage transistor with modified field implant mask |
TW441074B (en) | 2000-04-15 | 2001-06-16 | United Microelectronics Corp | Electrostatic discharge protection circuit structure for high voltage device |
JP4696335B2 (en) | 2000-05-30 | 2011-06-08 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
JP2002026328A (en) | 2000-07-04 | 2002-01-25 | Toshiba Corp | Horizontal semiconductor device |
US6306700B1 (en) | 2000-08-07 | 2001-10-23 | United Microelectronics Corp. | Method for forming high voltage devices compatible with low voltages devices on semiconductor substrate |
US6593620B1 (en) | 2000-10-06 | 2003-07-15 | General Semiconductor, Inc. | Trench DMOS transistor with embedded trench schottky rectifier |
US7075575B2 (en) | 2000-11-06 | 2006-07-11 | Isetex, Inc. | Gated vertical punch through device used as a high performance charge detection amplifier |
JP2002237591A (en) | 2000-12-31 | 2002-08-23 | Texas Instruments Inc | Dmos transistor source structure and method for manufacturing the same |
US6894349B2 (en) | 2001-06-08 | 2005-05-17 | Intersil Americas Inc. | Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide |
KR100387531B1 (en) | 2001-07-30 | 2003-06-18 | 삼성전자주식회사 | Method for fabricating semiconductor device |
US6846729B2 (en) | 2001-10-01 | 2005-01-25 | International Rectifier Corporation | Process for counter doping N-type silicon in Schottky device Ti silicide barrier |
KR100418435B1 (en) | 2001-12-26 | 2004-02-14 | 한국전자통신연구원 | Method for fabricating a power integrated circuit device |
US20040070050A1 (en) | 2002-10-10 | 2004-04-15 | Taiwan Semiconductor Manufacturing Company | Structures of vertical resistors and FETs as controlled by electrical field penetration and a band-gap voltage reference using vertical FETs operating in accumulation through the field penetration effect |
US6791155B1 (en) | 2002-09-20 | 2004-09-14 | Integrated Device Technology, Inc. | Stress-relieved shallow trench isolation (STI) structure and method for forming the same |
TW578321B (en) | 2002-10-02 | 2004-03-01 | Topro Technology Inc | Complementary metal-oxide semiconductor structure for a battery protection circuit and battery protection circuit therewith |
KR100440263B1 (en) | 2002-10-29 | 2004-07-15 | 주식회사 하이닉스반도체 | Transistor in a semiconductor device and a method of manufacturing the same |
US6819184B2 (en) | 2002-11-06 | 2004-11-16 | Cree Microwave, Inc. | RF transistor amplifier linearity using suppressed third order transconductance |
US7019377B2 (en) | 2002-12-17 | 2006-03-28 | Micrel, Inc. | Integrated circuit including high voltage devices and low voltage devices |
US6764890B1 (en) | 2003-01-29 | 2004-07-20 | Cypress Semiconductor Corporation | Method of adjusting the threshold voltage of a mosfet |
KR100554830B1 (en) | 2003-06-05 | 2006-02-22 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
KR100493061B1 (en) | 2003-06-20 | 2005-06-02 | 삼성전자주식회사 | Single chip data processing device having embeded nonvolatile memory |
US6825531B1 (en) | 2003-07-11 | 2004-11-30 | Micrel, Incorporated | Lateral DMOS transistor with a self-aligned drain region |
US7023050B2 (en) | 2003-07-11 | 2006-04-04 | Salama C Andre T | Super junction / resurf LDMOST (SJR-LDMOST) |
US7525150B2 (en) | 2004-04-07 | 2009-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage double diffused drain MOS transistor with medium operation voltage |
US7358567B2 (en) | 2004-06-07 | 2008-04-15 | United Microelectronics Corp. | High-voltage MOS device and fabrication thereof |
US7148540B2 (en) | 2004-06-28 | 2006-12-12 | Agere Systems Inc. | Graded conductive structure for use in a metal-oxide-semiconductor device |
US7125777B2 (en) | 2004-07-15 | 2006-10-24 | Fairchild Semiconductor Corporation | Asymmetric hetero-doped high-voltage MOSFET (AH2MOS) |
JP4947931B2 (en) | 2004-08-12 | 2012-06-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US7557394B2 (en) | 2004-11-09 | 2009-07-07 | Bourns, Inc. | High-voltage transistor fabrication with trench etching technique |
US7091079B2 (en) | 2004-11-11 | 2006-08-15 | United Microelectronics Corp. | Method of forming devices having three different operation voltages |
US7368785B2 (en) | 2005-05-25 | 2008-05-06 | United Microelectronics Corp. | MOS transistor device structure combining Si-trench and field plate structures for high voltage device |
US7067365B1 (en) | 2005-05-26 | 2006-06-27 | United Microelectronics Corp. | High-voltage metal-oxide-semiconductor devices and method of making the same |
US7868394B2 (en) | 2005-08-09 | 2011-01-11 | United Microelectronics Corp. | Metal-oxide-semiconductor transistor and method of manufacturing the same |
US7477532B2 (en) | 2005-08-18 | 2009-01-13 | Semiconductor Components Industries, L.L.C. | Method of forming a start-up device and structure therefor |
JP2007134674A (en) | 2005-10-11 | 2007-05-31 | Elpida Memory Inc | Semiconductor device and its manufacturing method |
US7309636B2 (en) | 2005-11-07 | 2007-12-18 | United Microelectronics Corp. | High-voltage metal-oxide-semiconductor device and method of manufacturing the same |
CN100461375C (en) | 2005-12-05 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for making isolation structure for flash-memory semiconductor device |
US7372104B2 (en) | 2005-12-12 | 2008-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage CMOS devices |
KR100734302B1 (en) | 2006-01-12 | 2007-07-02 | 삼성전자주식회사 | Semiconductor integrated circuit device for increasing integration density and fabrication method thereof |
US20070273001A1 (en) | 2006-05-24 | 2007-11-29 | Jung-Ching Chen | System on chip and method for manufacturing the same |
US20080160706A1 (en) | 2006-12-27 | 2008-07-03 | Jin Hyo Jung | Method for fabricating semiconductor device |
US20080185629A1 (en) | 2007-02-01 | 2008-08-07 | Denso Corporation | Semiconductor device having variable operating information |
US7692271B2 (en) * | 2007-02-28 | 2010-04-06 | International Business Machines Corporation | Differential junction varactor |
US7602037B2 (en) * | 2007-03-28 | 2009-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage semiconductor devices and methods for fabricating the same |
US7893490B2 (en) * | 2007-04-30 | 2011-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | HVNMOS structure for reducing on-resistance and preventing BJT triggering |
US7763928B2 (en) | 2007-05-31 | 2010-07-27 | United Microelectronics Corp. | Multi-time programmable memory |
US7541247B2 (en) * | 2007-07-16 | 2009-06-02 | International Business Machines Corporation | Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication |
EP2203933A2 (en) | 2007-10-19 | 2010-07-07 | Nxp B.V. | High voltage semiconductor device |
US7741659B2 (en) | 2007-10-25 | 2010-06-22 | United Microelectronics Corp. | Semiconductor device |
US20090111252A1 (en) | 2007-10-30 | 2009-04-30 | United Microelectronics Corp. | Method for forming deep well region of high voltage device |
US20090159966A1 (en) | 2007-12-20 | 2009-06-25 | Chih-Jen Huang | High voltage semiconductor device, method of fabricating the same, and method of fabricating the same and a low voltage semiconductor device together on a substrate |
US8324705B2 (en) | 2008-05-27 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Schottky diodes having low-voltage and high-concentration rings |
KR100974697B1 (en) | 2008-07-09 | 2010-08-06 | 주식회사 동부하이텍 | Lateral double diffused metal oxide semiconductor device and manufacturing method of lateral double diffused metal oxide semiconductor device |
US7906810B2 (en) | 2008-08-06 | 2011-03-15 | United Microelectronics Corp. | LDMOS device for ESD protection circuit |
US7982288B2 (en) | 2008-10-17 | 2011-07-19 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
US7902600B2 (en) | 2008-12-11 | 2011-03-08 | United Microelectronics Corp. | Metal oxide semiconductor device |
TWI397180B (en) * | 2008-12-17 | 2013-05-21 | Vanguard Int Semiconduct Corp | Lateral diffused metal oxide semiconductor (ldmos) devices with electrostatic discharge (esd) protection capability in integrated circuit |
US8115253B2 (en) | 2009-09-10 | 2012-02-14 | United Microelectronics Corp. | Ultra high voltage MOS transistor device |
US20110079849A1 (en) | 2009-10-06 | 2011-04-07 | Ting-Zhou Yan | Lateral-diffusion metal-oxide-semiconductor device |
US8304830B2 (en) * | 2010-06-10 | 2012-11-06 | Macronix International Co., Ltd. | LDPMOS structure for enhancing breakdown voltage and specific on resistance in biCMOS-DMOS process |
US8450801B2 (en) * | 2010-08-27 | 2013-05-28 | United Microelectronics Corp. | Lateral-diffusion metal-oxide-semiconductor device |
US9373619B2 (en) * | 2011-08-01 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage resistor with high voltage junction termination |
-
2012
- 2012-08-14 US US13/585,801 patent/US8643104B1/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI812995B (en) * | 2020-08-13 | 2023-08-21 | 大陸商杭州芯邁半導體技術有限公司 | Sic mosfet device and manufacturing method thereof |
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