CN104465773A - Terminal structure of metal oxide semiconductor field effect transistor and manufacturing method of terminal structure of metal oxide semiconductor field effect transistor - Google Patents
Terminal structure of metal oxide semiconductor field effect transistor and manufacturing method of terminal structure of metal oxide semiconductor field effect transistor Download PDFInfo
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- CN104465773A CN104465773A CN201410629243.1A CN201410629243A CN104465773A CN 104465773 A CN104465773 A CN 104465773A CN 201410629243 A CN201410629243 A CN 201410629243A CN 104465773 A CN104465773 A CN 104465773A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 21
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 21
- 230000005669 field effect Effects 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 238000002513 implantation Methods 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 239000000243 solution Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000005684 electric field Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention relates to a terminal structure of a metal oxide semiconductor field effect transistor (MOSFET). The terminal structure comprises an N-type cut-off ring and further comprises a first P-type low-doped region and a second P-type low-doped region, wherein the first P-type low-doped region and the second P-type low-doped region are formed between the cut-off ring and an active region through ion implantation, the implantation dose ranges from 1.5*10<11>/cm<2> to 2*10<13>/cm<2>, implantation energy ranges from 20 kilo electron volts to 80 kilo electron volts, the first P-type low-doped region is closer to the active region than the second P-type low-doped region, and the length of the first P-type low-doped region is smaller than that of the second P-type low-doped region. The invention further relates to a manufacturing method of the terminal structure of the MOSFET. The two P-type low-doped regions are adopted for reducing a surface electric field and increasing the breakdown voltage of the MOSFET, the terminal structure replaces a traditional terminal structure with a plurality of voltage dividing rings, the terminal size is greatly reduced, the effective use area of a chip is increased, and parameters of the chip are more excellent under the same area.
Description
Technical field
The present invention relates to semiconductor technology, particularly relate to a kind of terminal structure of metal oxide semiconductor field effect tube, also relate to a kind of manufacture method of terminal structure of metal oxide semiconductor field effect tube.
Background technology
Metal oxide semiconductor field effect tube (MOSFET) market competition more and more encourages, and each producer is all reducing costs by every means, and the scheme of employing mainly comprises raising current density, raising chip effectively utilizes area, reduces terminal size.
The terminal of MOSFET still adopts potential dividing ring structure mostly at present, and the shortcoming of this structure is that chip occupying area is larger.
Summary of the invention
Based on this, be necessary to provide the terminal structure of the metal oxide semiconductor field effect tube that a kind of size is less.
A terminal structure for metal oxide semiconductor field effect tube, comprises the cut-off ring of N-type, and also comprise and be formed at a P type low doped region between described cut-off ring and active area and the 2nd P type low doped region by ion implantation, implantation dosage is 1.5*10
11~ 2*10
13/ cm
2, Implantation Energy is 20 kiloelectron-volts ~ 80 kiloelectron-volts, and described in two P type low doped region, a P type low doped region is relatively closer to described active area, and the length of a described P type low doped region is less than the length of described 2nd P type low doped region.
Wherein in an embodiment, the length of a described P type low doped region is 10 ~ 50 microns, and the length of described 2nd P type low doped region is 30 ~ 200 microns.
Wherein in an embodiment, the spacing of a described P type low doped region and the 2nd P type low doped region is 4 ~ 20 microns.
Wherein in an embodiment, also comprise and be located at the P type trap zone of a described P type low doped region near side, described active area, described P type trap zone is connected with a described P type low doped region.
There is a need to the manufacture method of the terminal structure that a kind of metal oxide semiconductor field effect tube is provided.
A manufacture method for the terminal structure of metal oxide semiconductor field effect tube, comprises the following steps: to provide N-type substrate; Described N-type substrate forms oxide layer; By photoetching and etch described oxide layer and form two p type island regions and inject windows; Inject window to implanting p-type foreign ion in described N-type substrate by two p type island regions, form the P type low doped region near active area and relative the 2nd P type low doped region away from active area, implantation dosage is 1.5*10
11~ 2*10
13/ cm
2, Implantation Energy is 20 kiloelectron-volts ~ 80 kiloelectron-volts; The length of a described P type low doped region is less than the length of described 2nd P type low doped region; DIFFUSION TREATMENT is carried out to the foreign ion of a described P type low doped region and the 2nd P type low doped region; Form polysilicon field plate, described polysilicon field plate covers the oxide layer above a described P type low doped region; Described 2nd P type low doped region away from the side photoetching of a described P type low doped region and inject N-type ion formed cut-off ring.
Wherein in an embodiment, after the step of DIFFUSION TREATMENT is carried out to the foreign ion of a described P type low doped region and the 2nd P type low doped region, the length of a described P type low doped region is 10 ~ 50 microns, the length of described 2nd P type low doped region is 30 ~ 200 microns, and the spacing of a described P type low doped region and the 2nd P type low doped region is 4 ~ 20 microns.
Wherein in an embodiment, after the step of described formation polysilicon field plate, also be included in the side implanting p-type ion of a described P type low doped region near described active area, diffusion forms the step of the P type trap zone be connected with a described P type low doped region afterwards.
Wherein in an embodiment, described in the step of described N-type substrate formation oxide layer, the thickness of the oxide layer of formation is 800 ~ 1500 microns.
Wherein in an embodiment, described by photoetching and etch described oxide layer and form the step that windows are injected in two p type island regions, be adopt BOE solution to carry out wet etching.
Wherein in an embodiment, described employing BOE solution carries out in the step of wet etching, latter two p type island region injection window of corrosion remains with the sacrificial oxide layer that thickness is less than 20 dusts.
The terminal structure of above-mentioned MOSFET and manufacture method thereof, adopt two low-doped P-districts to reduce surface field, improve the puncture voltage of MOSFET, instead of the terminal structure of traditional multiple potential dividing rings, substantially reduce terminal size, improve chip effectively utilize area, under equal area, make the parameter of chip more excellent.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will become more clear.Reference numeral identical in whole accompanying drawing indicates identical part, and does not deliberately draw accompanying drawing by actual size equal proportion convergent-divergent, focuses on purport of the present invention is shown.
Fig. 1 is the schematic diagram of the MOSFET chip being provided with terminal;
Fig. 2 is the schematic cross-section of MOSFET terminal structure in an embodiment;
Fig. 3 is the flow chart of the manufacture method of the terminal structure of MOSFET in an embodiment.
Embodiment
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully.First-selected embodiment of the present invention is given in accompanying drawing.But the present invention can realize in many different forms, is not limited to embodiment described herein.On the contrary, the object of these embodiments is provided to be make to disclosure of the present invention more thoroughly comprehensively.
It should be noted that, when element is called as " being fixed on " another element, directly can there is element placed in the middle in it on another element or also.When an element is considered to " connection " another element, it can be directly connected to another element or may there is centering elements simultaneously.Term as used herein " vertical ", " level ", " on ", D score, "left", "right" and similar statement just for illustrative purposes.
Unless otherwise defined, all technology used herein and scientific terminology are identical with belonging to the implication that those skilled in the art of the present invention understand usually.The object of term used in the description of the invention herein just in order to describe specific embodiment, is not intended to be restriction the present invention.Term as used herein " and/or " comprise arbitrary and all combinations of one or more relevant Listed Items.
The invention provides the terminal structure of a kind of MOSFET.Fig. 1 is the schematic diagram of the MOSFET chip being provided with terminal, and wherein edge is without part and the terminal of filling lines, and centre has the part of filling lines to be active area.See Fig. 2, terminal structure comprises cut-off ring 40, P type low doped region 22 and a 2nd P type low doped region 24 of N-type.Wherein end ring 40 and be arranged in the side of terminal near chip boundary, a P type low doped region 22 and the 2nd P type low doped region 24 are positioned at the side of terminal near chip center, namely near the side of active area.One P type low doped region 22 and the 2nd P type low doped region 24 are diffuseed to form by ion implantation after heat, and implantation dosage is 1.5*10
11~ 2*10
13/ cm
2, Implantation Energy is 20 kiloelectron-volts ~ 80 kiloelectron-volts.The length of the one P type low doped region 22 is less than the length of the 2nd P type low doped region 24, and this length refers to the length in Fig. 2 on left and right directions.
The terminal structure of above-mentioned MOSFET, adopt two low-doped P-districts to reduce surface field, improve the puncture voltage of MOSFET, instead of the terminal structure of traditional multiple potential dividing rings, substantially reduce terminal size, improve chip effectively utilize area, under equal area, make the parameter of chip more excellent.For 600 volts of withstand voltage products, adopt the terminal size of potential dividing ring structure at 300 microns, and the terminal structure size of MOSFET of the present invention is only 100 microns ~ 250 microns.
Wherein in an embodiment, the length of a P type low doped region 22 is 10 ~ 50 microns, and the length of the 2nd P type low doped region 24 is 30 ~ 200 microns.The spacing of the one P type low doped region 22 and the 2nd P type low doped region 24 is 4 ~ 20 microns.
Structure shown in Fig. 2 also comprises P type trap zone 30, dielectric layer 50 (the present embodiment comprises oxide layer and boron-phosphorosilicate glass) and polysilicon field plate 60.P type trap zone 30 is located at a P type low doped region 22 near the side of active area, is connected with a P type low doped region 22.Polysilicon field plate 60 one end is overlapped in the dielectric layer 50 of covering the one P type low doped region 22 and the 2nd P type low doped region 24, and the other end extends in P type trap zone 30.
The present invention also provides the manufacture method of the terminal structure of a kind of MOSFET, and the manufacture method see the terminal structure of Fig. 3, MOSFET comprises the following steps:
S110, provides N-type substrate.
S120, N-type substrate forms oxide layer.
In the present embodiment, be the oxide layer that heat grows that a layer thickness is 800 ~ 1500 microns.
S130, injects window by photoetching and etching formation two p type island regions.
Photoetching also etches, and the oxide layer formed is etched two p type island regions and inject window in step S120.Be adopt wet etching in the present embodiment, BOE solution specifically can be used as etching liquid, i.e. HF and NH
4the buffered etch liquid that F is mixed to form.In the present embodiment, the oxide layer at injection window place, two p type island regions can not be completely removed, but retains skim as sacrificial oxide layer, and the thickness of sacrificial oxide layer should be less than
in the present embodiment, corrosion temperature is set to 21 degrees Celsius, and the time is 22 minutes.
S140, forms two P type low doped region by ion implantation.
Window implanting p-type ion is injected by two p type island regions.Implantation dosage is 1.5*10
11~ 2*10
13/ cm
2, Implantation Energy is 20 kiloelectron-volts ~ 80 kiloelectron-volts, thus forms low-doped P-district.Wherein a P type low doped region is relatively closer to active area, and the 2nd P type low doped region is relatively away from active area, and the length of a P type low doped region should be less than the length of the 2nd P type low doped region, could obtain desirable potential lines.
S150, carries out DIFFUSION TREATMENT to the foreign ion of two P type low doped region.
Wafer (Wafer) is heated, makes the foreign ion of two P type low doped region produce diffusion.
S160, forms polysilicon field plate.
The polysilicon field plate formed covers the oxide layer above P type low doped region.
S170, photoetching also injects N-type ion formation cut-off ring.
Inject away from the side side of chip boundary (namely near) photoetching of a P type low doped region cut-off ring that N-type ion forms N+ in the 2nd P type low doped region.
Wherein in an embodiment, be also included in the side implanting p-type ion of a P type low doped region near active area after step S160, diffusion forms the step of the P type trap zone be connected with a P type low doped region afterwards.Injection can carry out autoregistration injection by polysilicon field plate, thus does not need to carry out photoetching.
Wherein in an embodiment, the length of the P type low doped region after step S150 diffusion is 10 ~ 50 microns, and the length of the 2nd P type low doped region is 30 ~ 200 microns.The spacing of the one P type low doped region and the 2nd P type low doped region is 4 ~ 20 microns.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a manufacture method for the terminal structure of metal oxide semiconductor field effect tube, comprises the following steps:
N-type substrate is provided;
Described N-type substrate forms oxide layer;
By photoetching and etch described oxide layer and form two p type island regions and inject windows;
Inject window to implanting p-type foreign ion in described N-type substrate by two p type island regions, form the P type low doped region near active area and relative the 2nd P type low doped region away from active area, implantation dosage is 1.5*10
11~ 2*10
13/ cm
2, Implantation Energy is 20 kiloelectron-volts ~ 80 kiloelectron-volts; The length of a described P type low doped region is less than the length of described 2nd P type low doped region;
DIFFUSION TREATMENT is carried out to the foreign ion of a described P type low doped region and the 2nd P type low doped region;
Form polysilicon field plate, described polysilicon field plate covers the oxide layer above a described P type low doped region;
Described 2nd P type low doped region away from the side photoetching of a described P type low doped region and inject N-type ion formed cut-off ring.
2. the manufacture method of the terminal structure of metal oxide semiconductor field effect tube according to claim 1, it is characterized in that, after the step of DIFFUSION TREATMENT is carried out to the foreign ion of a described P type low doped region and the 2nd P type low doped region, the length of a described P type low doped region is 10 ~ 50 microns, the length of described 2nd P type low doped region is 30 ~ 200 microns, and the spacing of a described P type low doped region and the 2nd P type low doped region is 4 ~ 20 microns.
3. the manufacture method of the terminal structure of metal oxide semiconductor field effect tube according to claim 1, it is characterized in that, after the step of described formation polysilicon field plate, also be included in the side implanting p-type ion of a described P type low doped region near described active area, diffusion forms the step of the P type trap zone be connected with a described P type low doped region afterwards.
4. the manufacture method of the terminal structure of metal oxide semiconductor field effect tube according to claim 1, is characterized in that, described in the step of described N-type substrate formation oxide layer, the thickness of the oxide layer of formation is 800 ~ 1500 microns.
5. the manufacture method of the terminal structure of metal oxide semiconductor field effect tube according to claim 1, it is characterized in that, described by photoetching and etch described oxide layer and form the step that windows are injected in two p type island regions, be adopt BOE solution to carry out wet etching.
6. the manufacture method of the terminal structure of metal oxide semiconductor field effect tube according to claim 5, it is characterized in that, described employing BOE solution carries out in the step of wet etching, latter two p type island region injection window of corrosion remains with the sacrificial oxide layer that thickness is less than 20 dusts.
7. the terminal structure of a metal oxide semiconductor field effect tube, comprise the cut-off ring of N-type, it is characterized in that, also comprise and be formed at a P type low doped region between described cut-off ring and active area and the 2nd P type low doped region by ion implantation, implantation dosage is 1.5*10
11~ 2*10
13/ cm
2, Implantation Energy is 20 kiloelectron-volts ~ 80 kiloelectron-volts, and described in two P type low doped region, a P type low doped region is relatively closer to described active area, and the length of a described P type low doped region is less than the length of described 2nd P type low doped region.
8. the terminal structure of metal oxide semiconductor field effect tube according to claim 7, is characterized in that, the length of a described P type low doped region is 10 ~ 50 microns, and the length of described 2nd P type low doped region is 30 ~ 200 microns.
9. the terminal structure of metal oxide semiconductor field effect tube according to claim 8, is characterized in that, the spacing of a described P type low doped region and the 2nd P type low doped region is 4 ~ 20 microns.
10. the terminal structure of metal oxide semiconductor field effect tube according to claim 7, it is characterized in that, also comprise and be located at the P type trap zone of a described P type low doped region near side, described active area, described P type trap zone is connected with a described P type low doped region.
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|---|---|---|---|
| CN201410629243.1A CN104465773B (en) | 2014-11-10 | 2014-11-10 | The terminal structure and its manufacture method of metal oxide semiconductor field effect tube |
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|---|---|---|---|
| CN201410629243.1A CN104465773B (en) | 2014-11-10 | 2014-11-10 | The terminal structure and its manufacture method of metal oxide semiconductor field effect tube |
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| CN104465773A true CN104465773A (en) | 2015-03-25 |
| CN104465773B CN104465773B (en) | 2018-01-19 |
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| CN109524474A (en) * | 2018-11-08 | 2019-03-26 | 西安电子科技大学 | The 4H-SiC metal-semiconductor field effect transistor being lightly doped with grid edge leakage side section |
| CN109560119A (en) * | 2017-09-25 | 2019-04-02 | 新唐科技股份有限公司 | High voltage semiconductor element |
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| CN109560119A (en) * | 2017-09-25 | 2019-04-02 | 新唐科技股份有限公司 | High voltage semiconductor element |
| CN109560119B (en) * | 2017-09-25 | 2021-11-16 | 新唐科技股份有限公司 | High voltage semiconductor element |
| CN109524474A (en) * | 2018-11-08 | 2019-03-26 | 西安电子科技大学 | The 4H-SiC metal-semiconductor field effect transistor being lightly doped with grid edge leakage side section |
| CN109524474B (en) * | 2018-11-08 | 2021-06-25 | 西安电子科技大学 | 4H-SiC metal semiconductor field effect transistor with gate edge drain side part light doping |
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| CN104465773B (en) | 2018-01-19 |
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