CN105789287A - Field cut-off insulating gate bipolar transistor and preparation method therefor - Google Patents
Field cut-off insulating gate bipolar transistor and preparation method therefor Download PDFInfo
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- CN105789287A CN105789287A CN201410828072.5A CN201410828072A CN105789287A CN 105789287 A CN105789287 A CN 105789287A CN 201410828072 A CN201410828072 A CN 201410828072A CN 105789287 A CN105789287 A CN 105789287A
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Abstract
The invention relates to a preparation method for a field cut-off insulating gate bipolar transistor. The preparation method comprises the steps of providing a P type substrate; forming an N type field cut-off layer on the P type substrate in an epitaxy manner; forming an N type drifting region adopting a structure including at least two layers on the field cut-off layer in an epitaxy manner, wherein for the layer, which is closer to the field-cut-off layer, in the drifting region, the N type impurity concentration becomes lower and the resistivity becomes higher; forming a front surface structure of the field cut-off insulating gate bipolar transistor; performing thinning processing on the back surface of the P type substrate; and performing metalizing processing on the back surface of the field cut-off insulating gate bipolar transistor. The invention also relates to the field cut-off insulating gate bipolar transistor. According to the preparation method, the drifting region is prepared in the epitaxy manner by more than two times, so that the electric field distribution can be optimized and the breakdown voltage of the device can be increased under the same epitaxy thickness; in other words, on the basis of achieving the same breakdown voltage, the epitaxial layer thickness of the device can be effectively lowered; therefore, the cost can be lowered on one hand; and on the other hand, the turn-off loss and thermal resistance of the device can be lowered, and the performance of the device can be improved.
Description
Technical field
The present invention relates to technical field of semiconductor preparation, particularly relate to a kind of field cut-off igbt, the preparation method further relating to a kind of cut-off igbt.
Background technology
Since the nineties in last century, development through device and fabricating technology, igbt (IGBT) makes and has stepped into maturation, business-like IGBT voltage range contains from 370V to 6500V at present, from 2A to 4000A not etc., form includes single tube and module to electric current.Dividing by device architecture, IGBT experienced by PT (punch), NPT (non-punch) and FS (field cut-off type) three class formations on substrate.
The Facad structure that the preparation method of a kind of traditional field cut-off igbt (FS-IGBT) device adopts epitaxy technique to prepare device after forming drift region on drift region.But so typically require the epitaxial layer that growth is thicker, cause that manufacturing cost is higher.
Summary of the invention
Based on this, it is necessary to the preparation method providing a kind of field cut-off igbt that can reduce manufacturing cost.
A kind of preparation method of cut-off igbt, including: P type substrate is provided；Described P type substrate is epitaxially formed the field cutoff layer of N-type；By being epitaxially formed at least two-layer N-type drift region on the cutoff layer of described field, in drift region, its N-type impurity concentration is more low, resistivity is more high the closer to one layer of described field cutoff layer；Form the Facad structure of described field cut-off igbt；Described P type substrate is carried out thinning back side process；Igbt is ended in described field and carries out back face metalization process.
Wherein in an embodiment, by being epitaxially formed in the step of at least two-layer N-type drift region on described cutoff layer on the scene, it is form 2 layers of drift region, including the first drift region near described field cutoff layer and the second drift region away from described field cutoff layer.
Wherein in an embodiment, described field cutoff layer is N+ field cutoff layer, and described first drift region is N-drift region.
Wherein in an embodiment, by being epitaxially formed in the step of at least two-layer N-type drift region on described cutoff layer on the scene, it is form 3 layers of drift region.
Wherein in an embodiment, in the step of described offer P type substrate, the resistivity of P type substrate is less than 0.3 Ω * cm, and p type impurity concentration is more than 1*1016cm-3；Described P type substrate is carrying out after the step of thinning back side process directly as colelctor electrode.
Wherein in an embodiment, also include in described P type substrate implanting p-type impurity the step being annealed after the described step that P type substrate is carried out thinning back side process, to reduce collector contact resistance.
Wherein in an embodiment, described in implanting p-type impurity in P type substrate the step that is annealed, annealing temperature is not more than 450 degrees Celsius.
There is a need to provide a kind of field cut-off igbt.
A kind of field cut-off igbt, including the N-type field cutoff layer on the P type colelctor electrode on collector electrode metal electrode, described collector electrode metal electrode, described P type colelctor electrode and the Facad structure on the cutoff layer of described N-type field, described Facad structure includes N-type drift region, described drift region is the structure of at least two-layer, and in drift region, its N-type impurity concentration is more low, resistivity is more high the closer to one layer of described field cutoff layer.
Wherein in an embodiment, described drift region is double-layer structure, and including the first drift region near described field cutoff layer and the second drift region away from described field cutoff layer, described field cutoff layer is N+ field cutoff layer, and described first drift region is N-drift region.
Wherein in an embodiment, described drift region is three-decker.
The preparation method of above-mentioned field cut-off igbt, adopts the extension of more than twice to prepare drift region, in identical epitaxial thickness situation, it is possible to optimize Electric Field Distribution, increases device electric breakdown strength.It is to say, on the basis reaching same breakdown voltage, it is possible to it is effectively reduced the epitaxy layer thickness of device, reduces cost on the one hand, turn-off power loss and the thermal resistance of device, boost device performance can be reduced on the one hand.The field cutoff layer of above-mentioned field cut-off igbt adopts epitaxy technique to prepare equally, the impurity of device back surface field cutoff layer is without using laser annealing to activate, reduce the technical process requirement to equipment, can also avoid using completely wafer processes technique, completely compatible with existing DMOS technique, overcoming the deficiencies in the prior art, technique is simple, efficiency is high, greatly reduce process costs.Meanwhile, this technical process can be passed through extension and adjust thickness and the CONCENTRATION DISTRIBUTION of field cutoff layer, controls the injection efficiency of P+ colelctor electrode, the IGBT device more superior to obtain performance by controlling thinning back side degree.
Accompanying drawing explanation
By being more particularly described of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other purpose, feature and the advantage of the present invention will become more fully apparent.The part that accompanying drawing labelling instruction identical in whole accompanying drawings is identical, and deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, it is preferred that emphasis is the purport of the present invention is shown.
Fig. 1 is the flow chart of the preparation method of an embodiment midfield cut-off igbt；
Fig. 2 a～Fig. 2 d is the field cut-off igbt sectional view in preparation process adopting the preparation method of field cut-off igbt to prepare in an embodiment.
Detailed description of the invention
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully.Accompanying drawing gives the first-selected embodiment of the present invention.But, the present invention can realize in many different forms, however it is not limited to embodiment described herein.On the contrary, the purpose providing these embodiments is to make to the disclosure more thoroughly comprehensively.
It should be noted that be referred to as " being fixed on " another element when element, it can directly on another element or can also there is element placed in the middle.When an element is considered as " connection " another element, it can be directly to another element or may be simultaneously present centering elements.Term as used herein " vertical ", " level ", " on ", D score, "left", "right" and similar statement for illustrative purposes only.
Unless otherwise defined, all of technology used herein is identical with the implication that the those skilled in the art belonging to the present invention are generally understood that with scientific terminology.The term used in the description of the invention herein is intended merely to the purpose describing specific embodiment, it is not intended that in the restriction present invention.Term as used herein " and/or " include the arbitrary and all of combination of one or more relevant Listed Items.
Fig. 1 is the flow chart of the preparation method of an embodiment midfield cut-off igbt, comprises the following steps:
S110, it is provided that P type substrate.
The material of substrate 10 can be the one in silicon, carborundum, GaAs or gallium nitride.In the present embodiment, substrate 10 is P type FZ substrate.
S120, is epitaxially formed the field cutoff layer of N-type in P type substrate.
Owing to substrate 10 surface before use is likely to partial oxidation, therefore can first remove the oxide layer on substrate 10 surface before extension field cutoff layer 20.Fig. 2 a is the generalized section of device after step S120 completes.
S130, by being epitaxially formed at least two-layer N-type drift region on cutoff layer on the scene.
Control the concentration of each layer drift region so that drift region N-type impurity concentration is more low, resistivity is more high the closer to a layer of field cutoff layer 20.As shown in Figure 2 b, it is form two-layer drift region in the present embodiment, including the first drift region 32 near field cutoff layer 20 and the second drift region 34 away from field cutoff layer 20.
S140, forms the Facad structure of field cut-off igbt.
Fig. 2 b is the generalized section of device after step S140 completes, in the present embodiment, field cut-off igbt is plane (Planar) gate field cut-off igbt, it is possible to the front technique ending igbt with the planar gate field that those skilled in the art are known prepares its Facad structure.With reference to Fig. 2 b, step S140 complete after the device P Xing Ti district 41 that includes in the second drift region 34, the emitter stage 42 of the N+ type in P Xing Ti district 41, the gate oxide 43 of the second surface, drift region 34, polysilicon gate 44 above gate oxide 43, cover the medium of oxides layer 45 of gate oxide 43 and polysilicon gate 44, and covering device surface, metal electrode 46 as emitter stage.In other examples, cut-off igbt in field can also be groove (Trench) gate field cut-off igbt.
S150, carries out thinning back side process to P type substrate.
Carrying out thinning to the back side of substrate 10, thinning thickness can change according to design requirement.Fig. 2 c has been the generalized section of device after step S150.In the present embodiment, substrate 10 selects resistivity less than 0.3 Ω cm, and p type impurity concentration is more than 1*16cm-3P type FZ substrate.After reduction processing, before back face metalization, it is not necessary to substrate implanting p-type impurity and anneal to reduce back metal contacts resistance, it is possible to direct using substrate 10 as colelctor electrode.In other embodiments, the relatively low P type substrate of impurity concentration can also be adopted as substrate 10, in this case also need to carry out in substrate 10 implanting p-type impurity the step being annealed after step S150, before step S160, to reduce collector contact resistance.In order to avoid high temperature affects the metal formed in Facad structure during annealing, the temperature in annealing process should be not more than 450 degrees Celsius.
S160, ends igbt to field and carries out back face metalization process.
The mode that can adopt sputtering or evaporation prepares the back metal colelctor electrode 50 of field cut-off igbt, finally gives field cut-off igbt, as shown in Figure 2 d.Specifically, cut-off igbt in field includes the N-type field cutoff layer 20 on P type colelctor electrode on collector electrode metal electrode 50, collector electrode metal electrode 50 (namely thinning after substrate 10), P type colelctor electrode and the Facad structure on N-type field cutoff layer 20.
The preparation method of above-mentioned field cut-off igbt, adopts the extension of more than twice to prepare drift region, in identical epitaxial thickness situation, it is possible to optimize Electric Field Distribution, increases device electric breakdown strength.It is to say, on the basis reaching same breakdown voltage, it is possible to it is effectively reduced the epitaxy layer thickness of device, reduces cost on the one hand, turn-off power loss and the thermal resistance of device, boost device performance can be reduced on the one hand.Field cutoff layer 20 adopts epitaxy technique to prepare equally, the impurity of device back surface field cutoff layer 20 is without using laser annealing to activate, reduce the technical process requirement to equipment, can also avoid using completely wafer processes technique, completely compatible with existing DMOS technique, overcoming the deficiencies in the prior art, technique is simple, efficiency is high, greatly reduce process costs.Meanwhile, this technical process can be passed through extension and adjust thickness and the CONCENTRATION DISTRIBUTION of field cutoff layer 20, controls the injection efficiency of P+ colelctor electrode, the IGBT device more superior to obtain performance by controlling thinning back side degree.
In the aforementioned embodiment, field cutoff layer 20 is N+Buffer, and the first drift region 32 is N-Drift, and the second drift region 34 is NDrift.
In step s 130, suitably increasing extension number of times, every extension one layer relatively preceding layer increases impurity concentration, reduces resistivity, it is possible to boost device performance further, but relative extension cost also can increase.Comprehensive consideration, is advisable with 2～3 layers of extension in drift region.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to making some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a preparation method for field cut-off igbt, including:
P type substrate is provided；
Described P type substrate is epitaxially formed the field cutoff layer of N-type；
By being epitaxially formed at least two-layer N-type drift region on the cutoff layer of described field, in drift region, its N-type impurity concentration is more low, resistivity is more high the closer to one layer of described field cutoff layer；
Form the Facad structure of described field cut-off igbt；
Described P type substrate is carried out thinning back side process；
Igbt is ended in described field and carries out back face metalization process.
2. the preparation method of field according to claim 1 cut-off igbt, it is characterized in that, by being epitaxially formed in the step of at least two-layer N-type drift region on described cutoff layer on the scene, it is form 2 layers of drift region, including the first drift region near described field cutoff layer and the second drift region away from described field cutoff layer.
3. the preparation method of field according to claim 2 cut-off igbt, it is characterised in that described field cutoff layer is N+ field cutoff layer, and described first drift region is N-drift region.
4. the preparation method of field according to claim 1 cut-off igbt, it is characterised in that by being epitaxially formed in the step of at least two-layer N-type drift region on described cutoff layer on the scene, is form 3 layers of drift region.
5. the preparation method of field according to claim 1 cut-off igbt, it is characterised in that in the step of described offer P type substrate, the resistivity of P type substrate is less than 0.3 Ω * cm, and p type impurity concentration is more than 1*1016cm-3；Described P type substrate is carrying out after the step of thinning back side process directly as colelctor electrode.
6. the preparation method of field according to claim 1 cut-off igbt, it is characterized in that, in described P type substrate implanting p-type impurity the step being annealed also is included, to reduce collector contact resistance after the described step that P type substrate is carried out thinning back side process.
7. the preparation method of field according to claim 6 cut-off igbt, it is characterised in that described in implanting p-type impurity in P type substrate the step that is annealed, annealing temperature is not more than 450 degrees Celsius.
8. a field cut-off igbt, including the N-type field cutoff layer on the P type colelctor electrode on collector electrode metal electrode, described collector electrode metal electrode, described P type colelctor electrode and the Facad structure on the cutoff layer of described N-type field, it is characterized in that, described Facad structure includes N-type drift region, described drift region is the structure of at least two-layer, and in drift region, its N-type impurity concentration is more low, resistivity is more high the closer to one layer of described field cutoff layer.
9. field according to claim 8 cut-off igbt, it is characterized in that, described drift region is double-layer structure, including the first drift region near described field cutoff layer and the second drift region away from described field cutoff layer, described field cutoff layer is N+ field cutoff layer, and described first drift region is N-drift region.
10. field according to claim 8 cut-off igbt, it is characterised in that described drift region is three-decker.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108258029A (en) * | 2016-12-29 | 2018-07-06 | 无锡华润华晶微电子有限公司 | Igbt and preparation method thereof |
| CN109243975A (en) * | 2017-07-10 | 2019-01-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN113497132A (en) * | 2020-04-07 | 2021-10-12 | 苏州华太电子技术有限公司 | Super junction insulated gate bipolar transistor and manufacturing method thereof |
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| EP0746040A1 (en) * | 1995-05-31 | 1996-12-04 | Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Improved IGBT device |
| US20090032912A1 (en) * | 2007-06-20 | 2009-02-05 | Semikron Elektronik Gmbh & Co. Kg | Semiconductor component with buffer layer |
| JP2010171057A (en) * | 2009-01-20 | 2010-08-05 | Denso Corp | Semiconductor device, and method of manufacturing the same |
| CN101976683A (en) * | 2010-09-25 | 2011-02-16 | 浙江大学 | Insulated gate bipolar transistor and manufacturing method thereof |
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| JPH0529628A (en) * | 1991-07-19 | 1993-02-05 | Fuji Electric Co Ltd | Insulating-gate type bipolar transistor |
| EP0746040A1 (en) * | 1995-05-31 | 1996-12-04 | Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Improved IGBT device |
| US20090032912A1 (en) * | 2007-06-20 | 2009-02-05 | Semikron Elektronik Gmbh & Co. Kg | Semiconductor component with buffer layer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108258029A (en) * | 2016-12-29 | 2018-07-06 | 无锡华润华晶微电子有限公司 | Igbt and preparation method thereof |
| CN108258029B (en) * | 2016-12-29 | 2020-06-23 | 无锡华润华晶微电子有限公司 | Reverse conducting insulated gate bipolar transistor and preparation method thereof |
| CN109243975A (en) * | 2017-07-10 | 2019-01-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN113497132A (en) * | 2020-04-07 | 2021-10-12 | 苏州华太电子技术有限公司 | Super junction insulated gate bipolar transistor and manufacturing method thereof |
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