CN108257859B - Preparation method of gate oxide layer and MOSFET power device - Google Patents
Preparation method of gate oxide layer and MOSFET power device Download PDFInfo
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- CN108257859B CN108257859B CN201611238004.9A CN201611238004A CN108257859B CN 108257859 B CN108257859 B CN 108257859B CN 201611238004 A CN201611238004 A CN 201611238004A CN 108257859 B CN108257859 B CN 108257859B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/783—Field effect transistors with field effect produced by an insulated gate comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET
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Abstract
The invention provides a preparation method of a gate oxide layer and a MOSFET power device, wherein the preparation method comprises the steps of carrying out high-temperature sacrificial oxidation on a silicon carbide epitaxial wafer with a first conductive type, and forming a sacrificial oxide layer on the upper surface of the epitaxial layer; corroding the sacrificial oxide layer until the sacrificial oxide layer on the epitaxial layer is completely removed; performing high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed to form a smooth passivated surface; and sequentially carrying out high-temperature dry oxygen oxidation and annealing under a phosphorus atmosphere on the silicon carbide epitaxial wafer to form a gate oxide layer on the smooth passivated surface. Compared with the prior art, the preparation method of the gate oxide layer and the MOSFET power device provided by the invention can reduce SiC/SiO2Interface defects at the interface due to impurities and/or surface lattice defects.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a preparation method of a gate oxide layer and a MOSFET power device.
Background
The silicon carbide semiconductor material has wider forbidden band width (3.2eV), higher breakdown electric field intensity (2.2MV/cm) and higher high saturated electron migration rate (2.0 multiplied by 10)7cm/s), higher high thermal conductivity (5.0W/cm K), excellent physical and chemical stability, etc., and is suitable for manufacturing high-power, high-voltage, high-working-temperature, high-working-frequency power semiconductor devices, while silicon carbide is the only compound semiconductor material with the characteristic of generating dense SiO by oxidation2The capability of the dielectric layer enables the silicon carbide process to have higher process compatibility and maturity with the conventional CMOS process, and enables the silicon carbide MOSFET power device to be manufactured with a more mature manufacturing process.
A mosfet is a widely used type of power device that provides a control signal to a gate electrode that separates the semiconductor surfaces by an intervening insulator, which may be silicon dioxide (SiO)2). The current conduction is performed by the transport of majority carriers without the need for minority carrier injection when the bipolar transistor is in operation. Meanwhile, the silicon carbide MOSFET power device can provide a very large safe operating area, and a plurality of unit structures can be used in parallel.
However, silicon carbide power MOSFET devices due to the gate dielectric (SiO)2) Interface quality problem of/channel (SiC): SiO 22High density of interface states are typically present at the/SiC interface, resulting in silicon carbide MOSFET power devices with varying degrees of performance, stability and reliability. It is generally believed that this problem arises due to oxidationC residues generated during the process, which are usually present in the form of C dangling bonds and C clusters. Thus, how to reduce the appearance of C residues and how to make C dangling bonds and C clusters disappear or passivated after oxidation during oxidation is to improve SiO2The quality of the SiC interface and the performance, stability and reliability of the silicon carbide MOSFET power device. 200610126666.7 discloses a method for improving the channel mobility by improving the dangling bond termination at the interface between the gate dielectric layer and the channel region by annealing in hydrogen or a humid atmosphere, but this method has the disadvantage of causing unnecessary oxidation of the gate contact.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a preparation method of a gate oxide layer and a MOSFET power device.
In a first aspect, the technical scheme of the method for preparing the gate oxide layer is as follows:
the preparation method comprises the following steps:
performing high-temperature sacrificial oxidation on a silicon carbide epitaxial wafer with a first conduction type to form a sacrificial oxide layer on the upper surface of an epitaxial layer;
corroding the sacrificial oxide layer until the sacrificial oxide layer on the epitaxial layer is completely removed;
performing high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed to form a smooth passivated surface;
and sequentially carrying out high-temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing on the silicon carbide epitaxial wafer to form a gate oxide layer on the smooth passivated surface.
In a second aspect, a technical solution of the MOSFET power device in the present invention is:
the MOSFET power device comprises:
the epitaxial silicon carbide wafer comprises a silicon carbide substrate and an epitaxial layer, wherein the silicon carbide substrate and the epitaxial layer are both provided with a first conduction type; wherein: the upper surface of the epitaxial layer is a smooth passivated surface formed after the high-temperature surfacing treatment is carried out on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed;
a gate oxide layer disposed on the smooth passivated surface; wherein: the gate oxide layer is formed by sequentially carrying out high-temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing on the silicon carbide epitaxial wafer.
Compared with the closest prior art, the invention has the beneficial effects that:
1. the preparation method of the gate oxide layer provided by the invention has the advantages that after the silicon carbide epitaxial wafer is subjected to high-temperature sacrificial oxidation to form the sacrificial oxide layer, the sacrificial oxide layer is completely corroded and removed, the lattice damage and organic, metal and nonmetal contamination on the surface and near the surface of the silicon carbide epitaxial wafer can be eliminated, the impurity content in the silicon carbide epitaxial wafer oxide layer and the SiC/SiO2Interface defects (interface states) at the interface due to impurities and/or surface lattice defects; the high-temperature surface treatment of the silicon carbide epitaxial wafer is beneficial to reducing SiC/SiO2Interface defects (interface states) caused by surface roughness at the interface improve the mobility of a carrier channel; the high-temperature dry oxygen-wet oxygen-dry oxygen oxidation of the silicon carbide epitaxial wafer can form compact and reliable SiO on the silicon carbide epitaxial wafer2An oxide film; annealing the silicon carbide epitaxial wafer in a phosphorus atmosphere can help to decompose or passivate C dangling bonds and C clusters formed by C residues and reduce SiC/SiO2Interface defects at the interface;
2. according to the MOSFET power device provided by the invention, the epitaxial layer of the silicon carbide epitaxial wafer is provided with a smooth passivated surface, the passivated surface is formed by carrying out high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed, the removal of the sacrificial oxide layer can eliminate lattice damage and organic, metal and nonmetal contamination on the surface and near surface of the silicon carbide epitaxial wafer, and is beneficial to reducing the impurity content in the oxide layer of the silicon carbide epitaxial wafer and SiC/SiO2Interface defects (interface states) at the interface due to impurities and/or surface lattice defects, while the high temperature surfacing process helps to reduce SiC/SiO2Interface defects (interface states) at the interface due to surface roughness, and increased loading(ii) a runner channel mobility; the gate oxide layer is formed by sequentially carrying out high-temperature dry oxygen oxidation and annealing under the phosphorus atmosphere on the silicon carbide epitaxial wafer, and the high-temperature dry oxygen-wet oxygen-dry oxygen oxidation can form compact and reliable SiO on the silicon carbide epitaxial wafer2The oxide film, while annealing in a phosphorus atmosphere, can help to decompose or passivate C dangling bonds and C clusters formed by C residues, reducing SiC/SiO2Interface defects at the interface.
Drawings
FIG. 1: the invention discloses a preparation method of a gate oxide layer, which comprises the following steps of implementing a flow chart;
FIG. 2: the structure of the silicon carbide epitaxial wafer in the embodiment of the invention is shown schematically;
FIG. 3: in the embodiment of the invention, the well region, the source electrode contact region and the base electrode contact region of the silicon carbide epitaxial wafer are schematically illustrated;
FIG. 4: the schematic diagram of the sacrificial oxide layer of the silicon carbide epitaxial wafer in the embodiment of the invention;
FIG. 5: the passivation surface of a silicon carbide epitaxial wafer in the embodiment of the invention is schematically shown;
FIG. 6: the schematic diagram of the gate oxide layer of the silicon carbide epitaxial wafer in the embodiment of the invention;
FIG. 7: a schematic structural view of another silicon carbide epitaxial wafer according to an embodiment of the present invention;
FIG. 8: another schematic diagram of a base contact region and a trench region of a silicon carbide epitaxial wafer in an embodiment of the invention;
FIG. 9: the schematic diagram of the sacrificial oxide layer of another silicon carbide epitaxial wafer in the embodiment of the invention;
FIG. 10: a schematic view of a passivated surface of another silicon carbide epitaxial wafer in an embodiment of the invention;
FIG. 11: the schematic diagram of the gate oxide layer of another silicon carbide epitaxial wafer in the embodiment of the invention;
FIG. 12: the structure of another silicon carbide epitaxial wafer in the embodiment of the invention is shown schematically;
FIG. 13: in another embodiment of the present invention, a well region, a source contact region and a base contact region of a silicon carbide epitaxial wafer are schematically illustrated;
FIG. 14: in another embodiment of the present invention, a schematic diagram of a sacrificial oxide layer of a silicon carbide epitaxial wafer is provided;
FIG. 15: a schematic view of a passivated surface of another silicon carbide epitaxial wafer according to an embodiment of the present invention;
FIG. 16: the gate oxide layer of another silicon carbide epitaxial wafer in the embodiment of the invention is shown schematically;
wherein, 101: an n-type silicon carbide substrate; 102: an n-type silicon carbide epitaxial layer; 110: an n-type silicon carbide epitaxial wafer; 111: a p-type well region; 112: an n-type source contact region; 113: a p-type base contact region; 121: sacrificing the oxide layer; 131: passivating the surface; 141: a gate oxide layer; 201: an n-type silicon carbide substrate; 202: an n-type silicon carbide epitaxial layer; 203: a p-type silicon carbide epitaxial layer; 204: an n-type silicon carbide epitaxial layer; 210: an n-type silicon carbide epitaxial wafer; 211: a p-type base contact region; 212: a trench region; 221: sacrificing the oxide layer; 231: passivating the surface; 301: a semi-insulating silicon carbide substrate; 302: an n-type silicon carbide epitaxial layer; 310: an n-type silicon carbide epitaxial wafer; 312: an n-type source contact region; 313: a p-type base contact region; 321: sacrificing the oxide layer; 331: passivating the surface; 341: and (4) a gate oxide layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following describes a method for manufacturing a gate oxide layer according to an embodiment of the present invention with reference to the accompanying drawings.
In this embodiment, the gate oxide layer may be prepared according to the following steps:
step S101: and carrying out high-temperature sacrificial oxidation on the silicon carbide epitaxial wafer with the first conductivity type to form a sacrificial oxide layer on the upper surface of the epitaxial layer.
Step S102: and etching the sacrificial oxide layer until the sacrificial oxide layer on the epitaxial layer is completely removed.
Step S103: and carrying out high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed to form a smooth passivated surface.
Step S104: and sequentially carrying out high-temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing on the silicon carbide epitaxial wafer to form a gate oxide layer on the smooth passivated surface.
In this embodiment, after the silicon carbide epitaxial wafer is subjected to high-temperature sacrificial oxidation to form the sacrificial oxide layer, the sacrificial oxide layer is completely corroded and removed, so that lattice damage and organic, metal and nonmetal contamination on the surface and near the surface of the silicon carbide epitaxial wafer can be eliminated, and the reduction of impurity content in the silicon carbide epitaxial wafer oxide layer and the reduction of SiC/SiO2Interface defects (interface states) at the interface due to impurities and/or surface lattice defects; the high-temperature surface treatment of the silicon carbide epitaxial wafer is beneficial to reducing SiC/SiO2Interface defects (interface states) caused by surface roughness at the interface improve the mobility of a carrier channel; the high-temperature dry oxygen-wet oxygen-dry oxygen oxidation of the silicon carbide epitaxial wafer can form compact and reliable SiO on the silicon carbide epitaxial wafer2An oxide film; annealing the silicon carbide epitaxial wafer in a phosphorus atmosphere can help to decompose or passivate C dangling bonds and C clusters formed by C residues and reduce SiC/SiO2Interface defects at the interface.
Further, step S101 in this embodiment may further include the following steps, specifically:
1. an epitaxial layer having a first conductivity type is formed on a front surface of the silicon carbide epitaxial wafer.
2. And after the silicon carbide epitaxial wafer is cleaned, ions are implanted into the epitaxial layer to form a well region. Wherein: in this embodiment, the cleaning step is to sequentially perform Piranha process cleaning, RCA process cleaning, and DHF process cleaning on the silicon carbide epitaxial wafer.
3. And implanting ions into the well region to form a source contact region and a base contact region respectively, and annealing the silicon carbide epitaxial wafer under the protective mask and inert gas environment. Wherein: the annealing temperature is 1500-2100 ℃, and the annealing time is 10-30 min.
4. And cleaning the annealed silicon carbide epitaxial wafer. Wherein: in this embodiment, the cleaning step is to sequentially perform Piranha process cleaning, RCA process cleaning, and DHF process cleaning on the silicon carbide epitaxial wafer.
5. The high-temperature sacrificial oxidation is carried out on the silicon carbide epitaxial wafer, and the method specifically comprises the following steps: by using a box furnace or a tube furnace in oxygen O2And (3) carrying out high-temperature sacrificial oxidation on the silicon carbide epitaxial wafer in the environment. Wherein: the oxidation temperature of the high-temperature sacrificial oxidation is 1200-1500 ℃, the oxidation time is 10-30 min, and oxygen O2Has a purity of 6N, oxygen O2The flow rate of (2) is 0.1 to 10 slm.
Further, step S101 in this embodiment may further include the following steps, specifically:
1. and sequentially forming a first epitaxial layer with a first conductivity type, a second epitaxial layer with a second conductivity type and a third epitaxial layer with the first conductivity type on the front surface of the silicon carbide epitaxial wafer from bottom to top.
2. And after the silicon carbide epitaxial wafer is cleaned, ions are injected into the third epitaxial layer to form a base contact region. Wherein: in this embodiment, the cleaning step is to sequentially perform Piranha process cleaning, RCA process cleaning, and DHF process cleaning on the silicon carbide epitaxial wafer.
3. And annealing the silicon carbide epitaxial wafer under the protective mask and inert gas environment. Wherein: the annealing temperature is 1500-2100 ℃, and the annealing time is 10-30 min.
4. And etching the first epitaxial layer, the second epitaxial layer and the third epitaxial layer to form a groove region. Wherein: the trench region penetrates through the first epitaxial layer and the second epitaxial layer, and the depth of the trench region is smaller than the sum of the junction depths of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer. In this embodiment, an ICP plasma etching method based on an F-based gas or a Cl-based gas may be employed, wherein the mask is a silicon oxide mask.
5. And cleaning the silicon carbide epitaxial wafer after the groove region is formed. Wherein: in this embodiment, the cleaning step is to sequentially perform Piranha process cleaning, RCA process cleaning, and DHF process cleaning on the silicon carbide epitaxial wafer.
6. The high-temperature sacrificial oxidation is carried out on the silicon carbide epitaxial wafer, and the method specifically comprises the following steps: by using a box furnace or a tube furnace in oxygen O2And (3) carrying out high-temperature sacrificial oxidation on the silicon carbide epitaxial wafer in the environment. Wherein: the oxidation temperature of the high-temperature sacrificial oxidation is 1200-1500 ℃, the oxidation time is 10-30 min, and oxygen O2Has a purity of 6N, oxygen O2The flow rate of (2) is 0.1 to 10 slm.
Further, step S102 in this embodiment may further include the following steps, specifically: and corroding the sacrificial oxide layer by adopting wet corrosion at normal temperature. Wherein: the etching solution of the wet etching is BOE etching solution or DHF solution with the concentration of 1-50%, and the BOE etching solution can adopt conventional BOE etching solution.
Further, step S103 in this embodiment may further include the following steps, specifically: and (3) carrying out high-temperature surface treatment on the upper surface of the epitaxial layer in a hydrogen chloride gas (HCL) environment by adopting a box furnace or a tube furnace. Wherein: the temperature of the high-temperature surface treatment is 1000-2000 ℃, the time is 0.1-4 h, the purity of the hydrogen chloride gas HCL is 6N, and the flow rate of the hydrogen chloride gas HCL is 0.1-10 slm.
Further, step S104 in this embodiment may further include the following steps, specifically:
1. carrying out high-temperature dry oxygen-wet oxygen-dry oxygen oxidation on the silicon carbide epitaxial wafer, which specifically comprises the following steps: sequentially carrying out high-temperature dry oxygen oxidation, high-temperature wet oxygen oxidation and high-temperature dry oxygen oxidation on the silicon carbide epitaxial wafer by adopting a box furnace or a tubular furnace; wherein: the ratio of the oxidation time of the high-temperature dry oxygen oxidation to the oxidation time of the high-temperature wet oxygen oxidation is 1: 100-1: 1, namely the ratio of the oxidation time of the first high-temperature dry oxygen oxidation to the oxidation time of the high-temperature wet oxygen oxidation is 1: 100-1: 1, the ratio of the oxidation time of the second high-temperature dry oxygen oxidation to the oxidation time of the high-temperature wet oxygen oxidation is also 1: 100-1: 1.
(1) high-temperature dry oxygen oxidation is carried out on the silicon carbide epitaxial wafer
This embodiment can be carried out with oxygen O2Performing high-temperature dry oxygen oxidation on the silicon carbide epitaxial wafer under the environment, or performing high-temperature dry oxygen oxidation on the silicon carbide epitaxial wafer under the condition of laughing gas N2And (3) carrying out high-temperature dry oxygen oxidation on the silicon carbide epitaxial wafer in an O environment. Wherein: the oxidation temperature of the high-temperature dry oxygen oxidation is 1200-1500 ℃, and the oxygen O2And laughing gas N2The purity of O is 5N-6N, oxygen O2And laughing gas N2The flow rate of O is 0.1-10 slm.
(2) High-temperature wet oxygen oxidation is carried out on the silicon carbide epitaxial wafer
This embodiment can be used for the water vapor H2Carrying out high-temperature wet oxygen oxidation on the silicon carbide epitaxial wafer in an O environment; wherein: the oxidation temperature of the high-temperature wet oxygen oxidation is 1200-1500 ℃, and the steam H2Purity of O is 5N-6N, and steam H2The flow rate of O is 0.1-10 slm.
2. Carrying out nitridation annealing on the silicon carbide epitaxial wafer, which specifically comprises the following steps:
the embodiment can adopt a box type furnace or a tube type furnace to process nitric oxide NO or nitrous oxide N2And annealing the silicon carbide epitaxial wafer in an O environment. Wherein: nitric oxide NO and nitrous oxide N2The purity of O is 6N, and the flow rate is 0.1-10 slm; the annealing temperature is the same as the high-temperature dry oxygen-wet oxygen-dry oxygen oxidation temperature, or the temperature is 1000-1300 ℃; the annealing time is 0.1-4 h.
Based on the above preparation method, the present invention further provides three embodiments of gate oxide preparation methods, and each embodiment is described below with reference to the accompanying drawings.
Example 1
Step S201: preparation of silicon carbide epitaxial wafer
Fig. 2 is a schematic structural diagram of a silicon carbide epitaxial wafer in an embodiment of the present invention, and as shown in the drawing, the silicon carbide epitaxial wafer 110 in this embodiment includes an n-type silicon carbide substrate 101 and an n-type silicon carbide epitaxial layer 102.
Step S202: preparing well region, source contact region and base contact region
Fig. 3 is a schematic diagram of a well region, a source contact region and a base contact region of a silicon carbide epitaxial wafer according to an embodiment of the present invention, in which p-type ions are doped into an n-type silicon carbide epitaxial layer 102 to form a p-type well region 111, and p-type ions and n-type ions are doped into the p-type well region 111 to form an n-type source contact region 112 and a p-type base contact region 113, respectively.
Step S203: preparation of sacrificial oxide layer
Fig. 4 is a schematic view of a sacrificial oxide layer of a silicon carbide epitaxial wafer according to an embodiment of the present invention, wherein in this embodiment, a high temperature sacrificial oxidation is performed on a silicon carbide epitaxial wafer 110 to form a sacrificial oxide layer 121 on an n-type silicon carbide epitaxial layer 102.
Step S204: preparation of passivated surfaces
Fig. 5 is a schematic view of a passivated surface of a silicon carbide epitaxial wafer according to an embodiment of the invention, in which the sacrificial oxide layer 121 is etched until the sacrificial oxide layer 121 is completely removed. The upper surface of epitaxial layer 102 after removal of sacrificial oxide layer 121 is then subjected to a high temperature surfacing process to form a smooth passivated surface 131.
Step S205: preparation of gate oxide
Fig. 6 is a schematic diagram of a gate oxide layer of a silicon carbide epitaxial wafer according to an embodiment of the present invention, in which a high temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing are sequentially performed on a silicon carbide epitaxial wafer 110 to form a gate oxide layer 141 on a smooth passivated surface 131.
Example 2
Step S301: preparation of silicon carbide epitaxial wafer
Fig. 7 is a schematic structural diagram of another silicon carbide epitaxial wafer in this embodiment of the present invention, and as shown in the drawing, the silicon carbide epitaxial wafer 210 in this embodiment includes an n-type silicon carbide substrate 201, an n-type silicon carbide epitaxial layer 202, a p-type silicon carbide epitaxial layer 203, and an n-type silicon carbide epitaxial layer 204.
Step S302: preparing base contact region and trench region
Fig. 8 is a schematic view of a base contact region and a trench region of another silicon carbide epitaxial wafer according to an embodiment of the present invention, where p-type ions are doped into the n-type silicon carbide epitaxial layer 204 to form a base contact region 211, and the n-type silicon carbide epitaxial layer 202, the p-type silicon carbide epitaxial layer 203, and the n-type silicon carbide epitaxial layer 204 are etched to form a trench region 212 in this embodiment.
Step S303: preparation of sacrificial oxide layer
Fig. 9 is a schematic view of a sacrificial oxide layer of another silicon carbide epitaxial wafer according to an embodiment of the present invention, in which a high-temperature sacrificial oxidation is performed on a silicon carbide epitaxial wafer 210 to form a sacrificial oxide layer 221 on the silicon carbide epitaxial wafer 210.
Step S304: preparation of passivated surfaces
Fig. 10 is a schematic view of a passivated surface of another silicon carbide epitaxial wafer according to an embodiment of the invention, in which the sacrificial oxide layer 221 is etched until the sacrificial oxide layer 221 is completely removed. The upper surface of the silicon carbide epitaxial wafer 210 after removal of the sacrificial oxide layer 221 is then subjected to a high temperature surfacing process to form a smooth passivated surface 231.
Step S305: preparation of gate oxide
Fig. 11 is a schematic diagram of a gate oxide layer of another silicon carbide epitaxial wafer in accordance with an embodiment of the present invention, wherein a high temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing are sequentially performed on a silicon carbide epitaxial wafer 210 to form a gate oxide layer 241 on a smooth passivation surface 231.
Example 3
Step S401: preparation of silicon carbide epitaxial wafer
Fig. 12 is a schematic structural diagram of another silicon carbide epitaxial wafer in this embodiment of the present invention, and as shown in the drawing, the silicon carbide epitaxial wafer 310 in this embodiment includes a semi-insulating silicon carbide substrate 301 and an n-type silicon carbide epitaxial layer 302.
Step S402: preparing well region, source contact region and base contact region
Fig. 13 is a schematic diagram of a well region, a source contact region and a base contact region of another sic epitaxial wafer according to an embodiment of the present invention, in which p-type ions are doped into an n-type sic epitaxial layer 302 to form a p-type well region 311, and p-type ions and n-type ions are doped into the p-type well region 311 to form an n-type source contact region 312 and a p-type base contact region 313, respectively.
Step S403: preparation of sacrificial oxide layer
Fig. 14 is a schematic view of a sacrificial oxide layer of another silicon carbide epitaxial wafer according to an embodiment of the present invention, wherein in this embodiment, a high temperature sacrificial oxidation is performed on a silicon carbide epitaxial wafer 310 to form a sacrificial oxide layer 321 on an n-type silicon carbide epitaxial layer 302.
Step S404: preparation of passivated surfaces
FIG. 15 is a schematic view of a passivated surface of another SiC epitaxial wafer in accordance with an embodiment of the invention, in which the sacrificial oxide 321 is etched until the sacrificial oxide 321 is completely removed. The upper surface of epitaxial layer 302 after sacrificial oxide layer 321 is removed is then subjected to a high temperature surfacing process to form a smooth passivated surface 331.
Step S405: preparation of gate oxide
Fig. 16 is a schematic diagram of a gate oxide layer of another silicon carbide epitaxial wafer in this embodiment of the present invention, and as shown in the figure, a high temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing are sequentially performed on the silicon carbide epitaxial wafer 310 to form a gate oxide layer 341 on the smooth passivation surface 331.
The invention also provides a MOSFET power device and provides a specific embodiment.
The MOSFET power device in the embodiment comprises a silicon carbide epitaxial wafer and a gate oxide layer.
Wherein: the silicon carbide epitaxial wafer comprises a silicon carbide substrate and an epitaxial layer which have the same conductivity type at the same time, and the epitaxial layer is arranged on the front surface of the silicon carbide substrate. In this embodiment, the upper surface of the epitaxial layer is a smooth passivated surface formed after the high-temperature surfacing treatment is performed on the upper surface of the epitaxial layer from which the sacrificial oxide layer is removed.
The gate oxide layer is disposed on the smooth passivated surface of the epitaxial layer. In this embodiment, the gate oxide layer is formed by sequentially performing high-temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing on a silicon carbide epitaxial wafer.
In this embodiment, the epitaxial layer of the SiC epitaxial wafer has a smooth passivated surface, the passivated surface is formed by performing high-temperature surfacing on the upper surface of the epitaxial layer after removing the sacrificial oxide layer, and removing the sacrificial oxide layer can eliminate lattice damage and contamination of organic, metal, and nonmetal on the surface and near the surface of the SiC epitaxial wafer, which helps to reduce the impurity content in the oxide layer of the SiC epitaxial wafer, and SiC/SiO2At the interfaceInterface defects (interface states) due to impurities and/or surface lattice defects, while high temperature surfacing helps to reduce SiC/SiO2Interface defects (interface states) caused by surface roughness at the interface improve the mobility of a carrier channel; the gate oxide layer is formed by sequentially carrying out high-temperature dry oxygen oxidation and annealing under the phosphorus atmosphere on the silicon carbide epitaxial wafer, and the high-temperature dry oxygen-wet oxygen-dry oxygen oxidation can form compact and reliable SiO on the silicon carbide epitaxial wafer2The oxide film, while annealing in a phosphorus atmosphere, can help to decompose or passivate C dangling bonds and C clusters formed by C residues, reducing SiC/SiO2Interface defects at the interface.
Further, in this embodiment, the silicon carbide substrate may be a silicon carbide substrate, specifically:
in the embodiment, the silicon carbide substrate is 4H-SiC or 6H-SiC, and the thickness of the silicon carbide substrate is 300-1000 μm or 10-400 μm. Meanwhile, the silicon carbide substrate can be a silicon carbide substrate heavily doped with nitrogen ions N or phosphorus ions P, and the resistivity is 0.001-0.1 omega cm. Alternatively, the silicon carbide substrate can also be a silicon carbide substrate doped with vanadium ions V or not doped with any ions and with a resistivity greater than 105Ω·cm。
Further, in this embodiment, the epitaxial layer may be the following epitaxial layer, specifically:
the epitaxial layer in this embodiment may comprise a silicon carbide epitaxial layer. Wherein: the silicon carbide epitaxial layer is 4H-SiC or 6H-SiC, and the thickness of the silicon carbide epitaxial layer is 1-300 mu m. Meanwhile, the silicon carbide epitaxial layer may be a silicon carbide epitaxial layer doped with nitrogen ions N or phosphorus ions P, and the doping concentration of the silicon carbide epitaxial layer is 1 × 1013～1×1016cm-3。
In this embodiment, the epitaxial layers may also include a first silicon carbide epitaxial layer, a second silicon carbide epitaxial layer, and a third silicon carbide epitaxial layer, which are sequentially disposed on the silicon carbide substrate from bottom to top. Wherein: the first silicon carbide epitaxial layer, the second silicon carbide epitaxial layer and the third silicon carbide epitaxial layer are all 4H-SiC or 6H-SiC. At the same time, the user can select the desired position,
the first silicon carbide epitaxial layer is doped with nitrogen ions N or phosphorusA silicon carbide epitaxial layer of ions P, the first silicon carbide epitaxial layer having a doping concentration of 1X 1013～1×1016cm-3The thickness is 1 to 300 μm.
The second silicon carbide epitaxial layer is a silicon carbide epitaxial layer doped with aluminum ions Al or boron ions B, and the doping concentration of the second silicon carbide epitaxial layer is 1 multiplied by 1015～1×1017cm-3The thickness is 0.1 to 10 μm.
The third silicon carbide epitaxial layer is doped with nitrogen ions N or phosphorus ions P and has a doping concentration of 1 × 1018～1×1021cm-3The thickness is 0.1 to 1 μm.
Further, the MOSFET power device in this embodiment may further include the following structure, specifically:
the MOSFET power device in the embodiment comprises a well region, a source contact region and a base contact region:
wherein: the well region is a well region of a second conductivity type disposed within the epitaxial layer of silicon carbide epitaxy comprising an epitaxial layer of silicon carbide. In this embodiment, the junction depth of the well region is 0.2-1.0 μm, the impurity ions are aluminum ions Al or boron ions B, and the concentration of the impurity ions is 1 × 1015～1×1017cm-3。
The source contact region is a contact region having the first conductivity type and disposed in the well region. In this embodiment, the junction depth of the source contact region is 0.1-0.5 μm, the impurity ions are Al ions or B ions, and the concentration of the impurity ions is 1 × 1019～1×1021cm-3。
The base contact region is a contact region having the second conductivity type disposed within the well region. In this embodiment, the junction depth of the base contact region is 0.1-0.5 μm, the impurity ions are nitrogen ions N or phosphorus ions P, and the concentration of the impurity ions is 1 × 1018～1×1021cm-3。
Further, the MOSFET power device in this embodiment may further include the following structure, specifically:
the MOSFET power device in the embodiment comprises a base contact region and a groove region:
wherein: the base contact region is a contact region of the second conductivity type which is disposed within the third silicon carbide epitaxial layer of the silicon carbide epitaxy comprising the three silicon carbide epitaxial layers described above. In this embodiment, the junction depth of the base contact region is 0.1-0.5 μm, the impurity ions are nitrogen ions N or phosphorus ions P, and the concentration of the impurity ions is 1 × 1018～1×1021cm-3。
The trench region penetrates through the first epitaxial layer and the second epitaxial layer, and the depth of the trench region is smaller than the sum of the junction depths of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer. In this embodiment, the depth of the trench penetrating into the third epitaxial layer is 0.1-1 μm.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (16)
1. A preparation method of a gate oxide layer is characterized by comprising the following steps:
performing high-temperature sacrificial oxidation on a silicon carbide epitaxial wafer with a first conduction type to form a sacrificial oxide layer on the upper surface of an epitaxial layer;
corroding the sacrificial oxide layer until the sacrificial oxide layer on the epitaxial layer is completely removed;
performing high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed to form a smooth passivated surface;
sequentially carrying out high-temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing on the silicon carbide epitaxial wafer to form a gate oxide layer on the smooth passivated surface;
the high-temperature surfacing treatment of the upper surface of the epitaxial layer comprises the following steps: carrying out high-temperature surface treatment on the upper surface of the epitaxial layer in a hydrogen chloride gas (HCL) environment by adopting a box furnace or a tube furnace;
wherein: the temperature of the high-temperature surface treatment is 1000-2000 ℃, the time is 0.1-4 h, the purity of hydrogen chloride gas (HCL) is 6N, and the flow of the hydrogen chloride gas (HCL) is 0.1-10 slm;
the high-temperature dry oxygen-wet oxygen-dry oxygen oxidation of the silicon carbide epitaxial wafer comprises the following steps: sequentially carrying out high-temperature dry oxygen oxidation, high-temperature wet oxygen oxidation and high-temperature dry oxygen oxidation on the silicon carbide epitaxial wafer by adopting a box furnace or a tubular furnace; wherein: the ratio of the oxidation time of the high-temperature dry oxygen oxidation to the oxidation time of the high-temperature wet oxygen oxidation is 1: 100-1: 1;
the high-temperature dry oxygen oxidation of the silicon carbide epitaxial wafer comprises the following steps: in oxygen O2Or laughing gas N2Carrying out high-temperature dry oxygen oxidation on the silicon carbide epitaxial wafer in an O environment; wherein: the oxidation temperature of the high-temperature dry oxygen oxidation is 1200-1500 ℃, and the oxygen O2And laughing gas N2The purity of O is 5N-6N, oxygen O2And laughing gas N2The flow rate of O is 0.1-10 slm;
the high-temperature wet oxygen oxidation of the silicon carbide epitaxial wafer comprises the following steps: in the presence of steam H2Carrying out high-temperature wet oxygen oxidation on the silicon carbide epitaxial wafer in an O environment; wherein: the oxidation temperature of the high-temperature wet oxygen oxidation is 1200-1500 ℃, and the steam H2Purity of O is 5N-6N, and steam H2The flow rate of O is 0.1-10 slm.
2. The method of claim 1 wherein said high temperature sacrificial oxidation of said epitaxial silicon carbide wafer is preceded by:
forming an epitaxial layer with a first conductivity type on the front surface of the silicon carbide epitaxial wafer;
after the silicon carbide epitaxial wafer is cleaned, injecting ions into the epitaxial layer to form a well region;
implanting ions into the well region to form a source contact region and a base contact region respectively;
and sequentially annealing and cleaning the silicon carbide epitaxial wafer after ion implantation.
3. The method of claim 1 wherein said high temperature sacrificial oxidation of said epitaxial silicon carbide wafer is preceded by:
sequentially forming a first epitaxial layer with a first conductivity type, a second epitaxial layer with a second conductivity type and a third epitaxial layer with the first conductivity type on the front surface of the silicon carbide epitaxial wafer from bottom to top;
after the silicon carbide epitaxial wafer is cleaned, injecting ions into the third epitaxial layer to form a base contact region;
sequentially annealing, etching and cleaning the silicon carbide epitaxial wafer after ion implantation;
wherein: the groove etching comprises etching the first epitaxial layer, the second epitaxial layer and the third epitaxial layer to form a groove region; the groove region penetrates through the third epitaxial layer and the second epitaxial layer, and the depth of the groove region is smaller than the sum of the junction depths of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer.
4. A method of forming a gate oxide layer as claimed in claim 2 or 3, wherein said cleaning of said silicon carbide epitaxial wafer comprises: and sequentially carrying out Piranha process cleaning, RCA process cleaning and DHF process cleaning on the silicon carbide epitaxial wafer.
5. A method of fabricating a gate oxide as claimed in claim 1,
the high-temperature sacrificial oxidation of the silicon carbide epitaxial wafer comprises the following steps: by using a box furnace or a tube furnace in oxygen O2Carrying out high-temperature sacrificial oxidation on the silicon carbide epitaxial wafer in the environment;
wherein: the oxidation temperature of the high-temperature sacrificial oxidation is 1200-1500 ℃, the oxidation time is 10-30 min, and oxygen O2Has a purity of 6N, oxygen O2The flow rate of (2) is 0.1 to 10 slm.
6. A method of fabricating a gate oxide as claimed in claim 1,
the etching the sacrificial oxide layer comprises: corroding the sacrificial oxide layer by adopting wet corrosion at normal temperature;
wherein: the etching solution of the wet etching is BOE etching solution or DHF solution with the concentration of 1-50%.
7. The method of claim 1 wherein said subjecting said silicon carbide epitaxial wafer to a high temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing in sequence comprises: by using a box furnace or a tube furnace in nitric oxide NO or nitrous oxide N2Annealing the silicon carbide epitaxial wafer in an O environment; wherein: the nitric oxide NO and laughing gas N2The purity of O is 6N, and the flow rate is 0.1-10 slm; the annealing temperature is the same as the high-temperature dry oxygen-wet oxygen-dry oxygen oxidation temperature, or the temperature is 1000-1300 ℃; the annealing time is 0.1-4 h.
8. The MOSFET power device prepared by the gate oxide layer preparation method of claim 1, wherein the MOSFET power device comprises:
the epitaxial silicon carbide wafer comprises a silicon carbide substrate and an epitaxial layer, wherein the silicon carbide substrate and the epitaxial layer are both provided with a first conduction type; wherein: the upper surface of the epitaxial layer is a smooth passivated surface formed after the high-temperature surfacing treatment is carried out on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed;
a gate oxide layer disposed on the smooth passivated surface; wherein: the gate oxide layer is formed by sequentially carrying out high-temperature dry oxygen-wet oxygen-dry oxygen oxidation and nitridation annealing on the silicon carbide epitaxial wafer.
9. The MOSFET power device of claim 8,
the silicon carbide substrate is 4H-SiC or 6H-SiC, and the thickness of the silicon carbide substrate is 300-1000 μm or 10-400 μm;
the silicon carbide substrate is a silicon carbide substrate heavily doped with nitrogen ions N or phosphorus ions P, and the resistivity is 0.001-0.1 omega cm; or the silicon carbide substrate is doped with vanadium ions V or not doped with any ionsBottom, resistivity greater than 105Ω·cm。
10. The MOSFET power device of claim 8,
the epitaxial layer comprises a silicon carbide epitaxial layer having a first conductivity type; alternatively, the first and second electrodes may be,
the epitaxial layer comprises a first epitaxial layer with a first conductivity type, a second epitaxial layer with a second conductivity type and a third epitaxial layer with the first conductivity type, which are sequentially arranged on the front surface of the silicon carbide substrate from bottom to top.
11. The MOSFET power device of claim 10,
the silicon carbide epitaxial layer is 4H-SiC or 6H-SiC, and the thickness of the silicon carbide epitaxial layer is 1-300 mu m; the silicon carbide epitaxial layer is doped with nitrogen ions N or phosphorus ions P, and the doping concentration is 1 multiplied by 1013～1×1016cm-3。
12. The MOSFET power device of claim 10,
the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all 4H-SiC or 6H-SiC;
the first epitaxial layer is a silicon carbide epitaxial layer doped with nitrogen ions N or phosphorus ions P, and the doping concentration of the first epitaxial layer is 1 multiplied by 1013～1×1016cm-3The thickness is 1 to 300 μm;
the second epitaxial layer is a silicon carbide epitaxial layer doped with aluminum ions Al or boron ions B, and the doping concentration of the second epitaxial layer is 1 multiplied by 1015～1×1017cm-3The thickness is 0.1-10 μm;
the third epitaxial layer is a silicon carbide epitaxial layer doped with nitrogen ions N or phosphorus ions P, and the doping concentration of the third epitaxial layer is 1 multiplied by 1018～1×1021cm-3The thickness is 0.1 to 1 μm.
13. The MOSFET power device of claim 10, further comprising a well region, a source contact region, and a base contact region;
the well region is a well region with a second conduction type and is arranged in the silicon carbide epitaxial layer;
the source electrode contact region is a contact region with a first conduction type and is arranged in the well region; the base contact region is a contact region having a second conductivity type disposed within the well region.
14. The MOSFET power device of claim 13,
the junction depth of the well region is 0.2-1.0 μm, the impurity ions are aluminum ions Al or boron ions B, and the concentration of the impurity ions is 1 x 1015～1×1017cm-3；
The junction depth of the source electrode contact region is 0.1-0.5 mu m, the impurity ions are nitrogen ions N or phosphorus ions P, and the concentration of the impurity ions is 1 multiplied by 1019～1×1021cm-3；
The junction depth of the base contact region is 0.1-0.5 μm, the concentration of the impurity ions is 1 × 1018～1×1021cm-3。
15. The MOSFET power device of claim 10, further comprising a base contact region and a trench region;
the base contact region is a contact region with a second conductivity type and is arranged in the third epitaxial layer;
the groove region penetrates through the third epitaxial layer and the second epitaxial layer, and the depth of the groove region is smaller than the sum of the junction depths of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer.
16. The MOSFET power device of claim 15,
the junction depth of the base electrode contact region is 0.1-0.5 μm, impurity ions are doped with p-type ions, and the concentration of the impurity ions is 1 × 1018～1×1021cm-3；
The depth of the groove region penetrating into the first epitaxial layer is 0.1-1 mu m.
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| CN109461646B (en) * | 2018-10-31 | 2020-11-17 | 秦皇岛京河科学技术研究院有限公司 | Annealing method for SiC MOSFET gate oxide layer |
| CN110212031A (en) * | 2019-05-24 | 2019-09-06 | 华中科技大学 | A kind of carbide MOS devices and preparation method thereof |
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| CN111816549A (en) * | 2020-06-01 | 2020-10-23 | 浙江博蓝特半导体科技股份有限公司 | Method for cleaning surface of silicon carbide wafer |
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