CN109461646B - Annealing method for SiC MOSFET gate oxide layer - Google Patents
Annealing method for SiC MOSFET gate oxide layer Download PDFInfo
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- 238000000137 annealing Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000007789 gas Substances 0.000 claims abstract description 42
- 239000011261 inert gas Substances 0.000 claims abstract description 24
- 230000001590 oxidative effect Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 238000004140 cleaning Methods 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 26
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 26
- 239000000377 silicon dioxide Substances 0.000 abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 26
- 229910052682 stishovite Inorganic materials 0.000 abstract description 26
- 229910052905 tridymite Inorganic materials 0.000 abstract description 26
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 32
- 230000003647 oxidation Effects 0.000 description 19
- 238000007254 oxidation reaction Methods 0.000 description 19
- 229910052760 oxygen Inorganic materials 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 229910018557 Si O Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003344 environmental pollutant Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 231100000719 pollutant Toxicity 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000003471 anti-radiation Effects 0.000 description 1
- 150000001721 carbon Chemical class 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- -1 organic matters Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
Abstract
The invention relates toA SiC MOSFET gate oxide annealing method comprises the following steps: preparing a SiC epitaxial wafer; growing SiO on the SiC epitaxial wafer2A gate oxide layer; in the presence of an inert gas and Cl2Under the condition of mixed gas environment, the SiO is treated2And annealing the gate oxide layer. The invention uses inert gas and Cl2Mixed gas annealed SiC MOSFET device SiO2A gate oxide layer for improving SiO content in SiC MOSFET device2Critical breakdown electric field capability of the gate oxide layer.
Description
Technical Field
The invention belongs to the field of SiC MOSFET devices, and particularly relates to an annealing method of a gate oxide layer of a SiC MOSFET.
Background
SiC is used as a third-generation semiconductor material, has the advantages of wide band gap, high thermal conductivity, high breakdown field strength and the like, and is suitable for manufacturing high-temperature high-power, high-temperature high-frequency and anti-radiation devices. Therefore, SiC is widely used in a Semiconductor Field Effect Transistor (MOSFET).
In SiC MOSFETs, SiO is generated during the growth process2Lattice mismatch with SiC materials in SiO2SiO of gate oxide layer2A great deal of trapped charges such as dangling bonds, carbon clusters, oxygen vacancies and the like can be generated in the interface and the SiC interface of the SiC epitaxial wafer, and the performance of the device is influenced. Reduction of SiO at present2The method of trapping charges in the/SiC interface is to use high temperature gas annealing. Common annealing gases are nitrogen-containing gases (e.g., N)2O, NO, etc.), Ar, H2And the like. Wherein the nitrogen-containing gas is mainly used for reducing SiO2SiC interfaceCarbon cluster phenomenon of (H)2Mainly used for reducing SiO2Dangling bonds at the/SiC interface.
However, in SiC MOSFETs, SiO is grown at high temperatures2In the process of gate oxide layer, SiO2SiO of gate oxide layer2A great deal of oxygen vacancy trap charges can be generated in the SiC interface of the interface and the SiC epitaxial wafer, and SiO in the SiC MOSFET device can be reduced2Critical breakdown electric field capability of the gate oxide layer.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an annealing method of a SiC MOSFET gate oxide layer.
The embodiment of the invention provides an annealing method of a SiC MOSFET gate oxide layer, which comprises the following steps:
preparing a SiC epitaxial wafer;
growing SiO on the SiC epitaxial wafer2A gate oxide layer;
in the presence of an inert gas and Cl2Under the condition of mixed gas environment, the SiO is treated2And annealing the gate oxide layer.
In one embodiment of the present invention, preparing the SiC epitaxial wafer includes:
selecting a SiC substrate layer;
growing a SiC epitaxial layer on the SiC substrate layer to form the SiC epitaxial wafer.
In one embodiment of the invention, the SiO is grown on the SiC epitaxial wafer2Before the gate oxide, still include:
and cleaning the SiC epitaxial wafer by using RCA.
In one embodiment of the invention, the SiO is grown on the SiC epitaxial wafer2A gate oxide layer comprising:
introducing oxidizing gas at the temperature of 1000-1400 ℃, and growing the SiO on the SiC epitaxial wafer2And (4) a gate oxide layer.
In one embodiment of the invention, the oxidizing gas is a dry oxidizing gas or a wet oxidizing gas.
In one embodiment of the invention, the inert gas isWith Cl2Under the condition of mixed gas environment, the SiO is treated2And annealing the gate oxide layer, comprising:
under the conditions of 500-1000 ℃ temperature, set pressure and set time, in inert gas and Cl2Under the condition of mixed gas environment, the SiO is treated2And annealing the gate oxide layer.
In one embodiment of the invention, the set pressure is between 0.1mbar and 1 mbar.
In one embodiment of the present invention, the setting time is 30-180 min.
In one embodiment of the invention, the inert gas is mixed with Cl2Under the mixed gas environment condition, the Cl2The proportion of the mixed gas is 20-90%.
In one embodiment of the invention, the inert gas is N2Ar or He.
Compared with the prior art, the invention has the beneficial effects that:
the invention uses inert gas and Cl2Mixed gas annealed SiC MOSFET device SiO2A gate oxide layer capable of increasing SiO content in the SiC MOSFET device by reducing oxygen vacancy trap charges in the SiC MOSFET device2Critical breakdown electric field capability of the gate oxide layer.
Drawings
FIG. 1 is a schematic flow chart of a method for annealing a SiC MOSFET gate oxide layer according to an embodiment of the present invention;
FIGS. 2a to 2c are schematic diagrams of a process flow for preparing a SiC MOSFET gate oxide layer according to an embodiment of the present invention;
fig. 3 is a schematic diagram of temperature change of an annealing method for a SiC MOSFET gate oxide layer according to an embodiment of the present invention.
Description of reference numerals:
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 2a to 2c and fig. 3, fig. 1 is a schematic flow chart of a method for annealing a gate oxide of a SiCMOSFET according to an embodiment of the present invention; FIGS. 2a to 2c are schematic diagrams of a process flow for preparing a SiC MOSFET gate oxide layer according to an embodiment of the present invention; fig. 3 is a schematic diagram of temperature change of an annealing method for a SiC MOSFET gate oxide layer according to an embodiment of the present invention. The annealing method of the SiC MOSFET gate oxide layer comprises the following steps:
step 1, preparing a SiC epitaxial wafer;
preparing the SiC epitaxial wafer, comprising:
step 1.1, selecting a SiC substrate layer 01;
referring to fig. 2a, a SiC substrate layer 01 is selected.
SiC has advantages of wide band gap, high thermal conductivity, high breakdown field strength, and the like, and is suitable for manufacturing high-temperature, high-power, high-temperature, high-frequency, and radiation-resistant devices, so SiC is widely applied to semiconductor field effect transistors (MOSFETs).
And 1.2, growing a SiC epitaxial layer 02 on the SiC substrate layer 01 to form a SiC epitaxial wafer.
Cleaning the SiC substrate layer 01 by using RCA (Wet chemical cleaning method);
referring to fig. 2b, an SiC epitaxial layer 02 is grown on the SiC substrate layer 01 by chemical vapor deposition to form a SiC epitaxial wafer. The SiC epitaxial wafer comprises a SiC substrate layer 01 and a SiC epitaxial layer 02.
step 2.1, cleaning the SiC epitaxial wafer by using RCA;
the purpose of the RCA cleaning is to remove pollutants such as organic matters, particles, metal impurities and the like which may exist on the surface of the SiC epitaxial wafer, and the existence of the pollutants can influence the electrical characteristics of the SiC MOSFET device.
Step 2.2, growing SiO on the SiC epitaxial wafer2A gate oxide layer 03.
Firstly, the cleaned SiC epitaxial wafer is put into growing SiO2A high-temperature oxidation furnace of a gate oxide layer 03.
Further, referring to fig. 3, the temperature of the high temperature oxidation furnace is raised from room temperature to the oxidation temperature, i.e. the process T1 → T2, so that the temperature in the high temperature oxidation furnace storing the SiC epitaxial wafer reaches the temperature of the thermal oxidation growth SiO2The temperature of the gate oxide layer 03. Wherein the room temperature is 25 ℃.
Preferably, the oxidation temperature is 1000 ℃ to 1400 ℃.
Further, referring to fig. 3, the temperature inside the high temperature oxidation furnace is maintained at the oxidation temperature, i.e., the process T2 → T3, and the oxidizing gas is introduced into the high temperature oxidation furnace. Wherein, the introduced oxidizing gas can be dry oxidizing gas or wet oxidizing gas;
referring to FIG. 2c, SiO is grown on the SiC epitaxial wafer2A gate oxide layer 03;
specifically, oxidizing gas is introduced into a high-temperature oxidation furnace, and SiO grows on the SiC epitaxial wafer2 Gate oxide layer 03, for dry oxidation, dry O2React with the SiC epitaxial wafer to generate SiO2And CO, wherein the CO gas passes through the SiO2And escape SiC/SiO2Interface, formation of SiO on SiC epitaxial wafer2A gate oxide layer 03; for wet oxidation, H is introduced2O steam (or introduction of H)2And O2Two gases are subjected to chemical combination reaction in a high-temperature oxidation furnace to generate H2O vapor) reacts with SiC epitaxial wafer to generate CO and H2And SiO2Wherein CO and H2Gas passing through SiO2And escape SiC/SiO2Interface, formation of SiO on SiC epitaxial wafer2A gate oxide layer 03.
Growing SiO2The process conditions of the gate oxide layer 03 are as follows: the pressure in the high-temperature oxidation furnace is 0.1-1 mbar, and SiO grows2The time of the gate oxide layer 03 is 10-180 min. Wherein SiO is grown2The gate oxide layer 03 can obtain SiO with different thicknesses in long and short time2A gate oxide layer 03.
Step 3, in inert gas and Cl2Under the condition of mixed gas environment, the SiO is treated2And annealing the gate oxide layer.
First, please refer toFIG. 3, the temperature of the high temperature oxidation furnace is lowered to the annealing temperature, i.e., T3 → T4 process, because of the annealing of SiO2The gate oxide layer 03 requires an annealing temperature, so that the temperature of the high-temperature oxidation furnace is lowered to the annealing temperature.
Preferably, the annealing temperature is 500 ℃ to 1000 ℃.
Further, referring to FIG. 3, the temperature of the high temperature oxidation furnace is maintained at the annealing temperature, i.e. T4 → T5 process, inert gas and Cl are added2Introducing the mixed gas into a high-temperature oxidation furnace, and annealing SiO2A gate oxide layer 03. Using inert gases with Cl2Mixed gas annealing of SiO2The gate oxide layer 03 is formed by inert gas and Cl2Cl in the mixed gas2Can reduce oxygen vacancy trap charges in the SiC MOSFET device to obtain the SiO of the SiC MOSFET device with high critical breakdown electric field2A gate oxide layer 03. By Cl2Mixed with inert gas because of excess Cl2Will destroy SiO2Si-O bond in gate oxide layer 03, diluting Cl with inert gas2Prevention of excessive Cl2Destruction of SiO2Si-O bond in the gate oxide layer 03, resulting in SiO2Damage of the gate oxide layer 03.
Preferably, Cl2Inert gas and Cl2The proportion of the mixed gas is 20-90%.
Specifically, Cl2With SiO2Oxygen vacancies in the gate oxide layer 03 form Si-Cl bonds to reduce oxygen vacancies in SiC MOSFET devices.
Annealing SiO2The process conditions of the gate oxide layer 03 are as follows: the pressure in the high-temperature oxidation furnace is 0.1mbar to 1mbar, and inert gas and Cl are introduced for 30min to 180min2And (4) mixing the gases.
Further, the annealed SiO is taken out of the high-temperature oxidation furnace2A gate oxide layer 03.
Referring to FIG. 3, the annealing temperature in the HTO furnace is decreased to 25 ℃ in the room, i.e. T5 → T6, and the annealed SiO is taken out of the HTO furnace at 25 ℃ in the HTO furnace2And the gate oxide layer 03 completes the annealing of the SiC MOSFET gate oxide layer.
Referring again to FIG. 3, the process T1 → T6 forms the SiO of the SiC MOSFET device of the present invention2Temperature variation of the whole process of annealing the gate oxide layer 03. The inert gas and Cl2Mixed gas annealing of SiO2The method of the gate oxide layer 03 improves SiO of the SiC MOSFET device2Critical breakdown electric field capability of the gate oxide layer 03.
The beneficial effects of this embodiment:
this example uses an inert gas and Cl2Mixed gas annealed SiC MOSFET device SiO2A gate oxide layer capable of increasing SiO content of the SiC MOSFET device by reducing oxygen vacancy trap charges in the SiC MOSFET device2Critical breakdown electric field capability of the gate oxide layer 03.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (8)
1. A method for annealing a SiC MOSFET gate oxide layer is characterized by comprising the following steps:
preparing a SiC epitaxial wafer;
growing SiO on the SiC epitaxial wafer2A gate oxide layer;
in the presence of an inert gas and Cl2Under the condition of mixed gas environment, the SiO is treated2And annealing the gate oxide layer, comprising:
under the conditions of 500-1000 deg.C, set pressure and set time in the presence of said inert gas and Cl2Under the condition of mixed gas environment, the SiO is treated2Annealing the gate oxide layer, wherein the set pressure is 0.1 mbar-1 mbar, and the inert gas and Cl are mixed2Under the mixed gas environment condition, the Cl2The proportion of the mixed gas is 20-90%.
2. The method of claim 1, wherein preparing the SiC epitaxial wafer comprises:
selecting a SiC substrate layer;
growing a SiC epitaxial layer on the SiC substrate layer to form the SiC epitaxial wafer.
3. The method of claim 1, wherein the SiO is grown on the SiC epitaxial wafer2Before the gate oxide, still include:
and cleaning the SiC epitaxial wafer by using RCA.
4. The method of claim 1, wherein the SiO is grown on the SiC epitaxial wafer2A gate oxide layer comprising:
introducing oxidizing gas at the temperature of 1000-1400 ℃, and growing the SiO on the SiC epitaxial wafer2And (4) a gate oxide layer.
5. The method of claim 4, wherein the oxidizing gas is a dry oxidizing gas or a wet oxidizing gas.
6. The method of claim 1, wherein the inert gas is mixed with Cl2Under the condition of mixed gas environment, the SiO is treated2And annealing the gate oxide layer, comprising:
under the conditions of 500-1000 deg.C, set pressure and set time in the presence of said inert gas and Cl2Under the condition of mixed gas environment, the SiO is treated2And annealing the gate oxide layer.
7. The method according to claim 6, wherein the set time is 30-180 min.
8. The method of claim 1, wherein the inert gas is N2Ar or He.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104637801A (en) * | 2015-01-30 | 2015-05-20 | 株洲南车时代电气股份有限公司 | Method for preparing SiC MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) grid oxide layer |
| CN104658903A (en) * | 2015-01-30 | 2015-05-27 | 株洲南车时代电气股份有限公司 | Method for preparing SiC MOSFET gate oxide layer |
| CN108257859A (en) * | 2016-12-28 | 2018-07-06 | 全球能源互联网研究院 | A kind of preparation method of gate oxide and MOSFET power devices |
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| AU2002349589A1 (en) * | 2001-11-30 | 2003-06-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and production method therefor |
| JP2015142034A (en) * | 2014-01-29 | 2015-08-03 | ルネサスエレクトロニクス株式会社 | Method for manufacturing semiconductor device |
| CN107046059B (en) * | 2016-02-05 | 2020-04-21 | 瀚薪科技股份有限公司 | Silicon carbide semiconductor element and method for manufacturing same |
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| CN104637801A (en) * | 2015-01-30 | 2015-05-20 | 株洲南车时代电气股份有限公司 | Method for preparing SiC MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) grid oxide layer |
| CN104658903A (en) * | 2015-01-30 | 2015-05-27 | 株洲南车时代电气股份有限公司 | Method for preparing SiC MOSFET gate oxide layer |
| CN108257859A (en) * | 2016-12-28 | 2018-07-06 | 全球能源互联网研究院 | A kind of preparation method of gate oxide and MOSFET power devices |
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