CN111403280A - Silicon carbide MOS capacitor device and manufacturing method thereof - Google Patents
Silicon carbide MOS capacitor device and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
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Abstract
The invention provides a silicon carbide MOS capacitor device and a manufacturing method thereof, wherein the first annealing treatment is carried out under the Ar atmosphere condition or the Ar atmosphere condition containing O element, and further, the C element at the interface of a SiC epitaxial layer and a gate oxide layer can be removed through Ar annealing, so that the related defect of the C element is decomposed and leaves the position of the interface; further annealing under the Ar atmosphere condition containing O element can promote the decomposition and removal of C element related defects; and then, the second annealing treatment is carried out under the condition of the atmosphere containing N, the annealing of the atmosphere containing N can introduce N elements into the interface of the SiC epitaxial layer and the gate oxide layer, so that dangling bonds or other defects existing at the interface can be passivated, the defects at the interface of the gate oxide layer and the SiC epitaxial layer are finally improved, and the reliability of the silicon carbide MOS capacitor device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a silicon carbide MOS capacitor device and a manufacturing method thereof.
Background
The third-generation semiconductor material SiC has a larger forbidden bandwidth and a higher critical breakdown field strength than the first-generation semiconductor material represented by silicon and the second-generation semiconductor material represented by gallium arsenide. Compared with a silicon power device under the same condition, the withstand voltage degree of the SiC device is about 100 times that of the silicon material, and particularly, the withstand voltage range of the Schottky Diode (SBD) and junction Barrier Schottky Diode (JBS) structural products sequentially introduced by SiC device manufacturers in recent years reaches 600V-1700V. Meanwhile, SiC has higher thermal conductivity and lower intrinsic carrier concentration, and can bear junction temperature of about 600 ℃, so that the working temperature limit of the SiC device is greatly improved. In addition, the SiC device has high electronic saturation rate, small forward on-resistance and low power loss, is suitable for large-current and high-power application, and reduces the requirements on heat dissipation equipment. SiC is more convenient for forming silicon dioxide by thermal oxidation than other third generation semiconductors such as GaN. Therefore, SiC is considered as an important development direction of a new generation of high-performance power electronic devices, and has wide application prospects in the fields of new energy automobiles, rail transit, locomotive traction, smart power grids and the like.
However, in SiC power devices, the gate oxide layer formed by thermal oxidation may be in SiO2A large number of defects (such as carbon clusters, oxygen vacancies and the like) are introduced into the SiC interface, so that the state density of the interface is greatly increased, the effective mobility of an inversion layer carrier of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is greatly reduced, the reliability of a gate Oxide layer is reduced, and the development and the application of a SiC power device are seriously restricted.
Disclosure of Invention
In view of this, the invention provides a silicon carbide MOS capacitor device and a method for manufacturing the same, which effectively solve the technical problems in the prior art and improve the defects at the interface between the gate oxide layer and the SiC epitaxial layer.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a method for manufacturing a silicon carbide MOS capacitor device comprises the following steps:
providing a SiC epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC substrate and a SiC epitaxial layer positioned on the SiC substrate;
carrying out oxidation treatment on the SiC epitaxial wafer to form a gate oxide layer positioned on one side of the SiC epitaxial layer, which is far away from the SiC substrate;
carrying out first annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the Ar atmosphere condition or the Ar atmosphere condition containing O elements;
carrying out secondary annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the condition of N-containing atmosphere;
and forming a first electrode on one side of the gate oxide layer, which is far away from the SiC substrate, and forming a second electrode on one side of the SiC substrate, which is far away from the SiC epitaxial layer.
Optionally, the annealing temperature range during the first annealing treatment is 1200 ℃ to 1500 ℃, inclusive.
Optionally, the annealing temperature range during the second annealing treatment is 1200 ℃ to 1500 ℃, inclusive.
Optionally, the N-containing atmosphere condition is NO atmosphere condition, N2Atmospheric conditions, NH3Atmospheric conditions or NO2Atmospheric conditions.
Optionally, the annealing temperature during the first annealing treatment is higher than the oxidation temperature during the oxidation treatment.
Optionally, the annealing temperature in the second annealing treatment is lower than the annealing temperature in the first annealing treatment.
Optionally, while the oxidation treatment is performed on the SiC epitaxial wafer to form the gate oxide layer, the oxidation treatment is performed on the SiC epitaxial wafer to form a sacrificial oxide layer on one side of the SiC substrate away from the SiC epitaxial layer;
wherein the sacrificial oxide layer is removed before the second electrode is formed.
Optionally, the SiC epitaxial wafer is made of 4H-SiC, 3C-SiC or 6H-SiC.
Optionally, the oxidation treatment of the SiC epitaxial wafer includes:
and carrying out dry oxygen oxidation treatment on the SiC epitaxial wafer, and carrying out high-temperature treatment at a preset temperature on the SiC epitaxial wafer in an oxygen atmosphere.
Correspondingly, the invention also provides a silicon carbide MOS capacitor device which is manufactured by adopting the manufacturing method of the silicon carbide MOS capacitor device.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a silicon carbide MOS capacitor device and a manufacturing method thereof, wherein the method comprises the following steps: providing a SiC epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC substrate and a SiC epitaxial layer positioned on the SiC substrate; carrying out oxidation treatment on the SiC epitaxial wafer to form a gate oxide layer positioned on one side of the SiC epitaxial layer, which is far away from the SiC substrate; carrying out first annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the Ar atmosphere condition or the Ar atmosphere condition containing O elements; carrying out secondary annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the condition of N-containing atmosphere; and forming a first electrode on one side of the gate oxide layer, which is far away from the SiC substrate, and forming a second electrode on one side of the SiC substrate, which is far away from the SiC epitaxial layer.
According to the technical scheme provided by the invention, the first annealing treatment is carried out under the Ar atmosphere condition or the Ar atmosphere condition containing O elements, and further, the C elements at the interface of the SiC epitaxial layer and the gate oxide layer can be removed through the Ar annealing, so that the C element related defects are decomposed and leave the interface position; further annealing under the Ar atmosphere condition containing O element can promote the decomposition and removal of C element related defects; and then, the second annealing treatment is carried out under the condition of the atmosphere containing N, the annealing of the atmosphere containing N can introduce N elements into the interface of the SiC epitaxial layer and the gate oxide layer, so that dangling bonds or other defects existing at the interface can be passivated, the defects at the interface of the gate oxide layer and the SiC epitaxial layer are finally improved, and the reliability of the silicon carbide MOS capacitor device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a silicon carbide MOS capacitor device according to an embodiment of the present invention;
FIG. 2 is a flow chart of another method for fabricating a silicon carbide MOS capacitor device according to an embodiment of the invention;
fig. 3 a-3 f are corresponding schematic structural diagrams of the steps in fig. 2.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background, in SiC power devices, the gate oxide layer formed by thermal oxidation is in SiO2A large number of defects (such as carbon clusters, oxygen vacancies and the like) are introduced into the/SiC interface, so that the state density of the interface at the interface is greatly increased, the effective mobility of an inversion layer carrier of the SiC metal oxide semiconductor field effect transistor is greatly reduced, the reliability of a gate oxide layer is reduced, and the development and the application of the SiC power device are seriously restricted.
Based on the above, the invention provides a silicon carbide MOS capacitor device and a manufacturing method thereof, which effectively solve the technical problems in the prior art and improve the defects at the interface of a gate oxide layer and a SiC epitaxial layer.
In order to achieve the above object, the technical solutions provided by the present invention are described in detail below, specifically with reference to fig. 1 to 3 f.
Referring to fig. 1, a flowchart of a method for manufacturing a silicon carbide MOS capacitor device according to an embodiment of the present invention is shown, where the method includes:
s1, providing a SiC epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC substrate and a SiC epitaxial layer located on the SiC substrate;
s2, carrying out oxidation treatment on the SiC epitaxial wafer to form a gate oxide layer on one side of the SiC epitaxial layer, which is far away from the SiC substrate;
s3, carrying out first annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the Ar atmosphere condition or the Ar atmosphere condition containing O elements;
s4, carrying out secondary annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the condition of N-containing atmosphere;
and S5, forming a first electrode on the side of the gate oxide layer, which is far away from the SiC substrate, and forming a second electrode on the side of the SiC substrate, which is far away from the SiC epitaxial layer.
The technical scheme provided by the invention can be understood that the first annealing treatment is carried out under the Ar atmosphere condition or the Ar atmosphere condition containing O element, and further the C element at the interface of the SiC epitaxial layer and the gate oxide layer can be removed through the Ar annealing, so that the related defects of the C element are decomposed and leave the position of the interface; further annealing under the Ar atmosphere condition containing O element can promote the decomposition and removal of C element related defects; and then, the second annealing treatment is carried out under the condition of the atmosphere containing N, the annealing of the atmosphere containing N can introduce N elements into the interface of the SiC epitaxial layer and the gate oxide layer, so that dangling bonds or other defects existing at the interface can be passivated, the defects at the interface of the gate oxide layer and the SiC epitaxial layer are finally improved, and the reliability of the silicon carbide MOS capacitor device is improved.
In one embodiment of the present invention, the present invention can protect the SiC substrate side of the SiC epitaxial wafer before the oxidation treatment is performed on the SiC epitaxial wafer, and form the gate oxide layer only on the SiC epitaxial layer side of the SiC epitaxial wafer when the oxidation treatment is performed on the SiC epitaxial wafer. Or,
before the oxidation treatment is carried out on the SiC epitaxial wafer, one side of the SiC substrate of the SiC epitaxial wafer is not protected, and when the oxidation treatment is carried out on the SiC epitaxial wafer, a gate oxide layer is formed on one side of the SiC epitaxial layer of the SiC epitaxial wafer, a sacrificial oxide layer is formed on one side of the SiC substrate of the SiC epitaxial wafer at the same time, and then the sacrificial oxide layer is removed before the second electrode is manufactured; that is, in the embodiment of the present invention, while the oxidation treatment is performed on the SiC epitaxial wafer to form the gate oxide layer, the oxidation treatment is performed on the SiC epitaxial wafer, and a sacrificial oxide layer is further formed on a side of the SiC substrate away from the SiC epitaxial layer;
wherein the sacrificial oxide layer is removed before the second electrode is formed.
Referring specifically to fig. 2, a flowchart of another silicon carbide MOS capacitor device and a manufacturing method thereof according to an embodiment of the present invention is shown, where the manufacturing method includes:
s11, providing a SiC epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC substrate and a SiC epitaxial layer located on the SiC substrate;
s12, carrying out oxidation treatment on the SiC epitaxial wafer to form a gate oxide layer on one side, away from the SiC substrate, of the SiC epitaxial layer and simultaneously form a sacrificial oxide layer on one side, away from the SiC epitaxial layer, of the SiC substrate;
s13, carrying out first annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the Ar atmosphere condition or the Ar atmosphere condition containing O elements;
s14, carrying out secondary annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the condition of N-containing atmosphere;
s15, forming a first electrode on the side, facing away from the SiC substrate, of the gate oxide layer;
and S16, removing the sacrificial oxide layer, and forming a second electrode on the side of the SiC substrate, which is far away from the SiC epitaxial layer.
It should be noted that, in the embodiment of the present invention, the step of removing the sacrificial oxide layer may be performed after the step of forming the first electrode, or may be performed before the step of forming the first electrode, and the present invention is not particularly limited as long as the step is performed before the step of forming the second electrode.
The technical solution provided by the embodiment of the present invention is described in more detail below with reference to the schematic structural diagrams corresponding to each step in the manufacturing method of the silicon carbide MOS capacitor device. Referring to fig. 3 a-3 f, there are shown corresponding schematic structural diagrams of the steps in fig. 2.
As shown in fig. 3a, corresponding to step S11, a SiC epitaxial wafer is provided, where the SiC epitaxial wafer includes a SiC substrate 101 and a SiC epitaxial layer 102 on the SiC substrate 101.
In an embodiment of the invention, the material of the SiC epitaxial wafer provided by the invention can be 4H-SiC, 3C-SiC or 6H-SiC. The SiC epitaxial wafer may be an N-type material or a P-type material, and the present invention is not particularly limited thereto.
It can be understood that the material of the SiC epitaxial wafer provided by the embodiment of the present invention may be 3C-SiC, where 3C-SiC is the only homogeneous polytype with a sphalerite structure, the electron mobility of the polytype is the highest, and the polytype has high thermal conductivity and high critical breakdown electric field; the SiC epitaxial wafer provided by the embodiment of the invention can be made of 6H-SiC, the 6H-SiC has a wide band gap, and a power device made of the 6H-SiC has the advantages of high working temperature and the like; the SiC epitaxial wafer provided by the embodiment of the invention is made of 4H-SiC, the 4H-SiC has a wider band gap than the 6H-SiC, and the 4H-SiC has higher electron mobility and higher breakdown electric field intensity.
Preferably, the material of the SiC epitaxial layer provided by the embodiment of the present invention is 4H — SiC, the thickness of the SiC epitaxial layer may be set to 12 μm, and the doping concentration of the SiC epitaxial layer may be 8 × 1015cm-3。
As shown in fig. 3b, corresponding to step S12, performing oxidation treatment on the SiC epitaxial wafer to form a gate oxide layer 200 on the side of the SiC epitaxial layer 102 away from the SiC substrate 101, and simultaneously forming a sacrificial oxide layer 300 on the side of the SiC substrate 101 away from the SiC epitaxial layer 102;
in an embodiment of the present invention, before the oxidation treatment is performed on the SiC epitaxial wafer provided by the present invention, the SiC epitaxial wafer may be cleaned. Optionally, the SiC epitaxial wafer may be cleaned by a standard RCA cleaning method, and the present invention is not particularly limited.
Specifically, the SiC epitaxial wafer can be immersed in a mixed solution of 98 wt% concentrated sulfuric acid and 27 wt% hydrogen peroxide in a volume ratio of 1:1, heated in a water bath at 90 ℃ for 15min, washed with deionized water, and then N is used2Drying; then, soaking the SiC epitaxial wafer in a mixed solution of 28 wt% ammonia water and 27 wt% hydrogen peroxide in a volume ratio of 1:1, heating in a water bath for 15min, washing with deionized water, and then adopting N2Drying; finally, the SiC epitaxial wafer is immersed in a mixed solution of 10 wt% hydrochloric acid and 27 wt% hydrogen peroxide in a volume ratio of 1:1, heated in water bath for 15min at the temperature of 90 ℃, cleaned by deionized water, and then N is adopted2And drying to finish the cleaning process of the SiC epitaxial wafer.
After the SiC epitaxial wafer is cleaned, the SiC epitaxial wafer is placed in an oxidation furnace for oxidation. Optionally, the oxidation treatment of the SiC epitaxial wafer provided in the embodiment of the present invention includes:
and carrying out dry oxygen oxidation treatment on the SiC epitaxial wafer, and carrying out high-temperature treatment at a preset temperature on the SiC epitaxial wafer in an oxygen atmosphere to form a gate oxide layer and a sacrificial oxide layer.
In an embodiment of the present invention, the preset temperature provided by the present invention may be 1200 ℃ to 1500 ℃, inclusive; further optimization can be 1250 ℃ -1450 ℃, inclusive.
The embodiment of the invention provides a specific oxidation treatment process for a SiC epitaxial wafer, wherein nitrogen is firstly utilized to evacuate air in an oxidation furnace, and the cleaned SiC epitaxial wafer is placed on a quartz boat under the condition that the nitrogen is taken as protective gas, and is slowly pushed into a constant-temperature area of the oxidation furnace in an environment with the temperature of 700 ℃; then heating the constant temperature region at a rate of 5 ℃/min, slowly introducing oxygen when the temperature is raised to 1350 ℃, oxidizing the SiC epitaxial wafer for 20min in a pure dry oxygen atmosphere to form SiO with the thickness of 58nm-60nm2A gate oxide layer and SiO with a thickness of 58nm-60nm2And (4) sacrificing the oxide layer.
As shown in fig. 3c, corresponding to step S13, the SiC epitaxial wafer on which the gate oxide layer 200 and the sacrificial oxide layer 300 are formed is subjected to a first annealing treatment under an Ar atmosphere or an Ar atmosphere containing an O element.
After the SiC epitaxial wafer is placed in an oxidation furnace for oxidation treatment, an oxygen channel is closed, then a constant temperature region is cooled under the protection of nitrogen, and then the SiC epitaxial wafer is slowly pulled out of a quartz boat and taken out after the oxidation treatment; and then carrying out first annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the pure Ar atmosphere condition or the Ar atmosphere condition containing O elements (such as oxygen gas).
In an embodiment of the present invention, the annealing temperature range of the first annealing treatment provided by the present invention is 1200 ℃ to 1500 ℃, inclusive.
Further, the annealing temperature during the first annealing treatment provided by the embodiment of the present invention is higher than the oxidation temperature during the oxidation treatment, so that at a high temperature, the C element related defects at the interface between the SiC epitaxial layer and the gate oxide layer are decomposed and leave the interface; and further annealing under an Ar atmosphere containing an O element can promote the decomposition and removal of C element-related defects.
As shown in fig. 3d, corresponding to step S14, a second annealing process is performed on the SiC epitaxial wafer on which the gate oxide layer 200 is formed under an N-containing atmosphere;
after the first annealing treatment is finished (if the first annealing treatment is under the condition of Ar atmosphere containing O element, the oxygen channel needs to be closed), cooling the constant temperature area under the protection of Ar gas; and then carrying out secondary annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the condition of N-containing atmosphere.
In an embodiment of the present invention, the atmosphere condition containing N provided by the present invention is NO atmosphere condition, N2Atmospheric conditions, NH3Atmospheric conditions or NO2The atmosphere conditions are not particularly limited to the present invention. And the annealing temperature range during the second annealing treatment provided by the invention is 1200-1500 ℃ inclusive.
Furthermore, the annealing temperature during the second annealing treatment is lower than that during the first annealing treatment, so that annealing at a lower temperature is adopted during the second annealing treatment, defects caused by high temperature during the first annealing treatment can be repaired, and the reliability of the silicon carbide MOS capacitor device can be further improved.
As shown in fig. 3e, corresponding to step S15, a first electrode 401 is formed on the side of the gate oxide layer 200 facing away from the SiC substrate 101.
After the annealing treatment is performed on the SiC epitaxial wafer for two times, the first electrode can be formed by adopting the processes of photoetching, sputtering and stripping. Specifically, the SiC epitaxial wafer can be placed in an HMDS oven for 15min, and photoresist is coated on one side of the gate oxide layer, which is far away from the SiC substrate; then carrying out prebaking on the SiC epitaxial wafer at 100 ℃, wherein the prebaking time is 2 min; after cooling for 2min, etching a first electrode pattern on the photoresist by using a photoetching plate corresponding to the first electrode, wherein the front exposure time is 7s, and the reverse exposure time is 65 s; then soaking the SiC epitaxial wafer in a developing solution for developing for 75s, and then performing hot plate hardening at 115 ℃ for 90s to expose a pattern region of the first electrode; and forming an electrode layer with the thickness of 300nm on one side of the photoresist film, which is far away from the SiC epitaxial wafer, by adopting a sputtering process, and finally forming a first electrode with a preset pattern by a photoresist stripping method.
In an embodiment of the invention, the material of the first electrode provided by the invention may be Al, Ti, or NiCr, and the invention is not limited in particular.
As shown in fig. 3f, corresponding to step S16, the sacrificial oxide is removed, 300, and a second electrode 402 is formed on the side of the SiC substrate 101 facing away from the SiC epitaxial layer 102.
After a first electrode is formed, coating photoresist on one side of the first electrode, which is far away from the SiC substrate, for protection, then etching and removing the sacrificial oxide layer by using a diluted hydrofluoric acid solution with the concentration of 5% -10% as a corrosive liquid, and then forming a second electrode with the thickness of 300nm on one side of the SiC substrate, which is far away from the SiC epitaxial layer, by using a sputtering process; and finally, removing the photoresist on the side, away from the SiC substrate, of the first electrode by using an acetone solution, ultrasonically cleaning for 5 minutes by using acetone, ethanol and deionized water in sequence, and blow-drying by using nitrogen to complete the manufacture of the silicon carbide MOS capacitor device.
In an embodiment of the invention, the material of the second electrode provided by the invention may be Al, Ti, or NiCr, and the invention is not limited in particular.
Correspondingly, the invention also provides a silicon carbide MOS capacitor device which is manufactured by adopting the manufacturing method of the silicon carbide MOS capacitor device provided by any one of the embodiments.
The invention provides a silicon carbide MOS capacitor device and a manufacturing method thereof, wherein the method comprises the following steps: providing a SiC epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC substrate and a SiC epitaxial layer positioned on the SiC substrate; carrying out oxidation treatment on the SiC epitaxial wafer to form a gate oxide layer positioned on one side of the SiC epitaxial layer, which is far away from the SiC substrate; carrying out first annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the Ar atmosphere condition or the Ar atmosphere condition containing O elements; carrying out secondary annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the condition of N-containing atmosphere; and forming a first electrode on one side of the gate oxide layer, which is far away from the SiC substrate, and forming a second electrode on one side of the SiC substrate, which is far away from the SiC epitaxial layer.
According to the technical scheme provided by the invention, the first annealing treatment is carried out under the Ar atmosphere condition or the Ar atmosphere condition containing O elements, and further, the C elements at the interface of the SiC epitaxial layer and the gate oxide layer can be removed through the Ar annealing, so that the C element related defects are decomposed and leave the interface position; further annealing under the Ar atmosphere condition containing O element can promote the decomposition and removal of C element related defects; and then, the second annealing treatment is carried out under the condition of the atmosphere containing N, the annealing of the atmosphere containing N can introduce N elements into the interface of the SiC epitaxial layer and the gate oxide layer, so that dangling bonds or other defects existing at the interface can be passivated, the defects at the interface of the gate oxide layer and the SiC epitaxial layer are finally improved, and the reliability of the silicon carbide MOS capacitor device is improved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for manufacturing a silicon carbide MOS capacitor device is characterized by comprising the following steps:
providing a SiC epitaxial wafer, wherein the SiC epitaxial wafer comprises a SiC substrate and a SiC epitaxial layer positioned on the SiC substrate;
carrying out oxidation treatment on the SiC epitaxial wafer to form a gate oxide layer positioned on one side of the SiC epitaxial layer, which is far away from the SiC substrate;
carrying out first annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the Ar atmosphere condition or the Ar atmosphere condition containing O elements;
carrying out secondary annealing treatment on the SiC epitaxial wafer with the gate oxide layer under the condition of N-containing atmosphere;
and forming a first electrode on one side of the gate oxide layer, which is far away from the SiC substrate, and forming a second electrode on one side of the SiC substrate, which is far away from the SiC epitaxial layer.
2. The method of claim 1, wherein the first annealing is performed at an annealing temperature in a range of 1200 ℃ to 1500 ℃, inclusive.
3. The method of claim 1, wherein the second annealing is performed at an annealing temperature in a range of 1200 ℃ to 1500 ℃, inclusive.
4. The method of claim 1, wherein the N-containing atmosphere is NO, N2Atmospheric conditions, NH3Atmosphere(s)Condition or NO2Atmospheric conditions.
5. The method of claim 1, wherein the annealing temperature of the first annealing is higher than the oxidation temperature of the oxidation treatment.
6. The method of claim 1, wherein the second annealing is performed at a lower temperature than the first annealing.
7. The method of claim 1, wherein the oxidation of the SiC epitaxial wafer forms the gate oxide layer and a sacrificial oxide layer on a side of the SiC substrate facing away from the SiC epitaxial layer;
wherein the sacrificial oxide layer is removed before the second electrode is formed.
8. The method of claim 1, wherein the SiC epitaxial wafer is 4H-SiC, 3C-SiC or 6H-SiC.
9. The method of claim 1, wherein the oxidizing of the SiC epitaxial wafer comprises:
and carrying out dry oxygen oxidation treatment on the SiC epitaxial wafer, and carrying out high-temperature treatment at a preset temperature on the SiC epitaxial wafer in an oxygen atmosphere.
10. A silicon carbide MOS capacitor device, characterized in that it is manufactured by the method of manufacturing a silicon carbide MOS capacitor device according to any one of claims 1 to 9.
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