CN111725330A - Preparation method of silicon carbide MOS capacitor gate oxide layer - Google Patents
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
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Abstract
The invention discloses a preparation method of a silicon carbide MOS capacitor device gate oxide, which comprises the following steps: providing a SiC epitaxial wafer; cleaning the SiC epitaxial wafer; oxidizing the cleaned SiC epitaxial wafer to form SiO of the SiC MOS capacitor on the upper surface of the epitaxial wafer2A gate oxide layer with SiO on the lower surface2An oxide layer; annealing the oxidized SiC epitaxial wafer; forming a metal upper electrode on the surface of the annealed upper surface SiC MOS capacitor gate oxide layer; and etching the lower surface oxide layer to form a metal lower electrode. The invention realizes the optimization of the interface defect density and the reliability of the gate oxide layer by improving the annealing temperature in the annealing treatment step, and has simple process, high efficiency and low cost.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a preparation method of a gate oxide layer of a silicon carbide MOS capacitor device.
Background
Compared with a first-generation semiconductor represented by silicon and a second-generation semiconductor represented by gallium arsenide, the third-generation semiconductor material SiC has larger forbidden bandwidth and higher critical breakdown field strength; compared with silicon power devices under the same conditions, the withstand voltage degree of SiC is about 100 times that of silicon materials, and particularly, in recent years, Schottky Barrier Diode (SBD) and Junction Barrier Schottky Diode (JBS) structural products successively introduced by SiC device manufacturers, the withstand voltage range reaches 600V-1700V. Meanwhile, SiC has higher thermal conductivity and lower intrinsic carrier concentration, and can bear junction temperature of about 600 ℃, so that the working temperature limit of the SiC device is greatly improved. In addition, the SiC device has high electronic saturation rate, small forward on-resistance and low power loss, is suitable for large-current and high-power application, and reduces the requirements on heat dissipation equipment. SiC enables formation of silicon dioxide by thermal oxidation more conveniently than other third generation semiconductors such as GaN. Therefore, SiC is considered as an important development direction of a new generation of high-performance power electronic devices, and has wide application prospects in the fields of new energy automobiles, rail transit, locomotive traction, smart power grids and the like.
However, in SiC power devices, the gate oxide layer formed by thermal oxidation may be in SiO2The method has the advantages that a large number of defects such as carbon clusters, oxygen vacancies and the like are introduced into the SiC interface, so that the state density of the interface is greatly increased, the effective mobility of an inversion layer carrier of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is greatly reduced, the reliability of a gate Oxide layer is reduced, and the development and the application of the SiC power device are seriously restricted.
For SiC MOS capacitor, N is used2O、NH3Or gate oxide annealing process is carried out in NO atmosphere, so that the defect density at the interface can be effectively reduced, the interface state density can be reduced, and the interface quality can be improved, thereby improving the inversionEffective mobility of layer carriers and reliability of the gate oxide layer. And an annealing process performed in an NO atmosphere is considered to be the most promising method for improving the interface quality and gate oxide reliability of SiCMOS devices. In order to better improve the interface quality of the SiC MOS and the reliability of the gate oxide layer, the annealing time in NO atmosphere is generally prolonged, and the optimization of the interface defect density and the reliability of the gate oxide layer is realized. However, the method requires a long time, has high cost and low improvement efficiency.
Disclosure of Invention
Technical problem to be solved
In order to overcome the defects of the preparation method, the invention provides the preparation method of the gate oxide of the silicon carbide MOS capacitor device, which can effectively improve the density of nitrogen elements at the interface by prolonging the annealing time so as to improve the interface and the gate oxide and has low efficiency.
(II) technical scheme
The invention provides a preparation method of a silicon carbide MOS capacitor device gate oxide, which comprises the following steps:
providing a SiC epitaxial wafer;
cleaning the SiC epitaxial wafer;
oxidizing the cleaned SiC epitaxial wafer to form SiO of the SiC MOS capacitor on the upper surface of the epitaxial wafer2A gate oxide layer with SiO on the lower surface2An oxide layer;
annealing the oxidized SiC epitaxial wafer;
forming a metal upper electrode on the surface of the annealed upper surface SiC MOS capacitor gate oxide layer;
and etching the lower surface oxide layer to form a metal lower electrode.
In the step of providing the SiC epitaxial wafer, the SiC epitaxial wafer is made of N-type 4H-SiC, 3C-SiC or 6H-SiC; in the step of cleaning the SiC epitaxial wafer, the cleaning method is a standard RCA cleaning method; in the step of oxidizing the cleaned SiC epitaxial wafer, the oxidation treatment is dry oxygen oxidation in oxygenCarrying out 1250-1450 ℃ high-temperature treatment on the silicon carbide epitaxial wafer in the atmosphere, forming a SiC MOS capacitance gate oxide layer on the upper surface of the silicon carbide epitaxial wafer, and forming a lower surface oxide layer on the lower surface of the silicon carbide epitaxial wafer; in the step of annealing the oxidized SiC epitaxial wafer, the annealing treatment is carried out on NO and N2Or NH3The annealing temperature is increased to 1250-1300 ℃ under the atmosphere, so that the optimization of low interface state density and high reliability of the gate oxide layer is realized; the metal electrode is made of Al, Ti or NiCr materials and is prepared by a sputtering process; in the step of etching the lower surface oxide layer, a diluted hydrofluoric acid solution with the percentage concentration of 5% -15% is adopted as a corrosive liquid for etching.
(III) advantageous effects
Compared with the traditional preparation method of the gate oxide layer of the SiC MOS capacitor device, the preparation method of the gate oxide layer of the silicon carbide MOS capacitor device has the advantages that N, O bonds can be separated more easily by increasing the annealing temperature, and Si-N bonds and CO are formed more easily in an annealing process due to O vacancies, C residues and the like at the interface, so that the passivation effect of nitrogen elements is better exerted, and carbon clusters and the like at the interface are reduced, so that a better annealing effect is achieved.
Drawings
Fig. 1A to fig. 1C are schematic diagrams of steps of a process for preparing a gate oxide layer of a SiC MOS capacitor device according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for preparing a silicon carbide MOS capacitor gate oxide layer according to the present invention.
[ description of reference ]
101: SiC substrate
102: epitaxial layer of SiC substrate
103：SiO2Gate oxide layer
104: SiO on the lower surface2Oxide layer
105: metal top electrode
106: metal bottom electrode
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, the problem of the gate oxide layer of the SiC MOS device is the main reason for blocking the commercialization of the SiC MOSFET device, so a mature and repeatable gate oxide preparation method needs to be developed, and because the process of the silicon carbide MOSFET device is complex and the cost and the period are long, the single-step process development of the gate oxide layer of the SiC MOS device is carried out by virtue of the SiC MOS capacitor device, so that the time and the cost are saved, and the same effect is obtained.
The invention provides a preparation method of a silicon carbide MOS capacitor device gate oxide, which comprises the following steps:
providing a SiC epitaxial wafer;
cleaning the SiC epitaxial wafer;
oxidizing the cleaned SiC epitaxial wafer to form SiO of the SiC MOS capacitor on the upper surface of the epitaxial wafer2A gate oxide layer with SiO on the lower surface2An oxide layer;
annealing the oxidized SiC epitaxial wafer;
forming a metal upper electrode on the surface of the annealed upper surface SiC MOS capacitor gate oxide layer;
and etching the lower surface oxide layer to form a metal lower electrode.
In the step of providing the SiC epitaxial wafer, the SiC epitaxial wafer is made of N-type 4H-SiC, 3C-SiC or 6H-SiC; in the step of cleaning the SiC epitaxial wafer, the cleaning method is a standard RCA cleaning method; in the step of oxidizing the cleaned SiC epitaxial wafer, the oxidation treatment is dry oxygen oxidation, and the carbonization is carried out in an oxygen atmosphereCarrying out 1250-1450 ℃ high-temperature treatment on the silicon epitaxial wafer, forming a SiC MOS capacitance gate oxide layer on the upper surface of the silicon carbide epitaxial wafer, and forming a lower surface oxide layer on the lower surface of the silicon carbide epitaxial wafer; in the step of annealing the oxidized SiC epitaxial wafer, the annealing treatment is carried out on NO and N2Or NH3The annealing temperature is increased to 1250-1300 ℃ under the atmosphere, so that the optimization of low interface state density and high reliability of the gate oxide layer is realized; the metal electrode is made of Al, Ti or NiCr materials and is prepared by a sputtering process; in the step of etching the lower surface oxide layer, a diluted hydrofluoric acid solution with the percentage concentration of 5% -15% is adopted as a corrosive liquid for etching.
Compared with the traditional preparation method of the gate oxide of the SiC MOS capacitor device, the preparation method of the gate oxide of the SiC MOS capacitor device provided by the invention has the advantages that the higher surface density of the passivation element is realized by annealing the SiC MOS capacitor gate oxide at higher temperature, so that the interface state density is reduced and the reliability of the gate oxide is improved.
In particular, the invention characterizes the gate oxide layer of the SiC MOS device by the SiC MOS capacitor device.
In order to further explain the preparation method of the gate oxide layer of the silicon carbide MOS capacitor device, the embodiment is specifically illustrated. Fig. 1A to 1C show a structure diagram of steps of a process for manufacturing a SiC MOS capacitor according to the present invention, and fig. 1A shows a schematic structural diagram of an epitaxial wafer material of a SiC MOS capacitor after cleaning and etching according to an embodiment of the present invention; as shown in FIG. 1B, SiO is grown on the upper surface of the SiC epitaxial material2A gate oxide layer 103, and a lower surface SiO grown by oxidation on the lower surface2An oxide layer 104; as shown in FIG. 1C, a metal upper electrode 105 is grown on the upper surface of the annealed SiC epitaxial wafer, and a SiO layer is formed on the lower surface2Oxidized 104 and then sputtered to form a metal bottom electrode 106.
With reference to fig. 2, the steps of preparing the gate oxide layer of the SiC MOS capacitor device provided in this embodiment are as follows:
step S201, the SiC substrate 101 and the N-type 4H-SiC material with higher breakdown electric field intensity and higher carrier mobility on the silicon surface of the substrate 101 are used as the epitaxial layer 102 in one embodiment of the invention, the thickness of the epitaxial layer is 12 microns, and the doping concentration is 8 × 1015cm-3。
Step S202: and cleaning the 4H-SiC epitaxial wafer by adopting a standard RCA cleaning method. Specifically, the method comprises the following steps: first, a SiC epitaxial wafer was immersed in a solution of 1: 1 of 98 wt% concentrated sulfuric acid and 27 wt% hydrogen peroxide, heating in water at 80-90 deg.c for 15-30 min, washing with deionized water, and adding N2Drying; then, soaking the SiC epitaxial wafer in a mixed solution of 28 wt% ammonia water and 27 wt% hydrogen peroxide in a volume ratio of 1: 1, heating the mixed solution in a water area at the temperature of 80-90 ℃ for 15-30 min, washing the mixed solution with deionized water, and then carrying out N2Drying; finally, the SiC epitaxial wafer is immersed in a mixed solution of 10 wt% hydrochloric acid and 27 wt% hydrogen peroxide in a volume ratio of 1: 1, heated in a water area at a temperature of 80-90 ℃ for 15-30 min, washed by deionized water, and subjected to N2And (5) drying.
Step S203: in one embodiment of the present invention, nitrogen (N) is first utilized2) Evacuating the air in the oxidation furnace to N2Putting the cleaned SiC epitaxial wafer into a quartz boat under protection, slowly pushing the quartz boat into an oxidation furnace constant-temperature area in an environment with the temperature of 650-750 ℃, heating the constant-temperature area at the speed of 5 ℃/min, slowly introducing oxygen when the temperature is raised to 1250-1450 ℃, and oxidizing the SiC epitaxial wafer in pure dry oxygen atmosphere to form SiO with the thickness of 45-60 nm 2103 gate oxide layer and 450nm-600nm lower surface SiO2And (6) an oxide layer 104.
Step S204: and turning off the oxygen, cooling the constant temperature area under the protection of nitrogen, and slowly pulling out the quartz boat to take out the SiC epitaxial wafer. For the oxidized SiC epitaxial wafer in NO and N2Or NH3Annealing is carried out in the atmosphere, and the annealing temperature is 1250-1300 ℃.
Step S205: placing the annealed SiC epitaxial wafer in an HMDS oven for 15min, coating photoresist on the front surface, prebaking the SiC epitaxial wafer coated with the photoresist at 100 ℃, wherein the prebaking time is 2min, cooling for 2min, and then etching a gate pattern on the SiC epitaxial wafer by using a gate electrode photomask, wherein the prebaking time is 7s, and the reverse exposure time is 65 s; then soaking the SiC epitaxial wafer in a developing solution for developing for 75s, carrying out hot plate hardening at 115 ℃ for 90s, and exposing an effective grid contact area; a circular metal upper electrode 105 with the thickness of 300nm and the diameter of 300 mu m is formed on the upper surface of the SiC epitaxial wafer by adopting a sputtering process, and finally a gate electrode pattern is formed by a stripping method.
Step S206: coating photoresist on the front surface of the SiC epitaxial wafer with a front gate electrode formed by sputtering for protection, and adopting a diluted hydrofluoric acid solution with the concentration of 5-10% as an etching solution to carry out SiO etching on the lower surface2After the oxide layer 104 is etched, an Al metal lower electrode 106 with the thickness of 300nm is sputtered on the lower surface by adopting a sputtering process; removing the photoresist on the front surface by using an acetone solution, ultrasonically cleaning by using new acetone, ethanol and deionized water in sequence, and then using N2And drying to finish the manufacture of the SiC MOS capacitor device.
In particular, the embodiment provides two groups of embodiments for annealing the gate oxide layer under the NO condition under the processes of 1250 ℃, 30min, 1300 ℃ and 30min, and two groups of comparative examples for annealing the gate oxide layer under the NO condition under the process conditions of 1200 ℃, 30min, 1200 ℃ and 120min, respectively, and the gate oxide layer breakdown electric field intensity (E) of the SiC MOS capacitor is obtained by the four groups of processesBD) Amount of breakdown charge (Q)BD) Effective barrier height (phi)B) As shown in table 1.
TABLE 1
As can be seen from the comparison of the data in Table 1, the area density of the passivated nitrogen element near the gate oxide layer prepared by adopting the gate oxide layer NO annealing process conditions of 1300 ℃ and 30min in one embodiment of the invention is nearly the same as that of the passivated nitrogen element near the gate oxide layer prepared by adopting the gate oxide layer NO annealing process conditions of 1200 ℃ and 120min, but the SiO element is at the moment2Lower density of/SiC interface states and higher breakdown field strength (E)BDAbout 10.09MV/cm), amount of breakdown charge (Q)BDAbout 0.2223C/cm2) Effective barrier height (phi)BAbout 2.72eV), indicating that the method of increasing the surface density of the passivating nitrogen element by increasing the annealing temperature is more effective in improving the interface state density and the gate oxide reliability than the method of increasing the annealing time.
Therefore, compared with the traditional preparation method of the gate oxide layer of the SiC MOS capacitor device, the preparation method of the gate oxide layer of the SiC MOS capacitor device with low interface state density and high reliability provided by the invention has the advantages that the higher surface density of the passivation element is realized by annealing the gate oxide layer of the SiC MOS capacitor device at higher temperature, so that the interface state density is reduced and the reliability of the gate oxide layer is improved. And compared with the process of obtaining the surface density of the passivated nitrogen element by increasing the annealing time, the process has better effect, simple process and low cost.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A preparation method of a gate oxide layer of a silicon carbide MOS capacitor device comprises the following steps:
providing a SiC epitaxial wafer;
cleaning the SiC epitaxial wafer;
oxidizing the cleaned SiC epitaxial wafer to form SiO of the SiC MOS capacitor on the upper surface of the epitaxial wafer2A gate oxide layer with SiO on the lower surface2An oxide layer;
annealing the oxidized SiC epitaxial wafer;
forming a metal upper electrode on the surface of the annealed upper surface SiC MOS capacitor gate oxide layer;
and etching the lower surface oxide layer to form a metal lower electrode.
2. The method for preparing the gate oxide layer of the silicon carbide MOS capacitor device according to claim 1, wherein in the step of providing the SiC epitaxial wafer, the material of the SiC epitaxial wafer is N-type 4H-SiC, 3C-SiC or 6H-SiC.
3. The method for preparing the gate oxide layer of the silicon carbide MOS capacitor device according to claim 1, wherein in the step of cleaning the SiC epitaxial wafer, the cleaning method is a standard RCA cleaning method.
4. The method for preparing a gate oxide layer of a silicon carbide MOS capacitor according to claim 1, wherein in the step of subjecting the cleaned SiC epitaxial wafer to an oxidation treatment, the oxidation treatment is dry oxygen oxidation, the silicon carbide epitaxial wafer is subjected to a high temperature treatment of 1250 ℃ to 1450 ℃ in an oxygen atmosphere, a SiCMOS capacitor gate oxide layer is formed on the upper surface of the silicon carbide epitaxial wafer, and a lower surface oxide layer is formed on the lower surface of the silicon carbide epitaxial wafer.
5. The method of claim 1, wherein the step of annealing the oxidized SiC epitaxial wafer comprises annealing NO, N2 or NH3The annealing temperature is increased to 1250-1300 ℃ under the atmosphere, and the optimization of low interface state density and high reliability of the gate oxide layer is realized.
6. The method for preparing the gate oxide layer of the silicon carbide MOS capacitor device according to claim 1, wherein the metal electrode is made of Al, Ti or NiCr material by a sputtering process.
7. The method for preparing a gate oxide layer of a silicon carbide MOS capacitor as claimed in claim 1, wherein the step of etching the lower surface oxide layer is performed by etching with a diluted hydrofluoric acid solution having a percentage concentration of 5% -15% as an etching solution.
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