CN213150782U - Silicon carbide oxide field effect transistor with groove structure - Google Patents

Abstract

The utility model relates to a silicon carbide oxide field effect transistor with a groove structure, which is provided with an n + type SiC substrate, an n-type SiC layer and an insulating layer from bottom to top in sequence; the lower end face of the n + type SiC substrate is provided with a drain electrode; a p + type buried layer is arranged at the position, close to the n-type SiC layer, of the n-type SiC layer; the n-type SiC layer is provided with a p-type epitaxial layer and a protective ring-shaped junction, the p-type epitaxial layer is provided with a p + ground electrode, an n + source electrode and a grid groove, and a grid bottom insulating layer, a groove grid oxidation insulating layer and an n + polycrystalline electrode are arranged in the grid groove; and a source metal electrode and a grid metal electrode are arranged on the insulating layer, and the source metal electrode is in contact with the n + polycrystalline electrode. The utility model discloses form high concentration doping p + type somatic layer bottom the slot to the insulating film on protection gate region bottom surface. In addition, a method of oxidizing an insulating layer at a sidewall of a trench to reduce defects and fix a thickness, thereby improving performance and producing a highly reliable device.

Description

Silicon carbide oxide field effect transistor with groove structure

Technical Field

The utility model relates to the field of semiconductor technology, concretely relates to groove structure carborundum silicon oxide field effect transistor.

Background

SiC power semiconductors have excellent material characteristics compared to currently used silicon power semiconductors, and thus are widely used in high-current switching devices such as hybrid power (HV) and Electric Vehicles (EV), consumer electronics and industrial inverters, solar inverters, discontinuous power supplies (UPS), and the like, and in particular, in motor integrated control devices in the field of electric vehicles, it is expected that high-frequency, low-noise, small and light inverters will be obtained.

In a conventional general conventional SiC trench MOSFET device, an active region n-type SiC layer and a p-type body SiC layer are grown on an n + type SiC substrate as doped high concentrations, and a source region and a ground region are sequentially formed to form a source electrode. In addition, after a gate insulating film trench gate oxide (insulating) layer is formed on the sidewall and the bottom surface of the trench gate region, an n + polycrystalline electrode is filled in the trench, followed by growing a drain electrode structure and forming a gate. The reliability of such a device structure is a significant problem, and the internal electric field is concentrated on the trench bottom surface, which results in a high current density and a vulnerable region.

SUMMERY OF THE UTILITY MODEL

Problem to prior art existence, the utility model aims to provide a groove structure carborundum oxide field effect transistor, its easy destruction problem that can solve the strong electric field and cause improves field effect transistor's reliability.

In order to achieve the above object, the utility model adopts the following technical scheme:

a silicon carbide oxide field effect transistor with a groove structure is provided with an n + type SiC substrate, an n-type SiC layer and an insulating layer in sequence from bottom to top;

a drain electrode metal electrode is arranged on the lower end face of the n + type SiC substrate;

a p + type buried layer is arranged at the position, close to the n-type SiC layer, of the n-type SiC layer;

the n-type SiC layer is provided with a p-type epitaxial layer and a protective ring-shaped junction, the p-type epitaxial layer is provided with a p + ground electrode, an n + source electrode and a grid groove, and a grid bottom insulating layer, a groove grid oxidation insulating layer and an n + polycrystalline electrode are arranged in the grid groove;

and a source metal electrode and a grid metal electrode are arranged on the insulating layer, and the source metal electrode is in contact with the n + polycrystalline electrode.

The insulating layer includes an oxide layer and an ILD insulating layer, the oxide layer being in contact with the n-type SiC layer.

After the scheme of the oil adding device is adopted, the utility model discloses adopt double-deck epitaxial technology in double groove grid MOSFET device, the electric field intensity of dispersion grid insulating film forms high concentration and dopes p + type somatic layer bottom the ditch slot to the insulating film on protection gate district bottom surface. In addition, the method of oxidizing the insulating layer on the side wall of the trench by N2O gas directly by LPCVD at high temperature is used to reduce defects and fix the thickness, thereby improving the performance and producing highly reliable devices.

Drawings

FIG. 1 is a schematic diagram of a first step of the field effect transistor fabrication of the present invention;

FIG. 2 is a schematic diagram of a second step of manufacturing the field effect transistor of the present invention;

FIG. 3 is a schematic diagram of a third step of manufacturing the field effect transistor of the present invention;

FIG. 4 is a schematic diagram of a fourth step of manufacturing the field effect transistor of the present invention;

FIG. 5 is a schematic diagram of a fifth step of manufacturing the field effect transistor of the present invention;

fig. 6 is a schematic diagram of a sixth step of manufacturing the fet according to the present invention;

fig. 7 is a schematic diagram of a seventh step of manufacturing the fet according to the present invention;

fig. 8 is a schematic view of an eighth step of manufacturing the fet according to the present invention;

fig. 9 is a schematic view of a ninth step of manufacturing the field effect transistor of the present invention;

fig. 10 is a schematic view of the field effect tube structure after the preparation of the present invention.

Detailed Description

As shown in fig. 1 to 10, the present invention discloses a silicon carbide oxide field effect transistor with a trench structure, which is provided with an n + type SiC substrate 1, an n-type SiC layer 2, an n-type SiC layer 3, and an insulating layer in sequence from bottom to top;

a drain electrode metal electrode 14 is arranged on the lower end face of the n + type SiC substrate 1;

a p + type buried layer 15 is arranged at the position, close to the n-type SiC layer 3, of the n-type SiC layer 2;

the n-type SiC layer 3 is provided with a p-type epitaxial layer 4 and a protective ring-shaped junction 13, the p-type epitaxial layer 4 is provided with a p + ground 6, an n + source 5 and a grid groove 8, and a grid bottom insulating layer 12, a groove grid oxidation insulating layer 9 and an n + polycrystalline electrode 10 are arranged in the grid groove 8;

and a source metal electrode 7 and a gate metal electrode 11 are arranged on the insulating layer, and the source metal electrode 7 is in contact with the n + polycrystalline electrode 10.

With continuing reference to fig. 1-10, the method of making silicon carbide oxide fets of the present invention is as follows:

step 1, growing an n-type SiC layer 2 on an n + type SiC substrate 1, and then depositing an oxide film on the n-type SiC layer 2 by a CVD (chemical deposition) method; covering a layer of photoresist, photoetching the position of the p + type buried layer 15, and etching SiC of 5 um; finally, high concentration aluminum (Al) was injected at a temperature of 600 ℃ to the photo-etched position.

Step 2, removing the oxide film shielded in the previous step, growing an n-type SiC layer 3 on the n-type SiC layer 2 by a CVD method at a high temperature, and then growing an oxide film on the n-type SiC layer 3 by applying the CVD method again; then covering a layer of photoresist, photoetching a protection area, and injecting aluminum doping into the protection area at high temperature.

And 3, removing the shielded oxide film in the previous step, covering the oxide film and the photoresist again, photoetching the defined position of the p-type body epitaxial layer 4, and injecting aluminum dopant into the photoetching position at the temperature of 600 ℃.

And 4, covering photoresist after the previous step is completed, photoetching the defined position of the N + source 5, and injecting N-nitrogen doping substances into the defined position of the N + source 5 at the temperature of 600 ℃. Removing the oxide film shielded in the previous step, covering the oxide film and the photoresist again, photoetching the defined position of the p + grounding 6, and injecting aluminum doping into the defined position of the p + grounding 6 at the temperature of 600 ℃.

And 5, removing the shielded oxide film in the previous step, covering a layer of photoresist again, heating at 1600-1700 ℃ for 30 minutes-1 hour, and activating the impurities doped in the steps 1-4 to form a p + type buried layer 15, a protective ring type junction 13 (at a protective region), a p type epitaxial layer 4, an n + source 5 and a p + ground 6. At high temperatures, the photoresist graphitizes (burns); the graphite covering the surface can prevent the silicon carbide on the surface from sublimating.

And 6, removing the graphite layer in the previous step by utilizing O2 plasma and oxidation reaction, sequentially generating an oxide film, polysilicon and the oxide film by a CVD method, defining the position of a trench gate region, further removing photoresist at the position by wet etching, etching the trench 8 of the gate region to the level of 1.5-2.0 um, and etching and sacrificially oxidizing the U-shaped trench 8 (sacrificial oxidation). An oxide layer is further applied by LPCVD (Low Pressure Chemical Vapor Deposition), and then a thermal hardening treatment is performed by introducing nitrogen gas (N2) at 1100 ℃ and atmospheric Pressure, and the thickness of the oxide film at the bottom of the trench (i.e., the gate bottom insulating layer 12) is maintained at 500nm to 1 μm.

And 7, growing the silicon nitride layer on the U-shaped grid groove 8 in a gas growth modeOxidizing the insulating layer 9 by a 50-100 nm groove grid, introducing mixed gas of N2O (10%) and N2 at 1250 ℃, enabling mixed nitrogen to pass through a defect opening originally existing in a SiC/SiO2 contact surface to form oxynitride, and ensuring that interface defects (Dit) are less than 5x10¹¹. After cleaning the nitride film on the surface with phosphoric acid, performing CMP (chemical mechanical polishing) and RIE (reactive ion etching) to remove the oxide film on the surface; an n + polycrystalline electrode 10 is grown.

And 8, growing a BPSG film by LPCVD (low pressure chemical vapor deposition) and HTO (High Temperature Oxidation), and then introducing nitrogen (N2) at the atmospheric pressure of 900 ℃ to grow an ILD insulating layer. Then covering photoresist protection on the ILD insulating layer; alternately stacking an oxide film and polysilicon on the lower surface of the n + type SiC substrate 1 to a required thickness; and then polishing by CMP, plating nickel metal, and then performing RTP (rapid thermal processing) process for 3 minutes at 1000 ℃ under the atmosphere of atmospheric pressure argon to form ohmic contact.

Step 9, defining the position of the upper source metal electrode 7, and etching the source region of the ILD insulating layer by dry and wet etching. Sequentially and alternately stacking the oxide film and the polysilicon to a required thickness, plating nickel metal, and then performing an RTP (rapid thermal processing) process for 3 minutes at 1000 ℃ under an atmosphere of atmospheric pressure argon to form ohmic contact.

Step 10, cleaning the upper surface with hydrofluoric acid, and plating a TiW/AlSi alloy thick film; and dry-etching to obtain the required gate metal electrode 11 and source metal electrode 7. The lower surface of the N + -type SiC substrate 1 was cleaned with hydrofluoric acid by passing H2/N2 at 450 ℃ under atmospheric pressure, a Ti/Ag film was plated by electron beam to form a drain metal electrode 14, and then heat treatment was performed to complete the metal electrode arrangement.

The utility model discloses an adopt double-deck epitaxial technology in double groove grid MOSFET device, disperse the electric field intensity of grid insulating film, form high concentration doping p + type body layer bottom the ditch slot to the insulating film on protection gate region bottom surface. In addition, the method of oxidizing the insulating layer on the side wall of the trench by N2O gas directly by LPCVD at high temperature is used to reduce defects and fix the thickness, thereby improving the performance and producing highly reliable devices.

The above description is only an embodiment of the present invention, and is not intended to limit the technical scope of the present invention, so that any slight modifications, equivalent changes and modifications made by the technical spirit of the present invention to the above embodiments are all within the scope of the technical solution of the present invention.

Claims (2)

1. A silicon carbide oxide field effect transistor with a groove structure is characterized in that: an n + type SiC substrate, an n-type SiC layer and an insulating layer are sequentially arranged from bottom to top;

a drain electrode metal electrode is arranged on the lower end face of the n + type SiC substrate;

a p + type buried layer is arranged at the position, close to the n-type SiC layer, of the n-type SiC layer;

the n-type SiC layer is provided with a p-type epitaxial layer and a protective ring-shaped junction, the p-type epitaxial layer is provided with a p + ground electrode, an n + source electrode and a grid groove, and a grid bottom insulating layer, a groove grid oxidation insulating layer and an n + polycrystalline electrode are arranged in the grid groove;

and a source metal electrode and a grid metal electrode are arranged on the insulating layer, and the source metal electrode is in contact with the n + polycrystalline electrode.

2. The silicon carbide oxide field effect transistor with a trench structure of claim 1, wherein: the insulating layer includes an oxide layer and an ILD insulating layer, the oxide layer being in contact with the n-type SiC layer.

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