CN113488542B - Groove type SiC MOSFET device and preparation method thereof - Google Patents
Groove type SiC MOSFET device and preparation method thereof Download PDFInfo
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- 235000012239 silicon dioxide Nutrition 0.000 claims description 26
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- 238000005468 ion implantation Methods 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
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- 238000009616 inductively coupled plasma Methods 0.000 claims description 10
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- 238000000059 patterning Methods 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 24
- 230000015556 catabolic process Effects 0.000 abstract description 11
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- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The invention discloses a groove type SiC MOSFET device and a preparation method thereof, wherein a column region electric field modulation structure is introduced into the groove type SiC MOSFET device, so that electric field distribution at the bottom of a groove can be effectively relieved, an electric field aggregation effect is eliminated, the electric field intensity in gate oxide can be shielded, the electric field intensity in gate oxide is reduced, gate oxide breakdown is avoided, premature breakdown and burnout of the device are prevented, and the reliability of the device is improved. In addition, the device structure and the preparation method are simple, the effect is obvious, the preparation and the production of high-performance and batched groove type SiC MOSFET devices can be realized, and the device has huge market potential and wide application prospect.
Description
Technical Field
The invention relates to a groove type SiC MOSFET device and a preparation method thereof, belonging to the technical field of semiconductor component preparation.
Background
SiC has a series of excellent characteristics of large forbidden bandwidth, high critical breakdown electric field strength, high thermal conductivity, and the like as a third generation semiconductor material. The SiC power device can simultaneously realize excellent performances of high breakdown voltage, low on-resistance, high switching speed, easy heat dissipation and the like, has obvious competitiveness in the high-energy-efficiency, high-power and high-temperature power electronic technology, and has become a research hot spot of the current power semiconductor technology. With the continuous increase of energy crisis and the increasingly prominent environmental problems, the technology with energy conservation and emission reduction as the core is continuously emerging, and the technical field of improving the energy utilization rate by improving the existing power system is most interesting. It is counted that 60% to 70% of the electrical energy is used in low energy systems, and most of it is wasted in power conversion and power driving. A key role in improving power utilization efficiency is power devices, also known as power electronics. How to reduce the power consumption of a power device has become a global important issue. In this context, siC devices having properties far superior to those of conventional silicon devices are favored.
In a conventional planar gate SiC MOSFET device, the on-resistance of the device increases due to the presence of parasitic junction field effect transistor structures. The groove gate type SiC MOSFET has no JFET region, the on-resistance of the device can be obviously reduced, and the power density of the device can be further improved along with the reduction of the cell area of the device, so that the groove gate type SiC MOSFET has obvious performance advantages and wide application prospect. However, trench SiC MOSFET devices are very susceptible to premature breakdown and even burn-out of the device due to the effects of electric field concentration at the trench bottom corners. In addition, the high electric field in the gate oxide at the bottom of the groove is extremely easy to cause gate oxide breakdown, so that the device is invalid.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a groove type SiC MOSFET device and a preparation method thereof, wherein the structure and the preparation method are simple, the electric field at the bottom of a groove of the groove type SiC MOSFET device is effectively modulated, and the risk of gate oxide breakdown is reduced.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
in a first aspect, the present invention provides a method for fabricating a trench SiC MOSFET device, comprising the steps of:
providing a heavily doped substrate of a first doping type, and forming a lightly doped epitaxial layer of the first doping type on the upper surface of the substrate;
forming a column region of a second doping type in the epitaxial layer;
forming a well region with a second doping type in the epitaxial layer, and forming a source region with a first doping type in the well region;
forming a gate trench in the epitaxial layer;
forming a gate dielectric layer in the gate trench;
filling polysilicon of a first doping type on the surface of the gate dielectric layer in the gate trench;
forming a passivation layer on the surface of the epitaxial layer, and forming a source window in the passivation layer;
forming a source ohmic contact layer in the source window, and forming a drain ohmic contact layer on the bottom surface of the substrate;
forming a gate window in the passivation layer at a position corresponding to the polysilicon region;
and forming a gate electrode in the gate window, forming a source electrode on the surface of the source ohmic contact layer, and forming a drain electrode on the surface of the drain ohmic contact layer.
With reference to the first aspect, further, the forming a pillar region of the second doping type in the epitaxial layer includes the following steps:
forming an ion implantation mask layer on the surface of the epitaxial layer;
coating photoresist on the upper surface of the ion implantation mask layer, and performing patterning treatment to form patterned photoresist;
etching the ion implantation mask layer in the patterned photoresist by adopting an etching process to form an ion implantation window;
removing the patterned photoresist, and reserving the ion implantation mask layer after etching treatment;
according to the ion implantation mask layer after etching treatment, carrying out an aluminum ion implantation process on the epitaxial layer to form a column region;
and removing the ion implantation mask layer after the etching treatment.
Further, a gate trench is formed in the epitaxial layer, including the following steps:
growing an etching mask layer on the surface of the epitaxial layer through a chemical vapor deposition process;
coating photoresist on the surface of the etching mask layer, and performing patterning treatment to form patterned photoresist;
performing reactive ion etching on the etching mask layer in the patterned photoresist to form a patterned etching mask layer;
removing the patterned photoresist, and performing inductively coupled plasma etching on the epitaxial layer according to the patterned etching mask layer to form a gate trench;
removing the patterned etching mask layer;
and performing high-temperature passivation treatment on the epitaxial layer, and performing morphology modification on the gate trench.
Further, a gate dielectric layer is formed in the gate trench, and the method comprises the following steps:
growing a first silicon dioxide layer on the surface of the gate groove by utilizing a thermal oxidation process;
growing a second silicon dioxide layer on the surface of the first silicon dioxide layer formed by the thermal oxidation process by utilizing a low-pressure chemical vapor deposition process;
annealing the first silicon oxide layer and the second silicon oxide layer;
further, the surface of the gate dielectric layer in the gate trench is filled with polysilicon of the first doping type, which comprises the following steps:
growing polysilicon of a first doping type on the surface of the gate dielectric layer by utilizing a low-pressure chemical vapor deposition process;
and sequentially etching the polysilicon of the first doping type and the gate dielectric layer by utilizing an ICP etching process, and removing the polysilicon and the gate dielectric layer in the area outside the gate groove.
In a second aspect, the present invention provides a trench SiC MOSFET device comprising:
a heavily doped substrate of a first doping type;
a lightly doped epitaxial layer of a first doping type on the upper surface of the substrate;
a second doping type column region located in the epitaxial layer;
a well region of a second doping type located in the epitaxial layer;
a source region of a first doping type located in the well region;
a gate trench in the epitaxial layer;
the gate dielectric layer is positioned in the gate groove;
polysilicon of a first doping type is filled on the surface of the gate dielectric layer in the gate trench;
a passivation layer on the surface of the epitaxial layer between the source electrode and the gate electrode;
the source ohmic contact layer is positioned on the surfaces of the source region of the first doping type and the column region of the second doping type;
the drain ohmic contact layer is positioned on the lower surface of the substrate;
a gate electrode located on the upper surface of the polysilicon;
the source electrode is positioned on the upper surface of the source ohmic contact layer;
and the drain electrode is positioned on the lower surface of the drain ohmic contact layer.
With reference to the second aspect, further, the second doping type column region has a depth of 1.8-3.0 μm, a width of 0.4-1.2 μm, and a doping concentration of 1e 17-1 e19cm -3 。
Further, the first doping type source region has a depth of 0.2-0.5 μm, a width of 0.5-1.5 μm, and a doping concentration of 1e 19-1 e21cm -3 The source region of the first doping type is connected with the column region of the second doping type.
Further, the width of the gate trench is 0.6-2.0 μm, and the depth is 0.6-2.5 μm.
Further, the gate dielectric layer is a composite layer of a first oxide layer and a second oxide layer, the thickness of the gate dielectric layer positioned on the side wall of the gate groove is 40-60 nm, and the thickness of the gate dielectric layer positioned at the bottom of the gate groove is 80-120 nm.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the column region is introduced into the groove type SiC MOSFET device as an electric field modulation structure, so that the electric field distribution at the bottom of the groove is effectively relaxed, the electric field aggregation effect at the bottom corner of the groove is eliminated, the electric field intensity in the gate oxide can be shielded, the breakdown of the gate oxide is avoided, the premature breakdown and burning of the device are prevented, and the running reliability of the device is improved;
the device structure and the preparation method are simple, the effect is obvious, the preparation and the production of high-performance and batched groove type SiC MOSFET devices can be realized, and the device has huge market potential and wide application prospect.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a trench SiC MOSFET device according to an embodiment of the present invention;
fig. 2 is a schematic structural view of a lightly doped epitaxial layer of a first doping type formed on an upper surface of a substrate;
FIG. 3 is a schematic diagram of a structure for forming a pillar region of a second doping type in an epitaxial layer;
FIG. 4 is a schematic diagram of a structure of a source region of a first doping type formed in a well region;
fig. 5 is a schematic diagram of a structure for forming a gate trench in an epitaxial layer;
FIG. 6 is a schematic diagram of a structure in which a gate dielectric layer is formed in a gate trench;
FIG. 7 is a schematic diagram of a structure in which the surface of a gate dielectric layer in a gate trench is filled with polysilicon of a first doping type;
FIG. 8 is a schematic diagram of a structure of a passivation layer with a source window formed therein;
fig. 9 is a schematic structural diagram of forming a source ohmic contact layer in a source window and forming a drain ohmic contact layer on a bottom surface of the substrate;
fig. 10 is a schematic structural view of forming a gate window in the passivation layer at a position corresponding to the polysilicon region;
fig. 11 is a schematic structural diagram of a trench SiC MOSFET device according to an embodiment of the present invention;
in the figure: 101. a substrate; 102. a buffer layer; 103. an epitaxial layer; 104. a column region; 105. a well region; 106. a source region; 107. a gate trench; 108. a gate dielectric layer; 109. polycrystalline silicon; 110. a passivation layer; 111. a source window; 112. a source ohmic contact layer; 113. a drain ohmic contact layer; 114. a gate window; 115. a gate electrode; 116. a source electrode; 117. and a drain electrode.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art in a specific case.
As shown in fig. 1, a flow chart of a method for manufacturing a trench SiC MOSFET device according to the present invention includes the following steps:
1) Providing a heavily doped substrate 101 of a first doping type, and forming a lightly doped epitaxial layer 103 of the first doping type on the upper surface of the substrate 101;
2) Forming a second doping type column region 104 in the epitaxial layer 103;
3) Forming a well region 105 of a second doping type in the epitaxial layer 103 obtained by completing the step 2), and forming a source region 106 of a first doping type in the well region 105;
4) Forming a gate trench 107 in the epitaxial layer 103 obtained by completing the step 3);
5) Forming a gate dielectric layer 108 on the surface of the gate trench 107;
6) Filling polysilicon 109 of a first doping type on the surface of the gate dielectric layer 108 in the gate trench 107 obtained in the step 5);
7) Forming a passivation layer 110 on the surface of the epitaxial layer 103 obtained in the step 6), and forming a source window 111 in the passivation layer 110;
8) Forming a source ohmic contact layer 112 in the source window 111, and forming a drain ohmic contact layer 113 on the bottom surface of the substrate;
9) Forming a gate window 114 in the passivation layer 110 at a position corresponding to the polysilicon 109;
10 A gate electrode 115 is formed in the gate window 114, a source electrode 116 is formed on the surface of the source ohmic contact layer 112, and a drain electrode 117 is formed on the surface of the drain ohmic contact layer 113.
Fig. 2 to 11 are schematic structural diagrams of a trench SiC MOSFET device according to each step of the method for manufacturing a trench SiC MOSFET device according to an embodiment of the present invention.
As shown in fig. 2, a schematic structure of forming a lightly doped epitaxial layer of a first doping type on an upper surface of a substrate is shown, providing a heavily doped substrate 101 of the first doping type, and forming a lightly doped epitaxial layer 103 of the first doping type on the upper surface of the substrate.
In this embodiment, the step 1) further includes a step of forming a buffer layer 102 between the substrate 101 and the epitaxial layer 103, and the epitaxial layer 103 is formed on an upper surface of the buffer layer 102.
It should be noted that the buffer layer 102 is used to assist the epitaxial layer 103 and the substrate 101 to better achieve concentration matching, so that the doping concentration of the epitaxial layer 103 can be accurately controlled during the growth process.
In one aspect, the material of the epitaxial layer 103 may be the same as the material of the substrate 101, for example, the material of the substrate 101 and the material of the epitaxial layer 103 are one of 4H-SIC, 6H-SIC, or 3C-SIC; in this embodiment, the material of the substrate 101 and the material of the epitaxial layer 103 are both 4H-SIC; further, in this embodiment, the crystal orientation of the material of the substrate 101 is deviated by 4 degrees ±0.5 degrees from the (11-20) direction.
On the other hand, the material of the epitaxial layer 103 may be different from the material of the substrate 101, for example, the material of the substrate 101 may be one of monocrystalline silicon, polycrystalline silicon, sapphire and gallium arsenide, and the material of the epitaxial layer 103 may be one of 4H-SIC, 6H-SIC or 3C-SIC.
As shown in fig. 3, a schematic structure of forming a second doping type pillar region in the epitaxial layer is shown, and forming a second doping type pillar region 104 in the epitaxial layer 103.
In step 2), a second doping type pillar region 104 is formed in the epitaxial layer 103, including the steps of:
2-1) forming an ion implantation mask layer on the surface of the epitaxial layer 103;
2-2) coating photoresist on the upper surface of the ion implantation mask layer, and carrying out patterning treatment on the photoresist by adopting photoetching processes such as exposure, development, hardening and the like so as to form patterned photoresist;
2-3) etching the ion implantation mask layer by adopting an etching process according to the patterned photoresist to form an ion implantation window;
2-4) removing the patterned photoresist and reserving the etched ion implantation mask layer;
2-5) performing an aluminum ion implantation process on the epitaxial layer according to the etched ion implantation mask layer to form a column region 104;
2-6) removing the etched ion implantation mask layer.
After the pillar region 104 is formed by performing an aluminum ion implantation process on the epitaxial layer 103, a high-temperature activation process is performed on the implanted aluminum ions to activate the implanted aluminum ions to form an effective acceptor doping.
As shown in fig. 4, a schematic structure of forming a source region of a first doping type in a well region is shown, forming a well region 105 of a second doping type in the epitaxial layer 103 obtained by completing the step 2), and forming a source region 106 of the first doping type in the well region.
The source region 106 of the first doping type is connected to the column region 104 of the second doping type.
As shown in fig. 5, a schematic structure of forming a gate trench in the epitaxial layer is shown, and a gate trench 107 is formed in the epitaxial layer 103 obtained by completing the step 3).
Further, in step 4), forming a gate trench 107 in the epitaxial layer 103 obtained in step 3) includes the following steps:
4-1) growing an etching mask layer on the surface of the epitaxial layer, and growing compact and uniform SiO through a chemical vapor deposition process (Chemical Vapor Deposition, CVD) 2 The film thickness is 0.8 to 1.5 μm, preferably 0.9 to 1.0 μm, and in this example, 1.0 μm is selected;
4-2) coating photoresist on the surface of the etching mask layer, and forming a patterned photoresist layer by adopting photoetching processes such as exposure, development, hardening and the like;
4-3) performing reactive ion (Reactive Ion Etching, RIE) etching on the etching mask layer according to the patterned photoresist layer to form a patterned etching mask layer;
4-4) removing the patterned photoresist layer, and performing inductively coupled plasma (Inductively Coupled Plasma, ICP) etching on the epitaxial layer according to the patterned etching mask layer, wherein the etching gas is SF 6 /O 2 The flow ratio is 5:1-2:1, preferably 3:1-2:1, in this embodiment, 2:1, the total flow of the gas is 10-25 sccm, preferably 15-20 sccm, in this embodiment, 18sccm, to form the gate trench;
4-5) removing the patterned etching mask layer;
4-6) performing high-temperature passivation treatment on the epitaxial layer obtained after the step 4-5), wherein the treatment temperature is 1400-1700 ℃, preferably 1550-1650 ℃, in the embodiment, 1600 ℃, and the treatment temperature is selectedAtmosphere is H 2 、SiH 4 One gas or a mixture of a plurality of gases in Ar, the treatment time is 10-30 min, preferably 15-25 min, the gas pressure is 50-100 Torr, and in the embodiment, the treatment time is 22min, so as to perform morphology modification on the gate trench.
It should be noted that, in the step 4-6), the morphology modification of the gate trench is performed by using a micro etching and atomic recombination mechanism on the surface of the gate trench in the high-temperature passivation process. The modification purposes are as follows: firstly, the etching damage after the step 4-4) can be eliminated, and the surface roughness of the gate groove is reduced, so that the carrier mobility of the channel of the device is improved; and secondly, the shape of the gate groove formed in the step 4-4) can be modified, so that the smooth bottom angle of the groove is realized, and the electric field gathering effect at the bottom angle is reduced.
As shown in fig. 6, a schematic structure of forming a gate dielectric layer in the gate trench, and forming a gate dielectric layer 108 on the surface of the gate trench 107. In step 5), a gate dielectric layer 108 is formed on the surface of the gate trench 107, including the following steps:
5-1) growing a first silicon dioxide layer on the surface of the gate trench by using a thermal oxidation process, wherein the thermal oxidation temperature is 1100-1300 ℃, preferably 1150-1200 ℃, and in the embodiment, 1180 ℃ is selected, and the oxidation gas is O 2 Or H 2 /O 2 Mixing the gases;
5-2) growing a second silicon dioxide layer on the surface of the first silicon dioxide layer formed by the thermal oxidation process by utilizing a low-pressure chemical vapor deposition process (Low Pressure Chemical Vapor Deposition, LPCVD), wherein the growth temperature is 700-800 ℃, preferably 750-780 ℃, and in the embodiment, 750 ℃;
5-3) at N 2 And annealing the first silicon oxide layer and the second silicon oxide layer in an O or NO gas atmosphere at 1100-1250 ℃, preferably 1150-1200 ℃, 1180 ℃ in the embodiment, and 30-60 min, preferably 40-55 min, and 45min in the embodiment.
It should be noted that, the gate dielectric layer is composed of the first silicon dioxide layer completed in step 5-1) and the second silicon oxide layer completed in step 5-2), and the purposes are as follows: step 5-1) a first silicon dioxide layer is grown on the surface of the gate trench by utilizing a thermal oxidation process, so that excellent interface characteristics of the silicon dioxide layer and the gate trench can be realized, interface state density between the silicon dioxide layer and the gate trench is reduced, channel mobility of the gate trench is improved, and on-resistance of the trench type SiC MOSFET device can be reduced; and 5-2) growing a second silicon dioxide layer on the surface of the first silicon dioxide layer formed by the thermal oxidation process by LPCVD, so that the silicon dioxide layer structure with the thickness of the silicon dioxide layer at the bottom of the gate trench and the thin silicon dioxide layer at the side wall of the gate trench can be realized.
As shown in fig. 7, a schematic structure of filling the surface of the gate dielectric layer in the gate trench with the polysilicon of the first doping type is shown, and filling the surface of the gate dielectric layer 108 in the gate trench 107 obtained in the step 5) with the polysilicon 109 of the first doping type. In step 6), filling the surface of the gate dielectric layer 108 in the gate trench 107 obtained in step 5) with the polysilicon 109 of the first doping type, comprising the following steps:
6-1) growing a polysilicon layer of a first doping type on the surface of the gate dielectric layer by using an LPCVD (low pressure chemical vapor deposition) process, wherein the growth temperature is 600-800 ℃, preferably 650-750 ℃, and in the embodiment, 700 ℃;
6-2) sequentially etching the polysilicon layer of the first doping type and the gate dielectric layer by utilizing an ICP etching process so as to remove the polysilicon layer and the gate dielectric layer in the area outside the gate groove.
As shown in fig. 8, a schematic structure of forming a source window in the passivation layer is shown, a passivation layer 110 is formed on the surface of the epitaxial layer 103 obtained by completing the step 6), and a source window 111 is formed in the passivation layer 110.
The passivation layer 110 in the embodiment of the present invention has the main functions of forming a device surface protection film and overcoming the surface defect of the device, and enhancing the stability and reliability of the device, and the passivation layer 110 may be a composite layer of one or two of silicon dioxide or nitride, for example.
The method for forming the source window 111 in the passivation layer 110 according to the embodiment of the present invention may be RIE etching or ICP etching, where the source window 111 exposes the source region 106 and the pillar region 104.
As shown in fig. 9, a source ohmic contact layer is formed in the source window, a drain ohmic contact layer is formed on the bottom surface of the substrate, a source ohmic contact layer 112 is formed in the source window 111, and a drain ohmic contact layer 113 is formed on the bottom surface of the substrate 101.
In step 9), referring to step S19 in fig. 1 and fig. 10, a gate window 114 is formed in the passivation layer 110 at a position corresponding to the polysilicon 109.
As an example, the method of forming the gate window 114 in the step 9) may be RIE etching or ICP etching.
In step 10), referring to step S20 in fig. 1 and fig. 11, a gate electrode 115 is formed in the gate window 114, a source electrode 116 is formed on the surface of the source ohmic contact layer 112, and a drain electrode 117 is formed on the surface of the drain ohmic contact layer 113.
As shown in fig. 11, the present invention provides a trench type SiC MOSFET device structure including:
a heavily doped substrate 101 of a first doping type;
a lightly doped epitaxial layer 103 of a first doping type on the upper surface of the substrate 101;
a second doping type column region 104 located in the epitaxial layer 103;
a well region 105 of a second doping type located in the epitaxial layer 103;
a source region 106 of a first doping type located in the well region 104;
a gate trench 107 in the epitaxial layer 103;
the gate dielectric layer 108 is positioned on the surface of the gate groove 107;
polysilicon 109 of a first doping type is filled on the surface of the gate dielectric layer 107 in the gate trench 107;
a passivation layer 110 on the surface of the epitaxial layer 103 between the source electrode 116 and the gate electrode 115;
a source ohmic contact layer 112 located on the surfaces of the first doped source region 106 and the second doped column region 104;
a drain ohmic contact layer 113 on a lower surface of the substrate 101;
a gate electrode 115 on the upper surface of the polysilicon 109;
a source electrode 116 on an upper surface of the source ohmic contact layer 112;
and a drain electrode 117 positioned on a lower surface of the drain ohmic contact layer 113.
As an example, the device structure of the present embodiment further includes a buffer layer 102, where the buffer layer 102 is located between the substrate 101 and the epitaxial layer 103, and further, the thickness of the buffer layer 102 is 0.5-1 μm, preferably 0.6-0.9 μm, and in the present embodiment, 0.8 μm is selected.
As an example, the first doping type is N-type and the second doping type is P-type.
In other examples, the first doping type may also be P-type and the second doping type N-type.
By way of example, the second doping type of the column region 104 has a depth of 1.8-3.0 μm, preferably 2.0-2.5 μm, in this embodiment 2.2 μm, a width of 0.4-1.2 μm, preferably 0.5-1.0 μm, in this embodiment 0.5 μm, and a doping concentration of 1e 17-1 e19cm -3 Preferably 1e17 to 1e18cm -3 In the present embodiment, 5e17cm is selected -3 。
It should be noted that, when the device is in the blocking state, the pillar region 104 is used as an electric field modulation structure of the device, so as to modulate the electric field distribution inside the device, and enable the maximum electric field peak to be pulled from the bottom corner of the trench to the bottom of the electric field modulation region 104, thereby reducing the electric field concentration effect at the bottom corner of the trench. In addition, the electric field intensity in the gate oxide at the bottom of the groove can be shielded, so that the breakdown of the gate oxide is avoided.
For example, the first doping type source region 106 has a depth of 0.1-0.5 μm, preferably 0.1-0.4 μm, in this embodiment 0.2 μm, and a width0.3 to 1.5 μm, preferably 0.4 to 0.8 μm, in this embodiment 0.5 μm is selected, the doping concentration is 1e19 to 1e21cm -3 Preferably 5e19 to 5e20cm -3 In the present embodiment, 2e20cm is selected -3 And the source region 106 of the first doping type is connected to the column region 104 of the second doping type.
It should be noted that the role of connecting the first doping type source region 106 with the second doping type column region 104 is to electrically connect the first doping type source region 106 with the second doping type column region 104, so that the column region 104 is shorted with the source region 107.
For example, the thickness of the well region 106 of the second doping type is 0.4-1.0 μm, preferably 0.5-1.0 μm, and in this embodiment, 0.5 μm is selected, and the doping concentration is 1e 17-5 e18cm -3 Selected as 2e17 to 1e18cm -3 In the present embodiment, 3e17cm is selected -3 。
As an example, the width of the gate trench 109 is 0.6 to 2.0 μm, preferably 0.9 to 1.2 μm, in this embodiment 1.0 μm, and the depth is 0.6 to 2.5 μm, preferably 1.2 to 1.5 μm, in this embodiment 1.4 μm;
as an example, the gate dielectric layer 108 is a composite layer of a first oxide layer and a second oxide layer, and the thickness of the gate dielectric layer 110 on the sidewall of the gate trench 107 is 40-60 nm, preferably 45-55 nm, in this embodiment, 50nm is selected, and the thickness of the gate dielectric layer 110 on the bottom of the gate trench 107 is 80-120 nm, preferably 90-110 nm, in this embodiment, 100nm is selected.
It should be noted that, the gate dielectric layer 108 is a composite layer of the first oxide layer and the second oxide layer, and has the following advantages: the first silicon dioxide layer is formed on the surface of the gate groove by a thermal oxidation process, so that excellent interface characteristics between the silicon dioxide layer and the gate groove can be ensured, the interface state density is low, the gate groove has high channel mobility, and the on-resistance of the groove type SiC MOSFET device is reduced; and the second silicon dioxide layer is formed by LPCVD on the surface of the first silicon dioxide layer formed by the thermal oxidation process, so that the silicon dioxide layer structure with the thick silicon dioxide layer at the bottom of the gate trench and the thin silicon dioxide layer at the side wall of the gate trench can be realized, and the gate dielectric layer with the thick gate dielectric layer at the bottom of the gate trench and the thin gate dielectric layer at the side wall of the gate trench can be realized. Therefore, the gate dielectric layer can have excellent interface characteristics, and has thick bottom and thin side wall.
In summary, the present invention aims to provide a trench SiC MOSFET device and a method for manufacturing the same, including: 1) Providing a heavily doped substrate 101 of a first doping type, and forming a lightly doped epitaxial layer 103 of the first doping type on the upper surface of the substrate 101; 2) Forming a second doping type column region 104 in the epitaxial layer 103; 3) Forming a well region 105 of a second doping type in the epitaxial layer 103 obtained by completing the step 2), and forming a source region 106 of a first doping type in the well region 105; 4) Forming a gate trench 107 in the epitaxial layer 103 obtained by completing the step 3); 5) Forming a gate dielectric layer 108 on the surface of the gate trench 107; 6) Filling polysilicon 109 of a first doping type on the surface of the gate dielectric layer 108 in the gate trench 107 obtained in the step 5); 7) Forming a passivation layer 110 on the surface of the epitaxial layer 103 obtained in the step 6), and forming a source window 111 in the passivation layer 110; 8) Forming a source ohmic contact layer 112 in the source window 111, and forming a drain ohmic contact layer 113 on the bottom surface of the substrate; 9) Forming a gate window 114 in the passivation layer 110 at a position corresponding to the polysilicon 109; 10 A gate electrode 115 is formed in the gate window 114, a source electrode 116 is formed on the surface of the source ohmic contact layer 112, and a drain electrode 117 is formed on the surface of the drain ohmic contact layer 113.
According to the invention, the column region electric field modulation structure is introduced into the groove type SiC MOSFET device, so that the electric field distribution at the bottom of the groove can be effectively relaxed, the electric field aggregation effect is eliminated, the electric field intensity in the gate oxide can be shielded, the breakdown of the gate oxide is avoided, the device is prevented from being broken down and burned out too early, and the reliability of the device is improved. In addition, the device structure and the preparation method are simple, and the effect is obvious, so that the preparation and the production of the high-performance and batched groove type SiC MOSFET device can be realized, and the device has huge market potential and wide application prospect. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (10)
1. The preparation method of the groove type SiC MOSFET device is characterized by comprising the following steps of:
providing a heavily doped substrate (101) of a first doping type, and forming a lightly doped epitaxial layer (103) of the first doping type on the upper surface of the substrate (101);
-forming a pillar region (104) of a second doping type in the epitaxial layer (103);
forming a well region (105) of a second doping type in the epitaxial layer (103), and forming a source region (106) of a first doping type in the well region (105);
-forming a gate trench (107) in the epitaxial layer (103);
forming a gate dielectric layer (108) in the gate trench (107);
filling polysilicon (109) of a first doping type on the surface of a gate dielectric layer (108) in the gate trench (107);
forming a passivation layer (110) on the surface of the epitaxial layer (103), and forming a source window (111) in the passivation layer (110);
forming a source ohmic contact layer (112) in the source window (111), and forming a drain ohmic contact layer (113) on the bottom surface of the substrate (101);
forming a gate window (114) in the passivation layer (110) at a location corresponding to the polysilicon region (109);
a gate electrode (115) is formed in the gate window (114), a source electrode (116) is formed on the surface of the source ohmic contact layer (112), and a drain electrode (117) is formed on the surface of the drain ohmic contact layer (113).
2. A method of fabricating a trench SiC MOSFET device according to claim 1, characterized in that the epitaxial layer (103) has a pillar region (104) of a second doping type formed therein, comprising the steps of:
forming an ion implantation mask layer on the surface of the epitaxial layer (103);
coating photoresist on the upper surface of the ion implantation mask layer, and performing patterning treatment to form patterned photoresist;
etching the ion implantation mask layer in the patterned photoresist by adopting an etching process to form an ion implantation window;
removing the patterned photoresist, and reserving the ion implantation mask layer after etching treatment;
according to the ion implantation mask layer after etching treatment, carrying out an aluminum ion implantation process on the epitaxial layer (103) to form a column region (104);
and removing the ion implantation mask layer after the etching treatment.
3. A method of fabricating a trench SiC MOSFET device according to claim 1, characterized in that the epitaxial layer (103) has a gate trench (107) formed therein, comprising the steps of:
growing an etching mask layer on the surface of the epitaxial layer (103) through a chemical vapor deposition process;
coating photoresist on the surface of the etching mask layer, and performing patterning treatment to form patterned photoresist;
performing reactive ion etching on the etching mask layer in the patterned photoresist to form a patterned etching mask layer;
removing the patterned photoresist, and performing inductively coupled plasma etching on the epitaxial layer (103) according to the patterned etching mask layer to form a gate trench;
removing the patterned etching mask layer;
and performing high-temperature passivation treatment on the epitaxial layer (103) and performing morphology modification on the gate trench.
4. The method for manufacturing the trench SiC MOSFET device according to claim 1, wherein a gate dielectric layer (108) is formed in the gate trench (107), comprising the steps of:
growing a first silicon dioxide layer on the surface of the gate trench (107) by utilizing a thermal oxidation process;
growing a second silicon dioxide layer on the surface of the first silicon dioxide layer formed by the thermal oxidation process by utilizing a low-pressure chemical vapor deposition process;
and annealing the first silicon oxide layer and the second silicon oxide layer.
5. The method for manufacturing a trench SiC MOSFET device according to claim 1, characterized in that the surface of the gate dielectric layer (108) in the gate trench (107) is filled with polysilicon (109) of the first doping type, comprising the steps of:
growing polysilicon (109) of a first doping type on the surface of the gate dielectric layer by utilizing a low-pressure chemical vapor deposition process;
and sequentially etching the polysilicon (109) and the gate dielectric layer (108) of the first doping type by utilizing an inductively coupled plasma etching process, and removing the polysilicon (109) and the gate dielectric layer (108) in the area outside the gate trench.
6. A trench SiC MOSFET device, comprising:
a heavily doped substrate (101) of a first doping type;
a lightly doped epitaxial layer (103) of a first doping type, located on the upper surface of the substrate (101);
-a pillar region (104) of a second doping type, located in the epitaxial layer (103);
a well region (105) of a second doping type, located in the epitaxial layer (103);
a source region (106) of a first doping type located in the well region (105);
-a gate trench (107) in the epitaxial layer (103);
the gate dielectric layer (108) is positioned in the gate groove (107);
polysilicon (109) of a first doping type is filled on the surface of the gate dielectric layer (108) in the gate trench;
a passivation layer (110) located on the surface of the epitaxial layer (103) between the source electrode (116) and the gate electrode (115);
a source ohmic contact layer (112) located on the surfaces of the first doping type source region (106) and the second doping type column region (104);
a drain ohmic contact layer (113) located on the lower surface of the substrate (101);
a gate electrode (115) located on the upper surface of the polysilicon (109);
a source electrode (116) located on the upper surface of the source ohmic contact layer (112);
and a drain electrode (117) located on the lower surface of the drain ohmic contact layer (113).
7. The trench SiC MOSFET device of claim 6, wherein the second doping type column region (104) has a depth of 1.8-3.0 μm, a width of 0.4-1.2 μm, and a doping concentration of 1e 17-1 e19cm -3 。
8. The trench SiC MOSFET device of claim 6, wherein said source region (106) of said first doping type has a depth of 0.2-0.5 μm, a width of 0.5-1.5 μm, and a doping concentration of 1e 19-1 e21cm -3 The source region (106) of the first doping type is connected to the column region (104) of the second doping type.
9. A trench SiC MOSFET device according to claim 6, characterized in that the gate trench (107) has a width of 0.6-2.0 μm and a depth of 0.6-2.5 μm.
10. The trench type SiC MOSFET device of claim 6, wherein the gate dielectric layer (108) is a composite layer of a first oxide layer and a second oxide layer, and the thickness of the gate dielectric layer (108) located on the sidewall of the gate trench (107) is 40-60 nm, and the thickness of the gate dielectric layer (108) located on the bottom of the gate trench (107) is 80-120 nm.
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