CN113488542A - Groove type SiC MOSFET device and preparation method thereof - Google Patents
Groove type SiC MOSFET device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 58
- 238000005530 etching Methods 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 32
- 238000002161 passivation Methods 0.000 claims description 29
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 238000005468 ion implantation Methods 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 235000012239 silicon dioxide Nutrition 0.000 claims description 25
- 239000000377 silicon dioxide Substances 0.000 claims description 25
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 238000009616 inductively coupled plasma Methods 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 230000004048 modification Effects 0.000 claims description 7
- 238000012986 modification Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 23
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 9
- 238000009826 distribution Methods 0.000 abstract description 4
- 230000002776 aggregation Effects 0.000 abstract description 3
- 238000004220 aggregation Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 17
- 239000000463 material Substances 0.000 description 10
- 230000007547 defect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- -1 aluminum ions Chemical class 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
The invention discloses a groove type SiC MOSFET device and a preparation method thereof.A column region electric field modulation structure is introduced into the groove type SiC MOSFET device, so that the distribution of an electric field at the bottom of a groove can be effectively relieved, the electric field aggregation effect is eliminated, the electric field intensity in grid oxide can be shielded, the electric field intensity in the grid oxide is reduced, the grid oxide breakdown is avoided, the device is prevented from being broken down and burned out too early, and the reliability of the device is improved. In addition, the device structure and the preparation method are simple, the effect is obvious, the preparation and production of the high-performance and batch groove type SiC MOSFET device can be realized, and the device has huge market potential and wide application prospect.
Description
Technical Field
The invention relates to a groove type SiC MOSFET device and a preparation method thereof, belonging to the technical field of semiconductor device preparation.
Background
SiC has a series of excellent characteristics such as a large forbidden band width, a high critical breakdown field strength, and a high thermal conductivity as a third-generation semiconductor material. The SiC power device can simultaneously realize excellent performances of high breakdown voltage, low on-resistance, high switching speed, easy heat dissipation and the like, has obvious competitiveness in the power electronic technology with high energy efficiency, high power and high temperature, and becomes a research hotspot of the current power semiconductor technology. With the increasing increase of energy crisis and the increasing prominence of environmental problems, technologies with energy conservation and emission reduction as the core are emerging, and the technical field of improving the energy utilization rate by improving the existing power system is most concerned. Statistically, 60% to 70% of the electrical energy is used in low energy systems, where most of the energy is wasted in power conversion and power driving. A key role in improving power utilization efficiency is the power device, also known as a power electronic device. How to reduce the power consumption of power devices has become an important issue worldwide. In this context, SiC devices having performance far superior to that of conventional silicon devices are favored.
In a conventional planar gate type SiC MOSFET device, the on-resistance of the device increases due to the presence of a parasitic junction field effect transistor structure. The groove grid type SiC MOSFET has no JFET area, the on-resistance of the device can be obviously reduced, the power density of the device can be further improved along with the reduction of the cell area of the device, and the groove grid type SiC MOSFET has obvious performance advantages and wide application prospect. However, the trench SiC MOSFET device is susceptible to the electric field concentration effect at the bottom corner of the trench, which may cause premature breakdown and even burning of the device. In addition, the high electric field in the gate oxide at the bottom of the trench is easy to cause gate oxide breakdown, so that the device is out of work.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides the groove type SiC MOSFET device and the preparation method thereof, the structure and the preparation method are simple, the electric field at the bottom of the groove type SiC MOSFET device is effectively modulated, and the gate oxide breakdown risk is reduced.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
in a first aspect, the invention provides a preparation method of a trench type SiC MOSFET device, which comprises the following steps:
providing a heavily doped substrate of a first doping type, and forming a lightly doped epitaxial layer of the first doping type on the upper surface of the substrate;
forming a column region of a second doping type in the epitaxial layer;
forming a well region of a second doping type in the epitaxial layer, and forming a source region of a first doping type in the well region;
forming a gate trench in the epitaxial layer;
forming a gate dielectric layer in the gate trench;
filling polysilicon of a first doping type on the surface of the gate dielectric layer in the gate trench;
forming a passivation layer on the surface of the epitaxial layer, and forming a source electrode window in the passivation layer;
forming a source ohmic contact layer in the source window, and forming a drain ohmic contact layer on the bottom surface of the substrate;
forming a gate window in the passivation layer at a position corresponding to the polysilicon region;
and forming a grid electrode in the grid window, forming a source electrode on the surface of the source ohmic contact layer, and forming a drain electrode on the surface of the drain ohmic contact layer.
With reference to the first aspect, further, the forming a column region of the second doping type in the epitaxial layer includes the following steps:
forming an ion implantation mask layer on the surface of the epitaxial layer;
coating photoresist on the upper surface of the ion implantation mask layer, and performing graphical treatment to form graphical photoresist;
carrying out etching treatment on the ion implantation mask layer in the patterned photoresist by adopting an etching process to form an ion implantation window;
removing the patterned photoresist, and reserving the ion implantation mask layer after etching treatment;
according to the ion implantation mask layer after etching treatment, carrying out an aluminum ion implantation process on the epitaxial layer to form a column region;
and removing the ion implantation mask layer after the etching treatment.
Further, forming a gate trench in the epitaxial layer includes the following steps:
growing an etching mask layer on the surface of the epitaxial layer by a chemical vapor deposition process;
coating photoresist on the surface of the etching mask layer, and carrying out patterning treatment to form patterned photoresist;
performing reactive ion etching on the etching mask layer in the patterned photoresist to form a patterned etching mask layer;
removing the patterned photoresist, and performing inductively coupled plasma etching on the epitaxial layer according to the patterned etching mask layer to form a gate trench;
removing the graphical etching mask layer;
and carrying out high-temperature passivation treatment on the epitaxial layer, and carrying out appearance modification on the gate trench.
Further, forming a gate dielectric layer in the gate trench includes the following steps:
growing a first silicon dioxide layer on the surface of the gate trench by using a thermal oxidation process;
growing a second silicon dioxide layer on the surface of the first silicon dioxide layer formed by the thermal oxidation process by using a low-pressure chemical vapor deposition process;
annealing the first silicon oxide layer and the second silicon oxide layer;
further, the step of filling the surface of the gate dielectric layer in the gate trench with polysilicon of the first doping type includes the following steps:
growing polysilicon of a first doping type on the surface of the gate dielectric layer by using a low-pressure chemical vapor deposition process;
and etching the polysilicon of the first doping type and the gate dielectric layer in sequence by utilizing an ICP (inductively coupled plasma) etching process to remove the polysilicon and the gate dielectric layer in the region outside the gate groove.
In a second aspect, the present invention provides a trench type SiC MOSFET device, comprising:
a heavily doped substrate of a first doping type;
a lightly doped epitaxial layer of a first doping type on an upper surface of the substrate;
a column region of a second doping type located in the epitaxial layer;
the well region of the second doping type is positioned in the epitaxial layer;
a source region of a first doping type located in the well region;
a gate trench in the epitaxial layer;
the gate dielectric layer is positioned in the gate groove;
the polysilicon with the first doping type is filled on the surface of the gate dielectric layer in the gate trench;
a passivation layer positioned on the surface of the epitaxial layer between the source electrode and the gate electrode;
the source ohmic contact layer is positioned on the surfaces of the source region of the first doping type and the column region of the second doping type;
the drain electrode ohmic contact layer is positioned on the lower surface of the substrate;
the grid electrode is positioned on the upper surface of the polycrystalline silicon;
the source electrode is positioned on the upper surface of the source ohmic contact layer;
and the drain electrode is positioned on the lower surface of the drain ohmic contact layer.
In combination with the second aspect, further, the second doping type pillar region has a depth of 1.8 to 3.0 μm, a width of 0.4 to 1.2 μm, and a doping concentration of 1e17 to 1e19cm-3。
Furthermore, the depth of the source region of the first doping type is 0.2-0.5 μm, the width is 0.5-1.5 μm, and the doping concentration is 1e 19-1 e21cm-3And the source region of the first doping type is connected with the column region of the second doping type.
Furthermore, the width of the gate trench is 0.6-2.0 μm, and the depth is 0.6-2.5 μm.
Furthermore, the gate dielectric layer is a composite layer of a first oxide layer and a second oxide layer, the thickness of the gate dielectric layer on the side wall of the gate trench is 40-60 nm, and the thickness of the gate dielectric layer on the bottom of the gate trench is 80-120 nm.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, the column region is introduced into the groove type SiC MOSFET device to serve as an electric field modulation structure, so that the electric field distribution at the bottom of the groove is effectively relieved, the electric field aggregation effect at the bottom corner of the groove is eliminated, the electric field intensity in the gate oxide can be shielded, the gate oxide breakdown is avoided, the device is prevented from being broken down and burned out too early, and the reliability of the device in operation is improved;
the device structure and the preparation method are simple, the effect is obvious, the preparation and the production of the high-performance and batch groove type SiC MOSFET device can be realized, and the device has huge market potential and wide application prospect.
Drawings
FIG. 1 is a schematic flow chart of a method for manufacturing a trench type SiC MOSFET device according to an embodiment of the present invention;
FIG. 2 is a schematic view of a lightly doped epitaxial layer with a first doping type formed on the upper surface of the substrate;
FIG. 3 is a schematic structural diagram of a pillar region of a second doping type formed in an epitaxial layer;
FIG. 4 is a schematic structural diagram of a well region having a source region of a first doping type formed therein;
FIG. 5 is a schematic diagram of a structure for forming a gate trench in an epitaxial layer;
FIG. 6 is a schematic structural diagram of a gate dielectric layer formed in a gate trench;
FIG. 7 is a schematic structural diagram of a gate dielectric layer surface in a gate trench filled with polysilicon of a first doping type;
FIG. 8 is a schematic diagram of a source window formed in a passivation layer;
FIG. 9 is a schematic structural diagram of a source ohmic contact layer formed in a source window and a drain ohmic contact layer formed on a bottom surface of a substrate;
FIG. 10 is a schematic diagram of a structure in which a gate window is formed in a passivation layer at a location corresponding to the polysilicon region;
FIG. 11 is a schematic structural diagram of a trench type SiC MOSFET device according to an embodiment of the present invention;
in the figure: 101. a substrate; 102. a buffer layer; 103. an epitaxial layer; 104. a column region; 105. a well region; 106. a source region; 107. a gate trench; 108. a gate dielectric layer; 109. polycrystalline silicon; 110. a passivation layer; 111. a source window; 112. a source ohmic contact layer; 113. a drain ohmic contact layer; 114. a gate window; 115. a gate electrode; 116. a source electrode; 117. and a drain electrode.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
As shown in fig. 1, a schematic flow chart of a method for manufacturing a trench SiC MOSFET device according to the present invention includes the following steps:
1) providing a heavily doped substrate 101 of a first doping type, and forming a lightly doped epitaxial layer 103 of the first doping type on the upper surface of the substrate 101;
2) forming a column region 104 of a second doping type in the epitaxial layer 103;
3) forming a well region 105 of a second doping type in the epitaxial layer 103 obtained in the step 2), and forming a source region 106 of a first doping type in the well region 105;
4) forming a gate trench 107 in the epitaxial layer 103 obtained in the step 3);
5) forming a gate dielectric layer 108 on the surface of the gate trench 107;
6) filling the surface of the gate dielectric layer 108 in the gate trench 107 obtained in the step 5) with polysilicon 109 of the first doping type;
7) forming a passivation layer 110 on the surface of the epitaxial layer 103 obtained in the step 6), and forming a source window 111 in the passivation layer 110;
8) forming a source ohmic contact layer 112 in the source window 111, and forming a drain ohmic contact layer 113 on the bottom surface of the substrate;
9) forming a gate window 114 in the passivation layer 110 at a position corresponding to the polysilicon 109;
10) a gate electrode 115 is formed in the gate window 114, a source electrode 116 is formed on the surface of the source ohmic contact layer 112, and a drain electrode 117 is formed on the surface of the drain ohmic contact layer 113.
Fig. 2 to 11 are schematic structural views of a trench SiC MOSFET device shown in each step of a method for manufacturing a trench SiC MOSFET device according to an embodiment of the present invention.
As shown in fig. 2, which is a schematic structural diagram of a lightly doped epitaxial layer with a first doping type formed on the upper surface of a substrate, a heavily doped substrate 101 with a first doping type is provided, and a lightly doped epitaxial layer 103 with a first doping type is formed on the upper surface of the substrate.
In this embodiment, the step 1) further includes a step of forming a buffer layer 102 between the substrate 101 and the epitaxial layer 103, and the epitaxial layer 103 is formed on an upper surface of the buffer layer 102.
It should be noted that the buffer layer 102 is used to assist the epitaxial layer 103 and the substrate 101 to better achieve concentration matching, which is beneficial to accurately control the doping concentration of the epitaxial layer 103 during the growth process.
On one hand, the material of the epitaxial layer 103 and the material of the substrate 101 may be the same, for example, the material of the substrate 101 and the material of the epitaxial layer 103 are both one of 4H-SIC, 6H-SIC or 3C-SIC; in this embodiment, the substrate 101 and the epitaxial layer 103 are both 4H-SIC; further, in the present embodiment, the crystal orientation of the material of the substrate 101 is a tilt angle of 4 ± 0.5 ° biased to the (11-20) direction.
On the other hand, the material of the epitaxial layer 103 may be different from that of the substrate 101, for example, the material of the substrate 101 may be one of monocrystalline silicon, polycrystalline silicon, sapphire and gallium arsenide, and the material of the epitaxial layer 103 may be one of 4H-SIC, 6H-SIC or 3C-SIC.
As shown in fig. 3, which is a schematic structural diagram of forming a column region of a second doping type in an epitaxial layer, a column region 104 of the second doping type is formed in the epitaxial layer 103.
In step 2), forming a column region 104 of the second doping type in the epitaxial layer 103 includes the following steps:
2-1) forming an ion implantation mask layer on the surface of the epitaxial layer 103;
2-2) coating photoresist on the upper surface of the ion implantation mask layer, and carrying out patterning treatment on the photoresist by adopting photoetching processes such as exposure, development, hardening and the like to form patterned photoresist;
2-3) etching the ion implantation mask layer by adopting an etching process according to the patterned photoresist to form an ion implantation window;
2-4) removing the patterned photoresist, and reserving the etched ion implantation mask layer;
2-5) carrying out an aluminum ion implantation process on the epitaxial layer according to the etched ion implantation mask layer to form a column region 104;
2-6) removing the etched ion implantation mask layer.
It should be noted that after the epitaxial layer 103 is subjected to an aluminum ion implantation process to form the column region 104, a high-temperature activation process treatment needs to be performed on the implanted aluminum ions, so that the implanted aluminum ions are activated to form effective acceptor doping.
As shown in fig. 4, which is a schematic structural diagram of a source region of a first doping type formed in a well region, a well region 105 of a second doping type is formed in the epitaxial layer 103 obtained in the step 2), and a source region 106 of the first doping type is formed in the well region.
It should be noted that the source region 106 of the first doping type is connected to the pillar region 104 of the second doping type.
As shown in fig. 5, which is a schematic structural diagram of forming a gate trench in the epitaxial layer, a gate trench 107 is formed in the epitaxial layer 103 obtained by completing the step 3).
Further, in step 4), forming a gate trench 107 in the epitaxial layer 103 obtained by completing the step 3), including the following steps:
4-1) growing an etching mask layer on the surface of the epitaxial layer, and growing dense and uniform SiO by Chemical Vapor Deposition (CVD)2A thin film with a thickness of 0.8-1.5 μm, preferably 0.9-1.0 μm, in this embodiment, 1.0 μm;
4-2) coating photoresist on the surface of the etching mask layer, and forming a patterned photoresist layer by adopting photoetching processes such as exposure, development, hardening and the like;
4-3) performing Reactive Ion Etching (RIE) on the Etching mask layer according to the patterned photoresist layer to form a patterned Etching mask layer;
4-4) removing the patterned photoresist layer, carrying out Inductively Coupled Plasma (ICP) etching on the epitaxial layer according to the patterned etching mask layer, and etching by using etching gasThe body being SF6/O2The flow ratio of the mixed gas is 5:1-2:1, preferably 3: 1-2:1, in this embodiment, 2:1 is selected, the total flow of the gas is 10-25 sccm, preferably 15-20 sccm, in this embodiment, 18sccm is selected to form a gate trench;
4-5) removing the patterned etching mask layer;
4-6) carrying out high-temperature passivation treatment on the epitaxial layer obtained in the step 4-5), wherein the treatment temperature is 1400-1700 ℃, preferably 1550-1650 ℃, in the embodiment, 1600 ℃ is selected, and the treatment atmosphere is H2、SiH4And one or more of Ar and Ar, wherein the treatment time is 10-30 min, preferably 15-25 min, and the gas pressure is 50-100 Torr, and in the embodiment, the treatment time is selected to be 22min, so as to perform morphology modification on the gate trench.
It should be noted that the step 4-6) of performing morphology modification on the gate trench is to use a micro-etching and atomic recombination mechanism on the surface of the gate trench in a high-temperature passivation process. The modification purposes are as follows: firstly, etching damage after the step 4-4) can be eliminated, and the surface roughness of the gate trench is reduced, so that the carrier mobility of a device channel is improved; secondly, the shape of the gate groove formed after the step 4-4) can be modified, and the bottom corners of the groove can be smooth, so that the electric field gathering effect at the bottom corners can be reduced.
As shown in fig. 6, a schematic structural diagram of forming a gate dielectric layer in a gate trench is shown, and a gate dielectric layer 108 is formed on the surface of the gate trench 107. In step 5), forming a gate dielectric layer 108 on the surface of the gate trench 107, including the following steps:
5-1) growing a first silicon dioxide layer on the surface of the gate trench by using a thermal oxidation process, wherein the thermal oxidation temperature is 1100-1300 ℃, preferably 1150-1200 ℃, in the embodiment, 1180 ℃ is selected, and the oxidizing gas is O2Or H2/O2Mixing the gas;
5-2) growing a second silicon dioxide layer on the surface of the first silicon dioxide layer formed by the thermal oxidation process by using a Low Pressure Chemical Vapor Deposition (LPCVD) process, wherein the growth temperature is 700-800 ℃, preferably 750-780 ℃, and in the embodiment, 750 ℃ is selected;
5-3) in N2And annealing the first silicon oxide layer and the second silicon oxide layer in an O or NO gas atmosphere, wherein the annealing temperature is 1100-1250 ℃, preferably 1150-1200 ℃, in the embodiment, 1180 ℃ is selected, the annealing time is 30-60 min, preferably 40-55 min, in the embodiment, 45min is selected.
It should be noted that the gate dielectric layer is composed of the first silicon oxide layer completed in step 5-1) and the second silicon oxide layer completed in step 5-2), and the purpose is as follows: step 5-1) growing a first silicon dioxide layer on the surface of the gate trench by using a thermal oxidation process, so that excellent interface characteristics of the silicon dioxide layer and the gate trench can be realized, the interface state density between the silicon dioxide layer and the gate trench is reduced, the improvement of the channel mobility of the gate trench is facilitated, and the on-resistance of a trench type SiC MOSFET device can be reduced; and 5-2) growing a second silicon dioxide layer on the surface of the first silicon dioxide layer formed by the thermal oxidation process by using LPCVD (low pressure chemical vapor deposition), so that a silicon dioxide layer structure with thick silicon dioxide layer at the bottom of the gate trench and thin silicon dioxide layer on the side wall of the gate trench can be realized.
As shown in fig. 7, the structural diagram is that the surface of the gate dielectric layer in the gate trench is filled with the polysilicon of the first doping type, and the surface of the gate dielectric layer 108 in the gate trench 107 obtained by completing the step 5) is filled with the polysilicon 109 of the first doping type. In step 6), filling the first doping type polysilicon 109 on the surface of the gate dielectric layer 108 in the gate trench 107 obtained in the step 5), including the following steps:
6-1) growing a first doping type polycrystalline silicon layer on the surface of the gate dielectric layer by using an LPCVD (low pressure chemical vapor deposition) process, wherein the growth temperature is 600-800 ℃, preferably 650-750 ℃, and in the embodiment, 700 ℃ is selected;
and 6-2) sequentially etching the polycrystalline silicon layer of the first doping type and the gate dielectric layer by utilizing an ICP (inductively coupled plasma) etching process so as to remove the polycrystalline silicon layer and the gate dielectric layer in the region except the gate groove.
As shown in fig. 8, which is a schematic structural diagram of forming a source window in a passivation layer, a passivation layer 110 is formed on the surface of the epitaxial layer 103 obtained by completing the step 6), and a source window 111 is formed in the passivation layer 110.
The passivation layer 110 in the embodiment of the present invention mainly functions to form a device surface protection film, overcome device surface defects, and enhance the stability and reliability of the device, and for example, the material of the passivation layer 110 may be one or two composite layers of silicon dioxide or nitride.
The method for forming the source window 111 in the passivation layer 110 according to the embodiment of the present invention may be RIE etching or ICP etching, where the source window 111 exposes the source region 106 and the pillar region 104.
As shown in fig. 9, a schematic structural diagram of forming a source ohmic contact layer in a source window and a drain ohmic contact layer on the bottom surface of the substrate is shown, forming a source ohmic contact layer 112 in the source window 111, and forming a drain ohmic contact layer 113 on the bottom surface of the substrate 101.
In step 9), referring to step S19 of fig. 1 and fig. 10, a gate window 114 is formed in the passivation layer 110 at a position corresponding to the polysilicon 109.
As an example, the method for forming the gate window 114 in step 9) may be RIE etching or ICP etching.
In step 10), referring to step S20 in fig. 1 and fig. 11, a gate electrode 115 is formed in the gate window 114, a source electrode 116 is formed on the surface of the source ohmic contact layer 112, and a drain electrode 117 is formed on the surface of the drain ohmic contact layer 113.
As shown in fig. 11, the present invention provides a trench type SiC MOSFET device structure, including:
a heavily doped substrate 101 of a first doping type;
a lightly doped epitaxial layer 103 of a first doping type on the upper surface of the substrate 101;
a column region 104 of a second doping type located in the epitaxial layer 103;
a well region 105 of a second doping type located in the epitaxial layer 103;
a source region 106 of a first doping type located in the well region 104;
a gate trench 107 in the epitaxial layer 103;
a gate dielectric layer 108 positioned on the surface of the gate trench 107;
a passivation layer 110 on the surface of the epitaxial layer 103 between the source electrode 116 and the gate electrode 115;
a source ohmic contact layer 112 on the surfaces of the first doping type source region 106 and the second doping type column region 104;
a drain ohmic contact layer 113 on a lower surface of the substrate 101;
a gate electrode 115 on the upper surface of the polysilicon 109;
a source electrode 116 on an upper surface of the source ohmic contact layer 112;
and a drain electrode 117 on a lower surface of the drain ohmic contact layer 113.
As an example, the device structure of this embodiment further includes a buffer layer 102, where the buffer layer 102 is located between the substrate 101 and the epitaxial layer 103, and further, the thickness of the buffer layer 102 is 0.5 to 1 μm, preferably 0.6 to 0.9 μm, and in this embodiment, is selected to be 0.8 μm.
As an example, the first doping type is N-type and the second doping type is P-type.
In other examples, the first doping type may also be P-type, and the second doping type may be N-type.
Illustratively, the second doping type pillar region 104 has a depth of 1.8-3.0 μm, preferably 2.0-2.5 μm, in this embodiment, 2.2 μm, a width of 0.4-1.2 μm, preferably 0.5-1.0 μm, in this embodiment, 0.5 μm, and a doping concentration of 1e 17-1 e19cm-3Preferably 1e 17-1 e18cm-3In the present embodiment, 5e17cm is selected-3。
It should be noted that the pillar region 104 functions as a device electric field modulation structure when the device operates in the blocking state, and may modulate the electric field distribution inside the device, so that the maximum electric field peak is pulled from the bottom of the trench to the bottom of the electric field modulation region 104, thereby reducing the electric field concentration effect at the bottom of the trench. In addition, the electric field intensity in the gate oxide at the bottom of the trench can be shielded, so that the breakdown of the gate oxide is avoided.
Illustratively, the depth of the first doping type source region 106 is 0.1-0.5 μm, preferably 0.1-0.4 μm, in this embodiment, 0.2 μm, the width is 0.3-1.5 μm, preferably 0.4-0.8 μm, in this embodiment, 0.5 μm, and the doping concentration is 1e 19-1 e21cm-3Preferably 5e 19-5 e20cm-3In the present embodiment, 2e20cm is selected-3And the source region 106 of the first doping type is connected with the pillar region 104 of the second doping type.
It should be noted that the connection between the first doping type source region 106 and the second doping type column region 104 is to electrically connect the first doping type source region 106 and the second doping type column region 104, so that the column region 104 is shorted with the source region 107.
For example, the thickness of the well region 106 of the second doping type is 0.4-1.0 μm, preferably 0.5-1.0 μm, and in this embodiment, the thickness is 0.5 μm, and the doping concentration is 1e 17-5 e18cm-3Selected from 2e 17-1 e18cm-3In the present embodiment, 3e17cm is selected-3。
Illustratively, the width of the gate trench 109 is 0.6-2.0 μm, preferably 0.9-1.2 μm, in this embodiment, 1.0 μm, and the depth is 0.6-2.5 μm, preferably 1.2-1.5 μm, in this embodiment, 1.4 μm;
for example, the gate dielectric layer 108 is a composite layer of a first oxide layer and a second oxide layer, and the thickness of the gate dielectric layer 110 located on the sidewall of the gate trench 107 is 40 to 60nm, preferably 45 to 55nm, in this embodiment, 50nm is selected, and the thickness of the gate dielectric layer 110 located at the bottom of the gate trench 107 is 80 to 120nm, preferably 90 to 110nm, in this embodiment, 100nm is selected.
It should be noted that the gate dielectric layer 108 is a composite layer of a first oxide layer and a second oxide layer, and has the following advantages: the first layer of silicon dioxide layer is formed by growing on the surface of the gate trench through a thermal oxidation process, so that excellent interface characteristics between the silicon dioxide layer and the gate trench can be guaranteed, the interface state density is low, the gate trench has high channel mobility, and the on-resistance of a trench type SiC MOSFET device is reduced; and the second silicon dioxide layer is formed by growing on the surface of the first silicon dioxide layer formed by the thermal oxidation process by LPCVD, so that a silicon dioxide layer structure with thick silicon dioxide layer at the bottom of the gate trench and thin silicon dioxide layer on the side wall of the gate trench can be realized, and a gate dielectric layer with thick gate dielectric layer at the bottom of the gate trench and thin gate dielectric layer on the side wall can be realized. Therefore, the gate dielectric layer can have excellent interface characteristics, thick bottom and thin side wall.
In summary, the present invention provides a trench SiC MOSFET device and a method for manufacturing the same, including: 1) providing a heavily doped substrate 101 of a first doping type, and forming a lightly doped epitaxial layer 103 of the first doping type on the upper surface of the substrate 101; 2) forming a column region 104 of a second doping type in the epitaxial layer 103; 3) forming a well region 105 of a second doping type in the epitaxial layer 103 obtained in the step 2), and forming a source region 106 of a first doping type in the well region 105; 4) forming a gate trench 107 in the epitaxial layer 103 obtained in the step 3); 5) forming a gate dielectric layer 108 on the surface of the gate trench 107; 6) filling the surface of the gate dielectric layer 108 in the gate trench 107 obtained in the step 5) with polysilicon 109 of the first doping type; 7) forming a passivation layer 110 on the surface of the epitaxial layer 103 obtained in the step 6), and forming a source window 111 in the passivation layer 110; 8) forming a source ohmic contact layer 112 in the source window 111, and forming a drain ohmic contact layer 113 on the bottom surface of the substrate; 9) forming a gate window 114 in the passivation layer 110 at a position corresponding to the polysilicon 109; 10) a gate electrode 115 is formed in the gate window 114, a source electrode 116 is formed on the surface of the source ohmic contact layer 112, and a drain electrode 117 is formed on the surface of the drain ohmic contact layer 113.
According to the invention, by introducing the column region electric field modulation structure into the groove type SiC MOSFET device, the electric field distribution at the bottom of the groove can be effectively relieved, the electric field aggregation effect is eliminated, the electric field intensity in the gate oxide can be shielded, and the gate oxide breakdown is avoided, so that the device is prevented from being broken down and burnt out too early, and the reliability of the device is improved. In addition, the device structure and the preparation method are simple, the effect is obvious, and therefore the preparation and the production of the high-performance and batch groove type SiC MOSFET device can be realized, and the device has huge market potential and wide application prospect. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A preparation method of a groove type SiC MOSFET device is characterized by comprising the following steps:
providing a heavily doped substrate (101) with a first doping type, and forming a lightly doped epitaxial layer (103) with the first doping type on the upper surface of the substrate (101);
forming a column region (104) of a second doping type in the epitaxial layer (103);
forming a well region (105) of a second doping type in the epitaxial layer (103), and forming a source region (106) of a first doping type in the well region (105);
forming a gate trench (107) in the epitaxial layer (103);
forming a gate dielectric layer (108) in the gate trench (107);
filling polysilicon (109) with a first doping type on the surface of the gate dielectric layer (108) in the gate trench (107);
forming a passivation layer (110) on the surface of the epitaxial layer (103), and forming a source window (111) in the passivation layer (110);
forming a source ohmic contact layer (112) in the source window (111), and forming a drain ohmic contact layer (113) on the bottom surface of the substrate (101);
forming a gate window (114) in the passivation layer (110) at a position corresponding to the polysilicon region (109);
and forming a gate electrode (115) in the gate window (114), forming a source electrode (116) on the surface of the source ohmic contact layer (112), and forming a drain electrode (117) on the surface of the drain ohmic contact layer (113).
2. The method of manufacturing a trench type SiC MOSFET device as claimed in claim 1, wherein the forming of the column region (104) of the second doping type in the epitaxial layer (103) comprises the steps of:
forming an ion implantation mask layer on the surface of the epitaxial layer (103);
coating photoresist on the upper surface of the ion implantation mask layer, and performing graphical treatment to form graphical photoresist;
carrying out etching treatment on the ion implantation mask layer in the patterned photoresist by adopting an etching process to form an ion implantation window;
removing the patterned photoresist, and reserving the ion implantation mask layer after etching treatment;
according to the ion implantation mask layer after etching treatment, carrying out an aluminum ion implantation process on the epitaxial layer (103) to form a column region (104);
and removing the ion implantation mask layer after the etching treatment.
3. The method for preparing a trench type SiC MOSFET device as claimed in claim 1, wherein the step of forming a gate trench (107) in the epitaxial layer (103) comprises the steps of:
growing an etching mask layer on the surface of the epitaxial layer (103) by a chemical vapor deposition process;
coating photoresist on the surface of the etching mask layer, and carrying out patterning treatment to form patterned photoresist;
performing reactive ion etching on the etching mask layer in the patterned photoresist to form a patterned etching mask layer;
removing the patterned photoresist, and performing inductively coupled plasma etching on the epitaxial layer (103) according to the patterned etching mask layer to form a gate trench;
removing the graphical etching mask layer;
and carrying out high-temperature passivation treatment on the epitaxial layer (103) and carrying out appearance modification on the gate trench.
4. The method for preparing the groove type SiC MOSFET device as claimed in claim 1, wherein a gate dielectric layer (108) is formed in the gate trench (107), comprising the following steps:
growing a first silicon dioxide layer on the surface of the gate trench (107) by utilizing a thermal oxidation process;
growing a second silicon dioxide layer on the surface of the first silicon dioxide layer formed by the thermal oxidation process by using a low-pressure chemical vapor deposition process;
and annealing the first silicon oxide layer and the second silicon oxide layer.
5. The method for preparing the groove type SiC MOSFET device as claimed in claim 1, wherein the surface of the gate dielectric layer (108) in the gate trench (107) is filled with polysilicon (109) of the first doping type, and the method comprises the following steps:
growing polysilicon (109) of a first doping type on the surface of the gate dielectric layer by using a low-pressure chemical vapor deposition process;
and sequentially etching the polysilicon (109) with the first doping type and the gate dielectric layer (108) by utilizing an inductively coupled plasma etching process, and removing the polysilicon (109) and the gate dielectric layer (108) in the region outside the gate groove.
6. A trench SiC MOSFET device, comprising:
a heavily doped substrate (101) of a first doping type;
a lightly doped epitaxial layer (103) of a first doping type located on an upper surface of the substrate (101);
a column region (104) of a second doping type located in the epitaxial layer (103);
a well region (105) of a second doping type located in the epitaxial layer (103);
a source region (106) of a first doping type located in the well region (105);
a gate trench (107) located in the epitaxial layer (103);
a gate dielectric layer (108) located in the gate trench (107);
polysilicon (109) of a first doping type, which is filled on the surface of the gate dielectric layer (108) in the gate trench;
a passivation layer (110) located on the surface of the epitaxial layer (103) between the source electrode (116) and the gate electrode (115);
a source ohmic contact layer (112) positioned on the surfaces of the source region (106) of the first doping type and the column region (104) of the second doping type;
a drain ohmic contact layer (113) on the lower surface of the substrate (101);
a gate electrode (115) on an upper surface of the polysilicon (109);
a source electrode (116) located on an upper surface of the source ohmic contact layer (112);
and the drain electrode (117) is positioned on the lower surface of the drain ohmic contact layer (113).
7. The trench type SiC MOSFET device of claim 6, wherein the second doping type pillar region (104) has a depth of 1.8-3.0 μm, a width of 0.4-1.2 μm, and a doping concentration of 1e 17-1 e19cm-3。
8. The trench SiC MOSFET device of claim 6, wherein the trench SiC MOSFET device comprisesThe source region (106) of the first doping type has a depth of 0.2 to 0.5 μm, a width of 0.5 to 1.5 μm, and a doping concentration of 1e19 to 1e21cm-3A source region (106) of the first doping type is connected to a column region (104) of the second doping type.
9. The trench type SiC MOSFET device according to claim 6, wherein the gate trench (107) has a width of 0.6 to 2.0 μm and a depth of 0.6 to 2.5 μm.
10. The trench type SiC MOSFET device as claimed in claim 6, wherein the gate dielectric layer (108) is a composite layer of a first oxide layer and a second oxide layer, the thickness of the gate dielectric layer (108) on the sidewall of the gate trench (107) is 40-60 nm, and the thickness of the gate dielectric layer (108) on the bottom of the gate trench (107) is 80-120 nm.
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