CN117650178A - Groove type SiC MOSFET device and preparation method thereof - Google Patents
Groove type SiC MOSFET device and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a groove type SiC MOSFET device and a preparation method thereof, wherein a groove type source end and a wrapping area are introduced into the groove type SiC MOSFET device, and a gate-drain capacitor is converted into a form of connecting a gate source capacitor and a drain source capacitor in series, so that the gate-drain capacitor is obviously reduced on the premise of maintaining the on-resistance of the SiC MOSFET device to be excessively increased, the switching speed of the device is improved, the switching loss is reduced, and meanwhile, a gate oxide protection area at the bottom of the groove can shield the electric field intensity in gate oxide to protect the gate oxide and avoid the breakdown of the gate oxide, thereby preventing the premature breakdown and burning of the device and improving the reliability of the device. In addition, the device structure and the preparation method are simple, and the effect is obvious, so that the preparation and the production of the high-performance and batched groove type SiC MOSFET device can be realized, and the device has huge market potential and wide application prospect.
Description
Technical Field
The invention relates to the technical field of semiconductor component production, in particular to a groove type SiC MOSFET device and a preparation method thereof.
Background
Silicon carbide is used as a third generation wide bandgap semiconductor material, and becomes a main stream power device material under high voltage, high temperature, high frequency and radiation resistance application by virtue of a high critical breakdown electric field, high thermal conductivity, high electron saturation drift rate and strong radiation resistance. The SiC MOSFET device has the obvious advantages of low characteristic on-resistance, high working temperature, high switching speed, high power density and the like, and is widely applied to the fields of power systems, power supplies and the like. With the continuous increase of energy crisis and the increasingly prominent environmental problems, the technology with energy conservation and emission reduction as the core is continuously emerging, and the technical field of improving the energy utilization rate by improving the existing power system is most interesting. It is counted that 60% to 70% of the electric energy is used in low-power systems, and most of the energy is wasted in power conversion and power driving, and how to reduce the energy consumption of the power device has become an important issue worldwide.
SiC trench MOSFET devices have gained much attention due to their low on-resistance and small parasitic capacitance, but high electric fields in the gate oxide at the bottom of the trench are very prone to gate oxide breakdown, leading to device failure. P formation by ion implantation at the bottom of a trench gate + The gate oxide protection region can shield an electric field, protect gate oxide and improve withstand voltage, and is widely applied to the SiC groove M after the modeOSFET design and optimization. At present, the optimization of the trench MOSFET device is mainly focused on the premise that the gate oxide does not need to bear a high electric field, the on-resistance is reduced, the gate-drain capacitance is reduced, the purpose of reducing the loss of the MOSFET device is achieved, and however, a trade-off relationship exists between the on-resistance and the gate-drain capacitance. The material advantage of SiC makes SiC MOSFETs more suitable for high frequency applications, so reducing the gate-drain capacitance to reduce the dynamic power consumption of the device in high frequency applications without excessively increasing the on-resistance is a difficulty and hot spot problem of SiC trench MOSFET devices.
Disclosure of Invention
The invention aims to: the invention aims to provide a trench type SiC MOSFET device capable of realizing remarkable reduction of gate-drain capacitance without excessively increasing on-resistance and a preparation method thereof.
The technical scheme is as follows: the trench type SiC MOSFET device structure comprises:
a heavily doped substrate of a first doping type;
a heavily doped buffer layer of a first doping type on the upper surface of the substrate;
the lightly doped first epitaxial layer of the first doping type is positioned on the upper surface of the buffer layer;
a lightly doped cladding region of a first doping type located over an interior of the first epitaxial layer;
a lightly doped second epitaxial layer of a second doping type on the upper surface of the first epitaxial layer;
a heavily doped source region of the first doping type on the upper surface of the second epitaxial layer;
the gate groove is positioned in the wrapping area, the second epitaxial layer and the source area;
a heavily doped gate oxide protection region of a second doping type located in the gate trench;
the dielectric layer is positioned on the surface of the gate groove;
the polysilicon layer of the first doping type is filled on the surface of the dielectric layer in the gate trench;
the source groove is positioned outside the first epitaxial layer, the second epitaxial layer and the source region;
the heavily doped buried layer bottom contact region and the buried layer side wall contact region of the second doping type are positioned in the source groove;
the passivation layer is positioned between the source electrode and the gate electrode and is positioned on the surfaces of the polycrystalline silicon layer and the source region;
the source ohmic contact layer is positioned on the surfaces of the source region of the first doping type, the buried layer bottom contact region of the second doping type and the side wall contact region;
the drain ohmic contact layer is positioned on the lower surface of the bottom of the substrate;
the grid electrode is positioned on the upper surface of the polycrystalline silicon layer;
the source electrode is positioned on the upper surface of the source ohmic contact layer;
and the drain electrode is positioned on the lower surface of the drain ohmic contact layer.
Preferably, the depth of the wrapping area is 1.4-2.0 μm, the width is 4.4-5.8 μm, and the doping concentration is 1e 16-7 e16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the second epitaxial layer is 0.5-0.8 mu m, and the doping concentration is 1e 17-1 e18cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the source region is 0.2-0.4 μm, the width is 6.0-6.8 μm, and the doping concentration is 1e 19-1 e20cm -3 。
Preferably, the width of the gate trench is 3.5-4.5 μm, and the depth is 1.2-2.2 μm; the width of the source trench is 2.2-2.5 mu m, and the depth is the same as that of the gate trench; the depth of the gate oxide protection region is 0.5-0.8 mu m, and the doping concentration is 8e 18-1 e20cm -3 。
Preferably, the depth of the bottom contact region of the buried layer is 0.7-1.1 mu m; the width of the contact area of the side wall of the buried layer is 0.3-0.6 mu m, and the doping concentration is 1e 19-1 e20cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the dielectric layer is 40-60 nm.
The preparation method of the groove type SiC MOSFET device comprises the following steps:
forming a heavily doped buffer layer of a first doping type on the upper surface of the heavily doped substrate of the first doping type;
forming a lightly doped first epitaxial layer of a first doping type on the upper surface of the buffer layer;
forming a lightly doped cladding region of a first doping type over an interior of the first epitaxial layer;
forming a lightly doped second epitaxial layer of a second doping type on the upper surface of the first epitaxial layer;
forming a heavily doped source region of the first doping type on the upper surface of the second epitaxial layer;
etching the source region, the second epitaxial layer and the first epitaxial layer to obtain a gate trench and a source trench;
forming a heavily doped gate oxide protection region of a second doping type in the gate trench;
forming a heavily doped buried layer bottom contact region and a buried layer side wall contact region of a second doping type in the source trench;
forming a dielectric layer on the upper surfaces of the bottom contact region of the buried layer, the side wall of the gate trench and the gate oxide protection region;
filling a polysilicon layer of a first doping type on the upper surface of the dielectric layer in the gate trench;
forming a passivation layer on the upper surfaces of the polysilicon layer and the source region, thereby forming a source window;
forming a source ohmic contact layer on the source window, and forming a drain ohmic contact layer on the lower surface of the substrate;
etching the passivation layer to obtain a gate window, and exposing the polysilicon layer region;
a gate electrode is formed in the gate window, a source electrode is formed on the upper surface of the source ohmic contact layer, and a drain electrode is formed on the lower surface of the drain ohmic contact layer.
Further, a wrapping region of the first doping type is formed over the interior of the first epitaxial layer, and the specific method is as follows:
forming an ion implantation mask layer on the surface of the first epitaxial layer, coating photoresist, performing patterning treatment to obtain patterned photoresist, performing etching treatment on the ion implantation mask layer to form an ion implantation window, removing the patterned photoresist, performing nitrogen ion vertical implantation on the first epitaxial layer to form a wrapping area, and removing the etched ion implantation mask layer.
Further, etching the source region, the second epitaxial layer and the first epitaxial layer to obtain a gate trench and a source trench, wherein the method specifically comprises the following steps:
etching mask layer is grown on the surface of the source region, and compact and uniform SiO is grown through chemical vapor deposition process 2 A film; coating photoresist on the surface of the etching mask layer, and performing patterning treatment to obtain a patterned photoresist layer; performing reactive ion etching on the etching mask layer according to the patterned photoresist layer to form a patterned etching mask layer; removing the patterned photoresist layer, and performing inductively coupled plasma etching on the second epitaxial layer and the source region according to the patterned etching mask layer to form a gate trench and a source trench; removing the patterned etching mask layer; and performing high-temperature passivation treatment, and performing morphology modification on the gate trench and the source trench.
Further, a buried layer bottom contact region and a buried layer side wall contact region of a second doping type are formed in the source trench, and the specific method is as follows:
forming an ion implantation mask layer on the surfaces of the source groove and the first epitaxial layer, coating photoresist on the surfaces, and performing patterning treatment to obtain patterned photoresist; etching the ion implantation mask layer according to the patterned photoresist to form an ion implantation window; removing the patterned photoresist, and performing aluminum ion vertical implantation on the first epitaxial layer according to the etched ion implantation mask layer to form a buried layer bottom contact region; removing the etched ion implantation mask layer; obtaining a buried layer bottom contact area; forming an ion implantation mask layer on the surface of the side wall of the source trench; and similarly, the buried layer side wall contact region is obtained through aluminum ion inclined implantation.
Further, a dielectric layer is formed on the bottom contact region of the buried layer, the side wall of the gate trench and the upper surface of the gate oxide protection region, and the specific method is as follows:
and growing a silicon dioxide layer on the surfaces of the bottom contact region of the buried layer, the side wall of the gate groove and the gate oxide protection region by utilizing a thermal oxidation process, and carrying out annealing treatment on the silicon dioxide layer.
Further, the upper surface of the dielectric layer in the gate trench is filled with a polysilicon layer of the first doping type, and the specific method is as follows:
and growing a polysilicon layer on the surface of the dielectric layer by utilizing low-pressure chemical vapor deposition, sequentially etching the polysilicon layer and the dielectric layer, removing the redundant polysilicon layer and the dielectric layer outside the gate trench, exposing the source region, and flushing the rest polysilicon layer and the source region.
The beneficial effects are that: compared with the prior art, the invention has the remarkable advantages that: 1. according to the invention, the source groove is formed by etching the source electrode, the bottom contact region of the buried layer and the side wall contact region of the buried layer are formed at the bottom and the side wall of the source groove by ion implantation, and the capacitance of the side wall of the gate electrode and the drain electrode is converted into the series connection of the gate-source capacitance and the drain-source capacitance by the coupling effect of the buried layer bottom contact region, so that the gate-drain capacitance is greatly reduced; 2. according to the invention, the side surface of the dielectric layer and the gate oxide protection region are wrapped by introducing the wrapping region with the doping concentration higher than that of the epitaxial layer, so that the depletion region area of the gate oxide protection region is reduced, and the influence of on-resistance increase caused by the contact region at the bottom of the buried layer and the contact region at the side wall of the buried layer is compensated; 3. on the premise of maintaining the slightly increased on-resistance of the trench MOSFET, the gate-drain capacitance is obviously reduced, the switching speed of the device is improved, and the switching loss is reduced; 4. the sizes and doping concentrations of the wrapping layer, the second epitaxial layer and the source region are matched with each other, and the sizes of the gate/source groove, the buried layer bottom contact region and the buried layer side wall contact region are optimized, so that the invention can be applied to a 1200V breakdown voltage class, meets the requirement that the optimal threshold voltage required by system application is between 2 and 3V, and realizes the optimal device performance; 5. the device structure and the preparation method are simple, the effect is obvious, the preparation and the production of the groove type SiC MOSFET device with high performance and batch production can be realized, and the device has huge market potential and wide application prospect.
Drawings
Fig. 1 is a schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 8 is an eighth schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 10 is a schematic cross-sectional view of a SiC MOSFET device according to an embodiment of the present invention;
fig. 11 is an eleventh schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 12 is a schematic diagram showing a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 13 is a thirteenth schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 14 is a fourteen schematic diagram of a cross-sectional structure of a SiC MOSFET device according to an embodiment of the present invention;
fig. 15 is a flow chart of a method of fabricating a trench SiC MOSFET device;
in the figure: 101. a substrate; 102. a buffer layer; 103. an epitaxial layer; 104. a wrapping area; 105. a second epitaxial layer; 106. a source region; 107. a gate trench; 108. a source trench; 109. a gate oxide protection region; 110. a buried layer bottom contact region; 111. a buried layer sidewall contact region; 112. a dielectric layer; 113. a polysilicon layer; 114. a passivation layer; 115. a source window; 116. a source ohmic contact layer; 117. a drain ohmic contact layer; 118. a gate window; 119. a gate electrode; 120. a source electrode; 121. and a drain electrode.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the embodiments of the present application, it should be noted that, directions or positional relationships indicated by terms such as "upper", "lower", "vertical", "top", "bottom", "inner", "outer", etc., are based on directions or positional relationships shown in the drawings, are merely for convenience in describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the devices or elements to be referred to must have a specific direction, be configured and operated in the specific direction, and thus should not be construed as limiting the embodiments of the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
As shown in fig. 1, the trench SiC MOSFET device structure of the present invention includes:
a heavily doped substrate 101 of a first doping type;
a heavily doped buffer layer 102 of a first doping type on the upper surface of the substrate 101;
a lightly doped first epitaxial layer 103 of a first doping type on the upper surface of the buffer layer 102;
a lightly doped cladding region 104 of the first doping type, located over the interior of the first epitaxial layer 103;
a lightly doped second epitaxial layer 105 of a second doping type on the upper surface of the first epitaxial layer 103;
a heavily doped source region 106 of the first doping type on the upper surface of the second epitaxial layer 105;
a gate trench 107 in the wrapped-around region 104, the second epitaxial layer 105, and the source region 106;
a heavily doped gate oxide protection region 109 of the second doping type in the gate trench 107;
a dielectric layer 112 located on the surface of the gate trench 107;
a polysilicon layer 113 of the first doping type filled on the surface of the dielectric layer 112 in the gate trench 107;
a source trench 108 located outside the first epitaxial layer 103, the second epitaxial layer 105, and the source region 106;
a heavily doped buried layer bottom contact region 110 and buried layer sidewall contact region 111 of the second doping type, located in the source trench 108;
a passivation layer 114 between the source electrode 120 and the gate electrode 119 on the surfaces of the polysilicon layer 113 and the source region 106;
a source ohmic contact layer 116 located on the surfaces of the source region 106 of the first doping type, the buried layer bottom contact region 110 of the second doping type, and the sidewall contact region 111;
a drain ohmic contact layer 117 on a lower surface of the bottom of the substrate 101;
a gate electrode 119 located on the upper surface of the polysilicon layer 113;
a source electrode 120 on an upper surface of the source ohmic contact layer 116;
and a drain electrode positioned on the lower surface of the drain ohmic contact layer 117.
Alternatively, the thickness of the buffer layer 102 is 0.5 to 1 μm, preferably 0.6 to 0.9 μm, and in this embodiment, 0.8 μm is selected. The first doping type is N type, and the second doping type is P type; in other embodiments, the first doping type may be P-type and the second doping type may be N-type.
Optionally, lightly doped cladding region 104 of the first doping type has a depth of 1.4 to 2.0 μm, preferably 1.6 to 1.8 μm, in this embodiment 1.8 μm; the width of the wrapping area 104 is 4.4 to 5.8 μm, preferably 4.9 to 5.3 μm, in this embodiment 5.1 μm; the doping concentration of the wrapping area 104 is 1e 16-7 e16cm -3 Preferably 3e16 to 5e16cm -3 In the present embodiment, 3e16cm is selected -3 。
Optionally, the depth of the second epitaxial layer 105 of the second doping type is 0.5-0.8 μm, preferably 0.6-0.7 μm, in this embodiment 0.6 μm; the doping concentration of the second epitaxial layer 105 is 1e 17-1 e18cm -3 Preferably 1e17 to 3e17cm -3 In the present embodiment, 2e17cm is selected -3 。
Alternatively, the depth of the source region 106 of the first doping type is 0.2 to 0.4 μm, preferably 0.2 to 0.3 μm, in this embodiment 0.2 μm; the width of the source region 106 is 6.0 to 6.8 μm, preferably 6.0 to 6.4 μm, and in this embodiment, 6.2 μm is selected; the doping concentration of the source region 106 is 1e 19-1 e20cm -3 Preferably 1e19 to 3e19cm -3 In the present embodiment, 1e19cm is selected -3 。
Alternatively, the width of the gate trench 107 is 3.5 to 4.5 μm, preferably 3.8 to 4.2 μm, and in this embodiment, 4.0 μm is selected; the depth of the gate trench 107 is 1.2 to 2.2 μm, preferably 1.6 to 2.0 μm, and in this embodiment, 1.8 μm is selected; the source trench 108 has a width of 2.2 to 2.5 μm, preferably 2.2 to 2.4 μm, and in this embodiment, is selected to be 2.3 μm and has the same depth as the gate trench.
Optionally, the second doping type of the gate oxide protection region 109 has a depth of 0.5 to 0.8 μm, preferably 0.6 to 0.7 μm, in this embodimentSelecting 0.7 μm; the doping concentration of the gate oxide protection region 109 is 8e 18-1 e20cm -3 Preferably 8e18 to 2e19cm -3 In the present embodiment, 1e19cm is selected -3 。
Optionally, the depth of the buried layer bottom contact region 110 of the second doping type is 0.7-1.1 μm, preferably 0.7-0.9 μm, in this embodiment 0.7 μm; the width of the buried sidewall contact 111 is 0.3 to 0.6 μm, preferably 0.3 to 0.4 μm, and in this embodiment, 0.3 μm is selected; the doping concentration of the buried layer bottom contact region 110 and the buried layer side wall contact region 111 is 1e 19-1 e20cm -3 Preferably 1e19 to 3e19cm -3 In the present embodiment, 1e19cm is selected -3 。
Preferably, the dielectric layer 112 is located on the side wall and bottom of the gate trench 107, and the thickness of the dielectric layer is 40-60 nm, preferably 45-55 nm, and in this embodiment, 50nm is selected.
The dielectric layer 112 is formed by growing a silicon dioxide layer on the surface of the gate trench by a thermal oxidation process, so that excellent interface characteristics of the silicon dioxide layer and the gate trench can be realized, interface state density between the silicon dioxide layer and the gate trench is reduced, channel mobility of the gate trench is improved, and on-resistance of the trench type SiC MOSFET device can be reduced.
As shown in fig. 15, the method for preparing the trench SiC MOSFET device according to the present invention includes the following steps:
forming a heavily doped buffer layer 102 of a first doping type on an upper surface of a heavily doped substrate 101 of the first doping type;
forming a lightly doped first epitaxial layer 103 of a first doping type on an upper surface of the buffer layer 102;
forming a lightly doped cladding region 104 of a first doping type over the interior of the first epitaxial layer 103;
forming a lightly doped second epitaxial layer 105 of a second doping type on the upper surface of the first epitaxial layer 103;
forming a heavily doped source region 106 of the first doping type on the upper surface of the second epitaxial layer 105;
etching the source region 106, the second epitaxial layer 105 and the first epitaxial layer 103 to obtain a gate trench 107 and a source trench 108;
forming a heavily doped gate oxide protection region 109 of a second doping type within the gate trench 107;
forming a heavily doped buried layer bottom contact region 110 and a buried layer sidewall contact region 111 of a second doping type within the source trench 108;
forming a dielectric layer 112 on the upper surfaces of the buried layer bottom contact region 110, the buried layer sidewall contact region 111, the sidewalls of the gate trench 107, and the gate oxide protection region 109;
filling a polysilicon layer 113 of a first doping type on the upper surface of the dielectric layer 112 in the gate trench 107;
forming a passivation layer 114 on the upper surfaces of the polysilicon layer 113 and the source region 106, thereby forming a source window 115;
a source ohmic contact layer 116 is formed on the source window 115, and a drain ohmic contact layer 117 is formed on the lower surface of the substrate 101;
etching to obtain a gate window 118 at the passivation layer 114 to expose the polysilicon layer region;
a gate electrode 119 is formed in the gate window 118, a source electrode 120 is formed on the upper surface of the source ohmic contact layer 116, and a drain electrode 121 is formed on the lower surface of the drain ohmic contact layer 117.
Fig. 1 to 14 are schematic diagrams of a trench SiC MOSFET device according to the present invention, where the schematic diagrams are shown in the steps of the method for manufacturing a trench SiC MOSFET device.
As shown in fig. 2, a schematic structure of forming a first lightly doped epitaxial layer of a first doping type on the upper surfaces of the substrate and the buffer layer is shown, providing a heavily doped substrate 101 of the first doping type and a heavily doped buffer layer 102 of the first doping type, and forming a first lightly doped epitaxial layer 103 of the first doping type on the upper surface of the buffer layer 102. It should be noted that the buffer layer 102 is used to assist the first epitaxial layer 103 and the substrate 101 to better achieve concentration matching, which is beneficial to accurately controlling the doping concentration of the first epitaxial layer 103 during the growth process.
In one aspect, the material of the first epitaxial layer 103 may be the same as the material of the substrate 101, for example, the material of the substrate 101 and the material of the first epitaxial layer 103 are one of 4H-SiC, 6H-SiC or 3C-SiC; in this embodiment, the material of the substrate 101 and the material of the first epitaxial layer 103 are both 4H-SiC; further, in the present embodiment, the crystal orientation of the material of the substrate 101 is inclined at an angle of (4.+ -. 0.5) degrees to the (11-20) direction.
On the other hand, the material of the first epitaxial layer 103 may be different from the material of the substrate 101, for example, the material of the substrate 101 may be one of monocrystalline silicon, polycrystalline silicon, sapphire and gallium arsenide; the material of the first epitaxial layer 103 may be one of 4H-SiC, 6H-SiC or 3C-SiC.
As shown in fig. 3, a schematic structure of forming a first doping type wrapped-around region in the first epitaxial layer is shown, and a first doping type lightly doped wrapped-around region 104 is formed on the inner portion of the first epitaxial layer 103, specifically by the following method:
forming an ion implantation mask layer on the surface of the epitaxial layer 103;
coating photoresist on the upper surface of the ion implantation mask layer, and carrying out patterning treatment on the photoresist by adopting photoetching processes such as exposure, development, hardening and the like so as to form patterned photoresist;
etching the ion implantation mask layer by adopting an etching process according to the patterned photoresist to form an ion implantation window;
removing the patterned photoresist and reserving the etched ion implantation mask layer;
performing nitrogen ion vertical implantation on the epitaxial layer according to the etched ion implantation mask layer to form a wrapping region 104;
and removing the etched ion implantation mask layer.
After the first epitaxial layer 103 is subjected to a nitrogen ion implantation process to form the wrapping region 104, a high-temperature activation process is further required to be performed on the implanted nitrogen ions, so that the implanted nitrogen ions are activated to form effective donor doping.
As shown in fig. 4, a schematic structure of forming a lightly doped second epitaxial layer of a second doping type and a heavily doped source region of a first doping type in the epitaxial layer is shown, forming a lightly doped second epitaxial layer 105 of the second doping type in the upper surface of the first epitaxial layer 103, and forming a heavily doped source region 106 of the first doping type in the upper surface of the epitaxial layer 105.
As shown in fig. 5, which is a schematic structural diagram of forming a gate trench and a source trench in an epitaxial layer and a source region, etching the source region 106, the second epitaxial layer 105, and the first epitaxial layer 103 to obtain a gate trench 107 and a source trench 108, the specific method is as follows:
etching mask layer is grown on the surfaces of the second epitaxial layer and the source region, and dense and uniform SiO is grown by chemical vapor deposition (Chemical Vapor Deposition, CVD) 2 The film thickness is 0.8 to 1.5. Mu.m, preferably 0.9 to 1.1. Mu.m, in this example 1.0. Mu.m;
coating photoresist on the surface of the etching mask layer, and forming a patterned photoresist layer by adopting photoetching processes such as exposure, development, hardening and the like;
performing reactive ion (Reactive Ion Etching, RIE) etching on the etching mask layer according to the patterned photoresist layer to form a patterned etching mask layer;
removing the patterned photoresist layer, and performing inductively coupled plasma (Inductively Coupled Plasma, ICP) etching on the epitaxial layer and the source region according to the patterned etching mask layer, wherein the etching gas is SF 6 The flow ratio of the mixed gas of/O2 is 5:1-2:1, preferably 3:1-2:1, in this embodiment, 2:1 is selected, the total flow of the gas is 10-25 sccm, preferably 15-20 sccm, in this embodiment, 18sccm, to form the gate trench 107 and the source trench 108;
removing the patterned etching mask layer;
the epitaxial layer is subjected to high temperature passivation at 1400-1700 c, preferably 1550-1650 c, in this embodiment 1600 c, in an atmosphere of H 2 、SiH 4 One gas or a mixture of gases in Ar for 10 to 30 minutes, preferably 15 to 25 minutes, in this embodiment 22 minutes, and a gas pressure of 50 to 100Torr, preferably 65 to 85Torr, in this embodimentIs 75Torr to perform morphology modification on the gate trench 107 and the source trench 108.
It should be noted that, the topography modification of the gate trench 107 and the source trench 108 is performed by using a micro etching and atomic recombination mechanism for the surfaces of the gate trench 107 and the source trench 108 in the high temperature passivation process. The modification purposes are as follows: firstly, etching damage can be eliminated, and the surface roughness of the gate trench 107 can be reduced, so that the mobility of a channel carrier of a device can be improved; secondly, the shapes of the gate trench 107 and the source trench 108 formed after the step 4-4) can be modified, so that the rounded bottom angle of the trench is realized, and the electric field gathering effect at the bottom angle is reduced.
As shown in fig. 6, a schematic structure of forming a heavily doped gate oxide protection region of a second doping type in the gate trench is shown, and a heavily doped gate oxide protection region 109 of the second doping type is formed in the gate trench 107.
After forming the heavily doped gate oxide protection region 109 of the second doping type by aluminum ion implantation in the obtained gate trench 107, a high-temperature activation process is further required to be performed on the implanted aluminum ions, so that the implanted aluminum ions are activated to form effective acceptor doping.
As shown in fig. 7, 8 and 9, a schematic structure of forming a heavily doped buried layer contact region of a second doping type in a source trench is shown, and a heavily doped buried layer bottom contact region 110 and a buried layer sidewall contact region 111 of the second doping type are formed in the resulting source trench 108. The specific method comprises the following steps:
forming an ion implantation mask layer on the surfaces of the source groove 108 and the first epitaxial layer 103, coating photoresist on the surfaces, and performing patterning treatment to obtain patterned photoresist; etching the ion implantation mask layer according to the patterned photoresist to form an ion implantation window; removing the patterned photoresist, and performing aluminum ion vertical implantation on the first epitaxial layer according to the etched ion implantation mask layer to form a buried layer bottom contact region 110; removing the etched ion implantation mask layer; obtaining a buried layer bottom contact area; forming an ion implantation mask layer on the sidewall surface of the source trench 108; the buried layer sidewall contact region 111 is similarly obtained by aluminum ion tilt implantation.
It should be noted that the bottom contact region 110 of the buried layer needs to be formed by single vertical implantation of aluminum ions, the sidewall contact region 111 of the buried layer needs to be formed by two single oblique angle implantation of aluminum ions, and after the contact region is formed, the implanted aluminum ions need to be subjected to a high-temperature activation process so as to activate the implanted aluminum ions to form effective acceptor doping.
As shown in fig. 10, which is a schematic structural diagram of forming dielectric layers in the gate trench and the source trench, a dielectric layer 112 is formed on the upper surfaces of the buried layer bottom contact region 110, the buried layer sidewall contact region 111, the sidewall of the gate trench 107, and the gate oxide protection region 109, and the specific method is as follows:
a silicon dioxide layer is grown on the surfaces of the buried layer bottom contact region 110, the buried layer side wall contact region 111, the side wall of the gate trench 107 and the gate oxide protection region 109 by using a thermal oxidation process, wherein the thermal oxidation temperature is 1100-1300 ℃, preferably 1150-1200 ℃, and in the embodiment, 1180 ℃ is selected, and the oxidation gas is O 2 Or H 2 /O 2 Mixing the gases; at N 2 The silicon dioxide layer is annealed in an O or NO atmosphere at 1100-1250 c, preferably 1150-1200 c, in this example 1180 c for 30-60 min, preferably 40-55 min, in this example 45min.
The silicon dioxide layer 112 is grown on the surface of the gate trench 107 by using a thermal oxidation process, so that excellent interface characteristics of the silicon dioxide layer 112 and the gate trench 107 can be realized, interface state density between the silicon dioxide layer and the gate trench 107 is reduced, channel mobility of the gate trench 107 is improved, and on-resistance of the trench type SiC MOSFET device can be reduced.
As shown in fig. 11, a schematic structure of filling the upper surface of the dielectric layer in the gate trench with polysilicon of the first doping type is shown, and filling the upper surface of the dielectric layer 112 in the gate trench 107 with polysilicon 113 of the first doping type is shown in the following specific method:
growing a first doping type polysilicon layer 113 on the surface of the gate dielectric layer by using an LPCVD process, wherein the growth temperature is 600-800 ℃, preferably 650-750 ℃, and in the embodiment, 700 ℃ is selected; and sequentially etching the polysilicon layer 113 and the dielectric layer 112 with the first doping type by utilizing an ICP etching process to remove the polysilicon layer 113 and the dielectric layer 112 in the area outside the gate groove.
As shown in fig. 12, a source window is formed in the passivation layer, a passivation layer 114 is formed on the polysilicon layer 113 and the upper surface of the source region 106, and a source window 115 is formed in the passivation layer.
In one aspect, the passivation layer 114 is mainly used for forming a device surface protection film and overcoming device surface defects, and enhancing the stability and reliability of the device, and the passivation layer 114 may be made of one or two composite layers of silicon dioxide or nitride, for example.
On the other hand, the method of forming the source window 115 in the passivation layer 114 may be RIE etching or ICP etching, where the source window 115 exposes the source region 106 and the buried layer bottom contact region 110.
As shown in fig. 13, a source ohmic contact layer 116 is formed in the source window 115, and a drain ohmic contact layer 117 is formed on the lower surface of the substrate.
As shown in fig. 14, a schematic structure is shown in which a gate window 118 is formed in the passivation layer 114 at a position corresponding to the polysilicon region.
As an example, the method of forming the gate window 118 may be RIE etching or ICP etching.
As shown in fig. 1, a schematic structure of a trench SiC MOSFET device according to an embodiment of the present invention is shown, in which a gate electrode 119 is formed in a gate window 118, a source electrode 120 is formed on an upper surface of a source ohmic contact layer 116, and a drain electrode 121 is formed on a lower surface of a drain ohmic contact layer 117.
According to the invention, the source groove 108 is formed by etching the source electrode, the buried layer bottom contact region 110 and the buried layer side wall contact region 111 are formed on the side wall and the bottom of the source groove 108 by ion implantation, and the coupling effect of the buried layer bottom contact region 110 converts the capacitance of the side wall of the gate electrode and the drain electrode into the series connection of the gate-source capacitance and the drain-source capacitance, so that the gate-drain capacitance is greatly reduced. Because the existence of the buried layer bottom contact region 110 and the buried layer side wall contact region 111 makes the current path of the device in forward conduction narrower than that of the traditional trench structure, the on-resistance is obviously increased, so that the lateral surface of the epitaxial layer and the gate oxide protection region are wrapped by introducing a wrapping region with higher doping concentration than that of the epitaxial layer, and the depletion region area of the gate oxide protection region is reduced, so that the influence of the on-resistance increase caused by the buried layer bottom contact region 110 and the buried layer side wall contact region 111 is compensated. Finally, on the premise of maintaining the slightly increased on-resistance of the trench MOSFET, the gate-drain capacitance is obviously reduced, the switching speed of the device is improved, and the switching loss is reduced. In addition, the device structure and the preparation method are simple, and the effect is obvious, so that the preparation and the production of the high-performance and batched groove type SiC MOSFET device can be realized, and the device has huge market potential and wide application prospect. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (11)
1. A trench SiC MOSFET device, comprising:
a substrate (101);
a buffer layer (102) located on the upper surface of the substrate (101);
a first epitaxial layer (103) located on the upper surface of the buffer layer (102);
a wrapping region (104) located over the interior of the first epitaxial layer (103);
a second epitaxial layer (105) located on the upper surface of the first epitaxial layer (103);
a source region (106) located on the upper surface of the second epitaxial layer (105);
a gate trench (107) located in the wrapped-around region (104), the second epitaxial layer (105) and the source region (106);
a gate oxide protection region (109) located in the gate trench (107);
a dielectric layer (112) located on the surface of the gate trench (107);
a polysilicon layer (113) filled on the surface of the dielectric layer (112) in the gate trench (107);
a source trench (108) located outside the first epitaxial layer (103), the second epitaxial layer (105) and the source region (106);
a buried layer bottom contact region (110) and a buried layer sidewall contact region (111) located in the source trench (108);
a passivation layer (114) between the source electrode (120) and the gate electrode (119), on the surfaces of the polysilicon layer (113) and the source region (106);
a source ohmic contact layer (116) located on the surfaces of the source region (106), the buried layer bottom contact region (110) and the sidewall contact region (111);
a drain ohmic contact layer (117) located on a lower surface of the bottom of the substrate (101);
a gate electrode (119) located on the upper surface of the polysilicon layer (113);
a source electrode (120) located on an upper surface of the source ohmic contact layer (116);
and a drain electrode (121) positioned on the lower surface of the drain ohmic contact layer (117).
2. The trench SiC MOSFET device according to claim 1, characterized in that the substrate (101), buffer layer (102) and source region (106) are heavily doped of a first doping type; the first epitaxial layer (103) and the wrapping region (104) are lightly doped with a first doping type; the second epitaxial layer (105) is lightly doped of a second doping type; the gate oxide protection region (109) and the buried layer bottom contact region (110) are heavily doped with a second doping type; the polysilicon layer (113) is of a first doping type.
3. The trench SiC MOSFET device according to claim 1, characterized in that the wrapped-around region (104) has a depth of 1.4-2.0 μm, a width of 4.4-5.8 μm, a doping concentration of 1e 16-7 e16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the First, theThe depth of the two epitaxial layers (105) is 0.5-0.8 μm, the doping concentration is 1e 17-1 e18cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The depth of the source region (106) is 0.2-0.4 μm, the width is 6.0-6.8 μm, and the doping concentration is 1e 19-1 e20cm -3 。
4. A trench SiC MOSFET device according to claim 1, characterized in that the gate trench (107) has a width of 3.5-4.5 μm and a depth of 1.2-2.2 μm; the width of the source trench (108) is 2.2-2.5 mu m, and the depth is the same as that of the gate trench (107); the depth of the gate oxide protection region (109) is 0.5-0.8 mu m, and the doping concentration is 8e 18-1 e20cm -3 。
5. The trench SiC MOSFET device according to claim 1, characterized in that the depth of the buried layer bottom contact region (110) is 0.7-1.1 μm; the width of the buried layer side wall contact region (111) is 0.3-0.6 mu m, and the doping concentration is 1e 19-1 e20cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the dielectric layer (112) is 40-60 nm.
6. A method of fabricating a trench SiC MOSFET device according to any one of claims 1 to 5, comprising the steps of:
forming a buffer layer (102) on the upper surface of a substrate (101);
forming a first epitaxial layer (103) on the upper surface of the buffer layer (102);
forming a wrapping region (104) over an interior of the first epitaxial layer (103);
forming a second epitaxial layer (105) on the upper surface of the first epitaxial layer (103);
forming a source region (106) on the upper surface of the second epitaxial layer (105);
etching the source region (106), the second epitaxial layer (105) and the first epitaxial layer (103) to obtain a gate trench (107) and a source trench (108);
forming a gate oxide protection region (109) in the gate trench (107);
forming a buried layer bottom contact region (110) and a buried layer side wall contact region (111) in the source trench (108);
forming a dielectric layer (112) on the upper surfaces of the buried layer bottom contact region (110), the buried layer side wall contact region (111), the side wall of the gate trench (107) and the gate oxide protection region (109);
filling a polysilicon layer (113) on the upper surface of a dielectric layer (112) in the gate trench (107);
forming a passivation layer (114) on the upper surfaces of the polysilicon layer (113) and the source region (106), thereby forming a source window (115);
forming a source ohmic contact layer (116) on the source window (115), and forming a drain ohmic contact layer (117) on the lower surface of the substrate (101);
etching at the passivation layer (114) to obtain a gate window (118) exposing the polysilicon layer region;
a gate electrode (119) is formed in the gate window (118), a source electrode (120) is formed on the upper surface of the source ohmic contact layer (116), and a drain electrode (121) is formed on the lower surface of the drain ohmic contact layer (117).
7. The method of manufacturing a trench SiC MOSFET device according to claim 6, characterized in that a wrapped-around region (104) is formed over the interior of the first epitaxial layer (103), in particular by:
forming an ion implantation mask layer on the surface of the first epitaxial layer, coating photoresist, performing patterning treatment to obtain patterned photoresist, performing etching treatment on the ion implantation mask layer to form an ion implantation window, removing the patterned photoresist, performing nitrogen ion vertical implantation on the first epitaxial layer to form a lightly doped wrapping region of a first doping type, and removing the etched ion implantation mask layer.
8. The method for manufacturing the trench type SiC MOSFET device according to claim 6, wherein the source region (106), the second epitaxial layer (105) and the first epitaxial layer (103) are etched to obtain the gate trench (107) and the source trench (108), specifically comprising the steps of:
etching mask layer is grown on the surface of the source region, and compact and uniform SiO is grown through chemical vapor deposition process 2 A film; coating photoresist on the surface of the etching mask layer, and performing patterning treatment to obtain a patterned photoresist layer; according toPerforming reactive ion etching on the etching mask layer by the patterned photoresist layer to form a patterned etching mask layer; removing the patterned photoresist layer, and performing inductively coupled plasma etching on the second epitaxial layer and the source region according to the patterned etching mask layer to form a gate trench and a source trench; removing the patterned etching mask layer; and performing high-temperature passivation treatment, and performing morphology modification on the gate trench and the source trench.
9. The method of manufacturing a trench SiC MOSFET device according to claim 6, characterized in that a buried bottom contact region (110) and a buried sidewall contact region (111) are formed in the source trench (108), in which the method is as follows:
forming an ion implantation mask layer on the surfaces of the source groove and the first epitaxial layer, coating photoresist on the surfaces, and performing patterning treatment to obtain patterned photoresist; etching the ion implantation mask layer according to the patterned photoresist to form an ion implantation window; removing the patterned photoresist, and performing aluminum ion vertical implantation on the first epitaxial layer according to the etched ion implantation mask layer to form a buried layer bottom contact region; removing the etched ion implantation mask layer; obtaining a heavily doped buried layer bottom contact region of a second doping type; forming an ion implantation mask layer on the surface of the side wall of the source trench; and similarly, the buried layer side wall contact region is obtained through aluminum ion inclined implantation.
10. The method for manufacturing the trench type SiC MOSFET device according to claim 6, wherein a dielectric layer (112) is formed on the upper surfaces of the buried layer bottom contact region (110), the buried layer sidewall contact region (111), the sidewall of the gate trench (107) and the gate oxide protection region (109), specifically comprising the steps of:
and growing a silicon dioxide layer on the surfaces of the bottom contact region of the buried layer, the side wall of the gate groove and the gate oxide protection region by utilizing a thermal oxidation process, and carrying out annealing treatment on the silicon dioxide layer.
11. The method for manufacturing the trench type SiC MOSFET device according to claim 6, characterized in that the polysilicon layer (113) is filled on the upper surface of the dielectric layer (112) in the gate trench (107), specifically comprising the steps of:
and growing a polysilicon layer of a first doping type on the surface of the dielectric layer by utilizing low-pressure chemical vapor deposition, sequentially etching the polysilicon layer 113 and the dielectric layer, removing the redundant polysilicon layer and the dielectric layer outside the gate trench, exposing the source region, and flushing the rest polysilicon layer and the source region.
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