CN111900209A - Silicon carbide oxide field effect transistor with groove structure and preparation method thereof - Google Patents
Silicon carbide oxide field effect transistor with groove structure and preparation method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 65
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 65
- 230000005669 field effect Effects 0.000 title claims abstract description 15
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000007547 defect Effects 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 238000001259 photo etching Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910002804 graphite Inorganic materials 0.000 claims description 6
- 239000010439 graphite Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 239000012300 argon atmosphere Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 238000000407 epitaxy Methods 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005234 chemical deposition Methods 0.000 description 2
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- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention relates to a silicon carbide oxide field effect transistor with a groove structure and a preparation method thereof, wherein a double-layer epitaxy process is adopted in a double-groove grid MOSFET device, the electric field strength of a grid insulating film is dispersed, and a high-concentration doped p + type body layer is formed at the bottom of a groove so as to protect the insulating film on the bottom surface of a grid region. In addition, the method of oxidizing the insulating layer on the side wall of the trench by N2O gas directly by LPCVD at high temperature is used to reduce defects and fix the thickness, thereby improving the performance and producing highly reliable devices.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon carbide oxide field effect transistor with a groove structure and a preparation method thereof.
Background
SiC power semiconductors have excellent material characteristics compared to currently used silicon power semiconductors, and thus are widely used in high-current switching devices such as hybrid power (HV) and Electric Vehicles (EV), consumer electronics and industrial inverters, solar inverters, discontinuous power supplies (UPS), and the like, and in particular, in motor integrated control devices in the field of electric vehicles, it is expected that high-frequency, low-noise, small and light inverters will be obtained.
As shown in fig. 1, a conventional general conventional SiC trench MOSFET device first grows an active region n-type SiC layer 2 'and a p-type body SiC layer 4' on an n + type SiC substrate 1 ', as doped with high concentration, sequentially forms a source region 5' and a ground region 6 ', and forms a source electrode 7'. In addition, after a gate insulator film trench gate oxide (sacrificial) layer 9 'is formed on the sidewalls and bottom surface of the trench gate region, the trench is filled with an n + poly electrode 10', followed by the growth of the drain electrode 14 'structure and the formation of the gate 11'. The reliability of such a device structure is a significant problem, and the internal electric field is concentrated on the trench bottom surface, which results in a high current density and a vulnerable region.
Disclosure of Invention
Aiming at the problems in the prior art, the invention aims to provide a silicon carbide oxide field effect transistor with a groove structure and a preparation method thereof, which can solve the problem of easy damage caused by a strong electric field and improve the reliability of the field effect transistor.
In order to achieve the purpose, the invention adopts the technical scheme that:
a silicon carbide oxide field effect transistor with a groove structure is provided with an n + type SiC substrate, an n-type SiC layer and an insulating layer in sequence from bottom to top;
a drain electrode metal electrode is arranged on the lower end face of the n + type SiC substrate;
a p + type buried layer is arranged at the position, close to the n-type SiC layer, of the n-type SiC layer;
the n-type SiC layer is provided with a p-type epitaxial layer and a protective ring-shaped junction, the p-type epitaxial layer is provided with a p + ground electrode, an n + source electrode and a grid groove, and a grid bottom insulating layer, a groove grid oxidation insulating layer and an n + polycrystalline electrode are arranged in the grid groove;
and a source metal electrode and a grid metal electrode are arranged on the insulating layer, and the source metal electrode is in contact with the n + polycrystalline electrode.
The insulating layer includes an oxide layer and an ILD insulating layer, the oxide layer being in contact with the n-type SiC layer.
A preparation method of a silicon carbide oxide field effect transistor with a groove structure comprises the following steps:
and 3, removing the oxide film shielded in the previous step, covering the oxide film and the photoresist again, photoetching the defined position of the p-type epitaxial layer, and injecting aluminum dopant into the photoetching position at high temperature.
removing the oxide film shielded in the previous step, covering the oxide film and the photoresist again, photoetching a p + grounding defined position, and injecting aluminum dopant into the p + grounding defined position;
alternately stacking an oxide film and polycrystalline silicon on the lower surface of the n + type SiC substrate wafer to a required thickness; polishing and plating nickel metal, and then performing RTP process treatment at 1000 ℃ under the argon atmosphere under the atmospheric pressure to form ohmic contact;
and (3) introducing H2/N2 at the atmospheric pressure at 450 ℃, cleaning the lower surface of the N + type SiC substrate, plating a Ti/Ag film by using electron beams to form a drain metal electrode, and then carrying out heat treatment to complete the arrangement of the metal electrode.
After adopting the scheme, the invention adopts a double-layer epitaxial process in the double-groove gate MOSFET device, disperses the electric field intensity of the gate insulating film, and forms a high-concentration doped p + type body layer at the bottom of the groove so as to protect the insulating film on the bottom surface of the gate region. In addition, the method of oxidizing the insulating layer on the side wall of the trench by N2O gas directly by LPCVD at high temperature is used to reduce defects and fix the thickness, thereby improving the performance and producing highly reliable devices.
Drawings
FIG. 1 is a schematic diagram of a prior art FET structure;
FIG. 2 is a schematic view of a field effect transistor structure of the present invention;
fig. 3-10 are flow charts of the field effect transistor fabrication of the present invention.
Detailed Description
As shown in fig. 2, the invention discloses a silicon carbide oxide field effect transistor with a trench structure, which is provided with an n + type SiC substrate 1, an n-type SiC layer 2, an n-type SiC layer 3 and an insulating layer in sequence from bottom to top;
a drain electrode metal electrode 14 is arranged on the lower end face of the n + type SiC substrate 1;
a p + type buried layer 15 is arranged at the position, close to the n-type SiC layer 3, of the n-type SiC layer 2;
the n-type SiC layer 3 is provided with a p-type epitaxial layer 4 and a protective ring-shaped junction 13, the p-type epitaxial layer 4 is provided with a p + ground 6, an n + source 5 and a grid groove 8, and a grid bottom insulating layer 12, a groove grid oxidation insulating layer 9 and an n + polycrystalline electrode 10 are arranged in the grid groove 8;
and a source metal electrode 7 and a gate metal electrode 11 are arranged on the insulating layer, and the source metal electrode 7 is in contact with the n + polycrystalline electrode 10.
As shown in fig. 3 to fig. 10, the present invention further discloses a method for manufacturing a silicon carbide oxide field effect transistor with a trench structure, which comprises the following steps:
And 3, removing the shielded oxide film in the previous step, covering the oxide film and the photoresist again, photoetching the defined position of the p-type body epitaxial layer 4, and injecting aluminum dopant into the photoetching position at the temperature of 600 ℃.
And 4, covering photoresist after the previous step is completed, photoetching the defined position of the N + source 5, and injecting N-nitrogen doping substances into the defined position of the N + source 5 at the temperature of 600 ℃. Removing the oxide film shielded in the previous step, covering the oxide film and the photoresist again, photoetching the defined position of the p + grounding 6, and injecting aluminum doping into the defined position of the p + grounding 6 at the temperature of 600 ℃.
And 5, removing the shielded oxide film in the previous step, covering a layer of photoresist again, heating at 1600-1700 ℃ for 30 minutes-1 hour, and activating the impurities doped in the steps 1-4 to form a p + type buried layer 15, a protective ring type junction 13 (at a protective region), a p type epitaxial layer 4, an n + source 5 and a p + ground 6. At high temperatures, the photoresist graphitizes (burns); the graphite covering the surface can prevent the silicon carbide on the surface from sublimating.
And 8, growing a BPSG film by LPCVD (low pressure chemical vapor deposition) and HTO (High Temperature Oxidation), and then introducing nitrogen (N2) at the atmospheric pressure of 900 ℃ to grow an ILD insulating layer. Then covering photoresist protection on the ILD insulating layer; alternately stacking an oxide film and polysilicon on the lower surface of the n + type SiC substrate 1 to a required thickness; and then polishing by CMP, plating nickel metal, and then performing RTP (rapid thermal processing) process for 3 minutes at 1000 ℃ under the atmosphere of atmospheric pressure argon to form ohmic contact.
The invention adopts a double-layer epitaxial process in a double-groove gate MOSFET device, disperses the electric field strength of a gate insulating film, and forms a high-concentration doped p + type body layer at the bottom of a groove so as to protect the insulating film on the bottom surface of a gate region. In addition, the method of oxidizing the insulating layer on the side wall of the trench by N2O gas directly by LPCVD at high temperature is used to reduce defects and fix the thickness, thereby improving the performance and producing highly reliable devices.
The above description is only exemplary of the present invention and is not intended to limit the technical scope of the present invention, so that any minor modifications, equivalent changes and modifications made to the above exemplary embodiments according to the technical spirit of the present invention are within the technical scope of the present invention.
Claims (3)
1. A silicon carbide oxide field effect transistor with a groove structure is characterized in that: an n + type SiC substrate, an n-type SiC layer and an insulating layer are sequentially arranged from bottom to top;
a drain electrode metal electrode is arranged on the lower end face of the n + type SiC substrate;
a p + type buried layer is arranged at the position, close to the n-type SiC layer, of the n-type SiC layer;
the n-type SiC layer is provided with a p-type epitaxial layer and a protective ring-shaped junction, the p-type epitaxial layer is provided with a p + ground electrode, an n + source electrode and a grid groove, and a grid bottom insulating layer, a groove grid oxidation insulating layer and an n + polycrystalline electrode are arranged in the grid groove;
and a source metal electrode and a grid metal electrode are arranged on the insulating layer, and the source metal electrode is in contact with the n + polycrystalline electrode.
2. The silicon carbide oxide field effect transistor with a trench structure of claim 1, wherein: the insulating layer includes an oxide layer and an ILD insulating layer, the oxide layer being in contact with the n-type SiC layer.
3. A preparation method of a silicon carbide oxide field effect transistor with a groove structure is characterized by comprising the following steps: the method comprises the following steps:
step 1, sequentially growing an n-type SiC epitaxial layer and an oxide film on an n + type SiC substrate wafer, covering a layer of photoresist on the oxide film, and photoetching the position of a p + type buried layer; injecting high-concentration aluminum into the photoetching position at high temperature;
step 2, removing the oxide film shielded in the previous step, growing an n-type SiC epitaxial layer on the n-type SiC epitaxial layer, and growing an oxide film on the n-type SiC epitaxial layer; covering a layer of photoresist, photoetching a protection region, and injecting aluminum doping substances into the protection region at high temperature;
step 3, removing the oxide film shielded in the previous step, covering the oxide film and the photoresist again, photoetching the defined position of the p-type body epitaxial layer, and injecting aluminum dopant into the photoetching position at high temperature;
step 4, after the previous step is completed, continuing covering the photoresist, photoetching the defined position of the N + source, and injecting N-nitrogen doping substances into the defined position of the N + source at high temperature;
removing the oxide film shielded in the previous step, covering the oxide film and the photoresist again, photoetching a p + grounding defined position, and injecting aluminum dopant into the p + grounding defined position;
step 5, removing the oxide film shielded in the previous step, covering a layer of photoresist again, activating the impurities doped in the steps 1-4 to form a p + type buried layer, a protective ring type junction, a p type epitaxial layer, an n + source and a p + grounding layer, and graphitizing the photoresist to form a graphite layer;
step 6, removing the graphite layer in the previous step, then sequentially generating a first oxide film, polycrystalline silicon and a second oxide film by a CVD method, and etching a U-shaped grid groove of a grid region; coating an oxide layer in the U-shaped grid groove and carrying out a thermal hardening treatment, thereby forming an oxide film at the bottom of the groove, wherein the thickness of the oxide film is kept between 0.5 and 1 mu m;
step 7, growing a 50-100nm groove gate oxide insulating layer in the U-shaped gate groove by adopting a gas growth mode, and then introducing mixed gas of N2O and N2 at high temperature to enable the defect opening of the SiC/SiO2 contact surface to exist originally, and forming a nitride film by mixed nitrogen gas; then, cleaning the nitride film on the surface by phosphoric acid, and removing the polysilicon and the second oxide film; growing n + polycrystalline state electrodes on the U-shaped grid grooves;
step 8, growing a BPSG film on the first oxide film, introducing nitrogen at the atmospheric pressure of 900 ℃ to form an ILD insulating layer, and covering the ILD insulating layer with photoresist for protection;
alternately stacking an oxide film and polycrystalline silicon on the lower surface of the n + type SiC substrate wafer to a required thickness; polishing and plating nickel metal, and then performing RTP process treatment at 1000 ℃ under the argon atmosphere under the atmospheric pressure to form ohmic contact;
step 9, defining the position of an upper source electrode metal electrode on the IDL insulating layer, and etching a source region; sequentially and alternately stacking the oxide film and the polycrystalline silicon to the required thickness, plating nickel metal, and then carrying out RTP (real time processing) process treatment at 1000 ℃ under the atmosphere of atmospheric pressure argon to form ohmic contact;
step 10, cleaning the upper surface of the ILD insulating layer, and plating a TiW/AlSi alloy thick film; photoetching a needed grid metal electrode and a needed source metal electrode;
and (3) introducing H2/N2 at the atmospheric pressure at 450 ℃, cleaning the lower surface of the N + type SiC substrate, plating a Ti/Ag film by using electron beams to form a drain metal electrode, and then carrying out heat treatment to complete the arrangement of the metal electrode.
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