JP6372436B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  At the oxide film / silicon interface in the gate oxide film, the surface of the pn junction structure, and the like, the interface state greatly affects the electrical characteristics, and thus the interface state density needs to be reduced. Taking a MOS (Metal Oxide Semiconductor) structure as an example, an increase in interface state density affects carrier mobility and causes variation in threshold voltage. Further, in the pn junction structure, it affects the surface recombination speed (surface generated current).

  As a method for reducing the interface state density, so-called sintering treatment, in which heat treatment is performed with a gas containing hydrogen at a temperature of about 450 ° C., has been performed. However, as described in Non-Patent Document 1, hydrogen is easily desorbed by heat treatment, and the effect may be limited.

  As a method different from the sinter treatment with hydrogen, Patent Document 1 discloses a method for improving the interface state by ion implantation of fluorine. Fluorine improves the interface state instead of hydrogen. However, this method requires a fluorine ion implantation apparatus, which makes implementation large.

  In addition to this, for example, Patent Document 2 describes a method in which fluorine is contained in an oxide film embedded in a silicon substrate. However, since fluorine diffuses also to the back side of the silicon substrate, there is a limit to the amount of fluorine that can be included in the oxide film, and there is a problem that the introduction efficiency of fluorine is poor. As a method of improving this point, as disclosed in Patent Document 3, a method of forming a fluorine diffusion preventing layer has been proposed, but the structure becomes complicated.

  Patent Document 4 discloses a method for recovering crystallinity by annealing in an oxygen atmosphere after fluorine is ion-implanted in advance into a semiconductor layer of an SOI (Silicon On Insulator) substrate. This method can be applied to an SOI substrate, but is difficult to apply to a bulk wafer.

JP 2000-269492 A JP-A-3-149821 JP 2011-40422 A JP-A-2005-116607

K. Ohyu, T .; Itoga, Y. et al. Nishioka, and N.K. Natsuki, “Improvement of SiO 2 / Si Interface Properties Utilities Fluorine Ion Implantation and Drive-in Diffusion”, Jpn. J. et al. Appl. Phys. , 28, 1041 (1989) D. K. Schroder, Semiconductor Material and Device Characterisation 3ed ed.

  On the other hand, the gas containing fluorine is a gas generally used as a substrate processing gas such as silicon, that is, an etching gas. The etching using a gas containing fluorine is a method in which an electrode is placed in a vacuum chamber, a silicon substrate is placed in the vacuum chamber, and plasma is generated using a high frequency power source for etching. In general, the electrodes are installed above and below the chamber, and a silicon substrate is installed on the lower electrode side. At this time, the high frequency power source connected to the electrode on the silicon substrate side is called a cathode coupling (cathode coupling) method, and the one connected to the opposite electrode is called an anode coupling (anode coupling) method. It is generally said that the cathode coupling method in which a high-frequency power source is connected to the electrode on the silicon substrate side causes significant damage to the substrate because ions physically collide with the silicon substrate.

  As described above, fluorine is useful as an etching gas and is very effective for improving the interface state density. In order to improve the interface state density using fluorine, fluorine ions are used. There was a problem that an injection process was additionally required.

  The present invention has been made in view of the above problems, and provides a method for manufacturing a semiconductor device that can improve the interface state density without requiring a fluorine ion implantation step or formation of a special structure. The purpose is to provide.

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device,
After a silicon substrate is etched using a fluorine-containing gas in a cathode coupling type plasma etching apparatus, the plasma etching apparatus is switched to an anode coupling type, and plasma treatment is performed using a gas containing fluorine on the silicon substrate. Performing and depositing fluorine on the surface of the silicon substrate;
Performing a heat treatment on the silicon substrate on which the fluorine is deposited, and diffusing the deposited fluorine into the silicon substrate;
A method for manufacturing a semiconductor device is provided.

  In this way, if a silicon substrate is etched using a fluorine-containing gas in a cathode coupling plasma etching apparatus, and then switched to the anode coupling system and plasma treatment is performed, a fluorine ion implantation process is performed. Even if it is not, the fluorine passivation of the interface state can be efficiently performed by using the etching process, and an increase in the number of processes can be suppressed. Further, it is not necessary to provide a special structure in the silicon substrate for improving the interface state density, and an increase in manufacturing cost of the semiconductor device can be suppressed.

  At this time, the heat treatment is preferably performed at 800 ° C. or higher and 1050 ° C. or lower.

  With the heat treatment at such a temperature, the interface state density can be effectively reduced.

  As described above, according to the present invention, it is possible to efficiently perform fluorine passivation of the interface state using the etching process, thereby suppressing an increase in the number of processes required for reducing the interface state density, thereby , Increase in cost can be suppressed.

It is a figure which shows the process flow of the manufacturing method of the semiconductor device of this invention. It is the schematic which shows a cathode coupling system ((a)) and an anode coupling system ((b)). It is the schematic which shows an example of the plasma etching apparatus which can switch a cathode coupling system and an anode coupling system. It is a graph which shows the relationship between heat processing temperature and an interface state density.

Hereinafter, the present invention will be described in more detail.
As described above, in a method for manufacturing a semiconductor device, there is a need for a method for manufacturing a semiconductor device that can improve the interface state density without performing a fluorine ion implantation step or forming a special structure.

As a result of intensive studies to achieve the above-mentioned object, the present inventor, after etching a silicon substrate using a fluorine-containing gas in a cathode coupling type plasma etching apparatus, the plasma etching apparatus is subjected to anode coupling. Switching to a method, performing a plasma treatment using a gas containing fluorine on the silicon substrate, and depositing fluorine on the surface of the silicon substrate;
Performing a heat treatment on the silicon substrate on which fluorine is deposited, and diffusing the deposited fluorine into the silicon substrate;
It has been found that a method for manufacturing a semiconductor device having the above can solve the above problems, and the present invention has been completed.

  Hereinafter, the present invention will be described in detail as an example of an embodiment with reference to the drawings, but the present invention is not limited thereto.

  First, in FIG. 2, the schematic of each of a cathode coupling system ((a)) and an anode coupling system ((b)) is shown. 2A and 2B, a wafer (substrate) 3, an electrode 4 or 7, and a stage 2 on which the wafer 3 is placed are provided inside the chamber 1. Then, an etching gas 6 is introduced into the chamber 1. Waste gas after etching is exhausted from an exhaust port (not shown). Here, in the cathode coupling type (system) in which the high frequency oscillator 5 is installed on the wafer 3 side, ions generated in the generated plasma are attracted to the wafer 3 side, so that damage is easily introduced into the substrate. On the other hand, the anode coupling type (system) has little damage to the substrate because a potential is mainly applied to the upper portion of the substrate. In the plasma etching, etching proceeds using physical collision of generated ions in the cathode coupling type, and etching proceeds by a chemical reaction by a radical component in the anode coupling type.

  Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described with reference to a process flow shown in FIG.

  Using the above-described characteristics of the cathode coupling method and the anode coupling method, first, the silicon substrate is etched using a gas containing fluorine in a cathode coupling type plasma etching apparatus. This etching also serves to introduce fluorine ions generated from the etching gas into the silicon substrate by applying a high electric field. Next, switch to the anode coupling method, plasma treatment is performed on the silicon substrate with a gas containing fluorine, the damaged layer is removed by chemical etching (also isotropic etching), and fluorine is deposited on the surface of the silicon substrate. (Step A in FIG. 1).

  Thereafter, annealing (heat treatment) is performed to recover the damage introduced by the cathode coupling etching and to diffuse the fluorine deposited on the surface of the silicon substrate (step B in FIG. 1). Thereby, fluorine can be diffused into the silicon substrate while recovering plasma damage.

  For switching from the cathode coupling method to the anode coupling method, it is preferable to use a plasma etching apparatus having a changeover switch as shown in FIG. In the plasma etching apparatus 60 shown in FIG. 3, an upper electrode 17 and a lower electrode 18 are provided in the chamber 11. The wafer 13 is placed on the lower electrode 18. The lower electrode 18 also functions as a wafer stage. Then, an etching gas 16 is introduced into the chamber 11.

  The plasma etching apparatus 60 includes a terminal 21 connected to the high frequency oscillator 15, a grounded terminal 22, and a changeover switch 20. In FIG. 3, the upper electrode 17 is connected to the terminal 22 on the ground side, and the lower electrode 18 is connected to the terminal 21 on the high frequency oscillator side, which is cathode coupling. When the changeover switch 20 is operated and the connection of the upper electrode 17 is switched from the ground to the high frequency oscillator 15 side, and the connection of the lower electrode is switched from the high frequency oscillator 15 side to the ground side, anode coupling occurs.

  Further, the relationship between the heat treatment temperature and the interface state density obtained experimentally will be described below with reference to FIG.

First, a silicon single crystal substrate of P type doped with boron and having a diameter of 200 mm was prepared. The resistivity of this substrate is 10 Ω · cm. Plasma etching was performed on this substrate using CF ₄ as a gas containing fluorine. The etching conditions are: gas type and flow rate: CF ₄ : O ₂ = 80 sccm: 20 sccm, high frequency output Rf is 600 W, pressure is 0.05 Pa, and etching is performed for 2 minutes in the order of cathode coupling and anode coupling. And plasma treatment was performed.

  The gas flow rate ratio, high-frequency output, pressure, and etching time during plasma etching vary depending on the depth and shape required for processing. If the required depth of etching is deep, generally high frequency output, long time etching, and high gas flow rate are required. As a result, the film is exposed to a large amount of fluorine, and the etching time and fluorine passivation are considered to have a positive correlation.

  Next, the silicon single crystal substrate on which fluorine was deposited was annealed (heat treatment) in a nitrogen atmosphere for 30 minutes while changing the heat treatment temperature. Thereafter, the interface state density of the annealed silicon single crystal substrate was measured. The measurement results are shown in FIG.

  FIG. 4 is a graph showing the relationship between the heat treatment temperature and the interface state density. It can be seen that if the heat treatment temperature is 800 ° C. or higher and 1050 ° C. or lower, it is effective in reducing the interface state density.

  Even if the temperature of the heat treatment is higher than 1050 ° C., the effect is not changed. Further, since heat treatment at about 1000 ° C. is used for damage recovery in ion implantation or the like, it is determined that 1050 ° C. or less is sufficient for recovery from damage due to this etching.

The atmosphere is generally nitrogen (N ₂ ). In an oxidizing atmosphere, the surface of the silicon single crystal substrate may be oxidized, and the region into which fluorine has been introduced may be removed in another subsequent etching step.

  Furthermore, a heat treatment time of about 30 minutes is sufficient. Even if heat treatment is performed for 1 hour or more, there is no difference in effect.

  Note that the method for manufacturing a semiconductor device of the present invention can also be applied to etching for selectively removing a film to be processed after lithography, and removing a film formed over the entire surface of a silicon substrate. It can also be applied to etching.

  EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.

Example 1
As a sample for interface state density measurement, a P-type silicon single crystal substrate doped with boron (B) and having a diameter of 200 mm was used. The resistivity of this silicon single crystal substrate is 10 Ω · cm. Plasma etching was performed on this substrate using CF ₄ as an etching gas containing fluorine. Etching conditions were such that the gas type and flow rate were CF ₄ : O ₂ = 80 sccm: 20 sccm, the high-frequency output Rf was 600 W, the pressure in the chamber was 0.05 Pa, and etching was performed for 2 minutes with a cathode coupling type plasma etching apparatus. Thereafter, the plasma etching apparatus was switched to the anode coupling system, and plasma treatment was performed for 2 minutes under the same conditions to deposit fluorine. This plasma treatment includes etching and fluorine deposition. Thereafter, a silicon single crystal substrate on which fluorine has been deposited is subjected to a heat treatment at 1000 ° C. for 30 minutes in an N ₂ atmosphere, and then subjected to SC1 cleaning (with a mixed chemical solution of ammonium hydroxide / hydrogen peroxide solution / pure water). Washing).

Then, the silicon single crystal substrate after SC1 cleaning is subjected to gate oxidation with a thickness of 25 nm in a dry atmosphere at 900 ° C., and then a poly-Si (polycrystalline silicon) layer doped with phosphorus (P) is formed. The film was deposited at a thickness of 300 nm by a CVD (Chemical Vapor Deposition) method. At that time, the sheet resistance of the polycrystalline silicon layer is 30 Ω / sq. I tried to become. The silicon single crystal substrate was subjected to photolithography, and the polycrystalline silicon layer was selectively etched to form an electrode having an area of 1 mm ^{2 on} the substrate.

  Next, when the interface state density was determined by the CV method, the values shown in Table 1 were obtained. Table 1 is a table | surface which shows the interface state density calculated | required by Example 1 and Comparative Example 1-5 mentioned later. In Example 1, the interface state density is lower than that in Comparative Example 1 in which the interface state density reduction process was not performed, as in the case of performing the hydrogen sintering process shown in Comparative Example 2 described later. I understood that. The method for measuring the interface state density by the CV method is described in detail in Non-Patent Document 2, for example.

(Comparative Example 1)
As a sample for interface state density measurement, a boron-doped P-type silicon single crystal substrate having a diameter of 200 mm was used. The resistivity of this substrate is 10 Ω · cm. This silicon single crystal substrate is subjected to gate oxidation with a thickness of 25 nm in a dry atmosphere at 900 ° C., and then a poly-Si layer doped with phosphorus is deposited to a thickness of 300 nm by the CVD method. Sheet resistance is 30 Ω / sq. It was made to become. This silicon single crystal substrate was subjected to photolithography and etching to form an electrode having an area of 1 mm ^{2 on} the substrate.

  Next, when the interface state density was determined by the CV method, it was found that the interface state density was very large as shown in Table 1 unless the interface improvement treatment was performed as described above.

(Comparative Example 2)
As a sample for interface state density measurement, a boron-doped P-type silicon single crystal substrate having a diameter of 200 mm was used. The resistivity of this substrate is 10 Ω · cm. This substrate was gate-oxidized with a thickness of 25 nm in a dry atmosphere at 900 ° C., and then a Poly-Si layer doped with phosphorus was deposited with a thickness of 300 nm by a CVD method. At that time, the sheet resistance of this layer was 30 Ω / sq. It was made to become. This silicon single crystal substrate was subjected to photolithography and etching to form an electrode having an area of 1 mm ^{2 on} the substrate. Thereafter, heat treatment was performed for 30 minutes in a nitrogen atmosphere gas containing 2% hydrogen (hydrogen sintering treatment).

  Next, when the interface state density was determined by the CV method, as shown in Table 1, the interface state density was improved by performing the hydrogen sintering process.

  As described above, even in the hydrogen sintering process, there is an effect of reducing the interface state density at substantially the same level as in Example 1. However, as disclosed in Non-Patent Document 1 described above, hydrogen is easily desorbed by heat treatment, The effect may be limited. For this reason, as in Example 1, it is preferable to use fluorine that has a stable effect.

(Comparative Example 3)
As a sample for interface state density measurement, a boron-doped P-type silicon single crystal substrate having a diameter of 200 mm was used. The resistivity of this substrate is 10 Ω · cm. Plasma etching was performed on this substrate using CF ₄ as an etching gas containing fluorine. Etching conditions were such that the gas type and flow rate were CF ₄ : O ₂ = 80 sccm: 20 sccm, the high-frequency output Rf was 600 W, the pressure in the chamber was 0.05 Pa, and etching was performed for 2 minutes with a cathode coupling type plasma etching apparatus. . Plasma treatment by the anode coupling method was not performed. Thereafter, the silicon single crystal substrate was heat-treated in an N ₂ atmosphere at 1000 ° C. for 30 minutes, and then SC1 cleaning was performed.

Then, gate oxidation with a thickness of 25 nm is performed on the silicon single crystal substrate after SC1 cleaning in a dry atmosphere at 900 ° C., and then a Poly-Si layer doped with phosphorus is formed with a thickness of 300 nm by CVD. Deposited. At that time, the sheet resistance of this layer was 30 Ω / sq. It was made to become. This silicon single crystal substrate was subjected to photolithography and etching to form an electrode having an area of 1 mm ^{2 on} the substrate.

  Next, when the interface state density was determined by the CV method, as shown in Table 1, it was found that the interface state density was not improved as much as in Example 1 by only the cathode coupling etching.

(Comparative Example 4)
As a sample for interface state density measurement, a boron-doped P type silicon single crystal substrate having a diameter of 200 mm was used. The resistivity of this substrate is 10 Ω · cm. The same apparatus as the plasma etching apparatus used in Comparative Example 3 with the gas type and flow rate of CF ₄ : O ₂ = 80 sccm: 20 sccm, the high-frequency output Rf of 600 W, and the pressure in the chamber of 0.05 Pa is applied to this substrate. The plasma treatment was performed for 2 minutes after using the anode coupling method. Etching by the cathode coupling method was not performed. Thereafter, the silicon single crystal substrate was heat-treated in an N ₂ atmosphere at 1000 ° C. for 30 minutes, and then SC1 cleaning was performed.

Then, gate oxidation with a thickness of 25 nm is performed on the silicon single crystal substrate after SC1 cleaning in a dry atmosphere at 900 ° C., and then a Poly-Si layer doped with phosphorus is formed with a thickness of 300 nm by CVD. Deposited. At that time, the sheet resistance of this layer was 30 Ω / sq. It was made to become. This silicon single crystal substrate was subjected to photolithography and etching to form an electrode having an area of 1 mm ^{2 on} the substrate.

  Next, when the interface state density was determined by the CV method, as shown in Table 1, it was found that the interface state density was not improved as much as in Example 1 only by the plasma treatment of the anode coupling method. .

(Comparative Example 5)
As a sample for interface state density measurement, a boron-doped P-type silicon single crystal substrate having a diameter of 200 mm was used. The resistivity of this substrate is 10 Ω · cm. Plasma etching was performed on this substrate using CF ₄ as an etching gas containing fluorine. Etching conditions were such that the gas type and flow rate were CF ₄ : O ₂ = 80 sccm: 20 sccm, the high-frequency output Rf was 600 W, the pressure in the chamber was 0.05 Pa, and etching was performed for 2 minutes with a cathode coupling type plasma etching apparatus. Thereafter, the plasma etching apparatus was switched to the anode coupling method, and plasma treatment was performed for 2 minutes under the same conditions. Thereafter, SC1 cleaning was performed.

Then, the silicon single crystal substrate after the SC1 cleaning is subjected to gate oxidation with a thickness of 25 nm in a dry atmosphere at 900 ° C., and then a Poly-Si layer doped with phosphorus is formed by a CVD method at a thickness of 300 nm. Deposited. At that time, the sheet resistance of this layer was 30 Ω / sq. I tried to become. This silicon single crystal substrate was subjected to photolithography and etching to form an electrode having an area of 1 mm ^{2 on} the substrate.

  Next, when the interface state density was determined by the CV method, as shown in Table 1, it was found that the interface state density was not improved as much as in Example 1 unless heat treatment was performed.

  Thus, after etching a silicon substrate using an etching gas containing fluorine in a cathode coupling type plasma etching apparatus, switching to an anode coupling type plasma etching method, performing plasma treatment with a gas containing fluorine, The interface state density could be effectively reduced by depositing fluorine and then performing heat treatment. On the other hand, if any one of the cathode coupling type etching, the anode coupling type plasma treatment, and the heat treatment is not performed, the improvement of the interface state density is limited.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

1 ... chamber, 2 ... stage, 3 ... wafer, 4 ... electrode,
5 ... high frequency oscillator, 6 ... etching gas, 7 ... electrode, 11 ... chamber,
13 ... wafer, 15 ... high frequency oscillator, 16 ... etching gas,
17 ... Upper electrode, 18 ... Lower electrode, 20 ... Changeover switch,
21 ... a terminal on the high frequency oscillator side, 22 ... a terminal on the ground side,
60: Plasma etching apparatus.

Claims (2)

A method for manufacturing a semiconductor device, comprising:
After a silicon substrate is etched using a fluorine-containing gas in a cathode coupling type plasma etching apparatus, the plasma etching apparatus is switched to an anode coupling type, and plasma treatment is performed using a gas containing fluorine on the silicon substrate. Performing and depositing fluorine on the surface of the silicon substrate;
Performing a heat treatment on the silicon substrate on which the fluorine is deposited, and diffusing the deposited fluorine into the silicon substrate;
A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at 800 ° C. or higher and 1050 ° C. or lower.

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