CN103107086B - Manufacturing technique of low-voltage chip and low-voltage chip thereof - Google Patents
Manufacturing technique of low-voltage chip and low-voltage chip thereof Download PDFInfo
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- CN103107086B CN103107086B CN201310033221.4A CN201310033221A CN103107086B CN 103107086 B CN103107086 B CN 103107086B CN 201310033221 A CN201310033221 A CN 201310033221A CN 103107086 B CN103107086 B CN 103107086B
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Abstract
The invention belongs to the technical field of chip manufacturing and preparation, and particularly relates to a manufacturing technique of a low-voltage chip and the low-voltage chip thereof. The manufacturing technique comprises the following steps: (1), a P-shaped primary silicon slice is selected; (2) boron impurities are pre-processed before spreading; (3) the boron impurities are spread; (4) crystal separation and cleaning are conducted; (5) phosphorus impurities are spread; (6) crystal separation and cleaning are conducted; (7) table board processing is conducted; (8) cleaning is conducted before passivation; (9) sodion is cleaned; (10) glass is passivated; and (11) a finished product is manufactured. The manufacturing technique is simple and easy to operate. The low-voltage chip manufactured by the manufacturing technique is low in leakage value and capable of meeting the requirement of low leakage.
Description
Technical field
The invention belongs to technical field prepared by chip production, be specifically related to a kind of production technology and low-voltage chip thereof of low-voltage chip.
Background technology
The electric leakage of current low-voltage chip is large, is difficult to meet current client to the more and more stricter requirement of this parameter, such as, within the leakage current that the transient state of 6.8V voltage restrains diode chip goes survey cannot accomplish 20 μ A by its operating voltage.In order to meet the requirement of Low dark curient, the method for some employing shallow junctions diffusion, but cause easy in the process of metal with silicon alloy and PN junction conducting like this, cause product failure.Existing low-voltage chip produces the thickness adopting low temperature oxidation technology can not meet oxide layer, cannot play the object of passivation, more cannot meet the tendency freely in packaging technology.Low pressure diffusion can not accomplish that junction depth can reach again the requirement of surge and VC more than 23 μm.Clean and the protection at mesa technique PN junction place are most important, and be subject to the restriction of environment and process conditions, the cleannes of existing technique are difficult to reach technical requirement.
Summary of the invention
The object of the invention is to the defect for above-mentioned existence and provide a kind of production technology and low-voltage chip thereof of low-voltage chip, this technique is simple to operation, and the low-voltage chip electrical leakage prepared by this technique is low, meets the requirement of Low dark curient.
Technical scheme of the present invention is: a kind of production technology of low-voltage chip, comprises the following steps:
(1) choose the former silicon chip of P type: select resistivity to be 0.002 ~ 0.0037 ohm/cm, thickness is the former silicon chip of P type of 290 ~ 340 microns;
(2) preliminary treatment before boron impurity diffusion: first the former silicon chip of P type selected by step (1) is carried out chemical corrosion 30 seconds under 1 ~ 3 DEG C of temperature conditions in the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in No. I liquid by hydrogen peroxide, ammoniacal liquor and water proportioning after being rinsed well in pure water by former for P type silicon chip, make the former silicon chip of P type at 80 ~ 95 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Rinse well with water after cleaning in No. I liquid, former for P type silicon chip is placed in by No. II liquid heat temperature raising of hydrogen peroxide, hydrochloric acid and water proportioning again, make the former silicon chip of P type at 80 ~ 95 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: hydrochloric acid: water is 1:1:6; Finally bath cleans up and dries;
(3) boron impurity diffusion: the former silicon chip of pretreated P type is positioned in stove, heat temperature raising, under 1200 ~ 1300 DEG C of conditions, carry out the diffusion of boron impurity, be then cooled to 500 ~ 600 DEG C and come out of the stove, the upper and lower surface of the former silicon chip of P type is formed P+ diffusion layer;
(4) brilliant point/clean: the former silicon chip of P type step (3) being completed boron impurity diffusion is positioned in hydrofluoric acid and soaks separately, then be positioned over pure water interior bath cleaning 1 hour, described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: enter stove under 200 ~ 400 DEG C of conditions, be heated to 900 DEG C and carry out the diffusion of first paragraph phosphorus impurities; Carry out the diffusion of second segment phosphorus impurities under being heated to 1200 ~ 1300 DEG C of conditions again, complete the diffusion of whole phosphorus impurities, form phosphorus impurities diffusion layer, be finally cooled to 500 ~ 600 DEG C and come out of the stove, between P+ diffusion layer and phosphorus impurities diffusion layer, form U-shaped PN junction;
(6) brilliant point/cleaning: the former silicon chip of P type step (5) being completed phosphorus impurities diffusion is positioned in hydrofluoric acid and soaks separately, then cleaning 1 hour of washing by water in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblasting; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) cleaning before passivation: after first the wafer of completing steps (7) being cleaned a minute with the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then to wash by water cleaning after 10 minutes, then put into by the solution of hydrofluoric acid and water proportioning except oxide layer, wherein hydrofluoric acid by volume: water is 1:1; Last at 80 ~ 95 DEG C heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule and is heated to 1200 DEG C and injects chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped PN junction place sodium ion, scavenging period is 30 ~ 60 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product makes: cleaning before nickel plating; Nickel plating/alloy; Scribing; Test; Packaging.
In described step (3), the temperature of boron impurity diffusion is 1200 ~ 1240 DEG C.
In described step (5), the temperature of second segment phosphorus impurities diffusion is 1220 ~ 1260 DEG C.
In described step (5), the diffusion junction depth of U-shaped PN junction is greater than 23 microns.
Low-voltage chip prepared by described production technology, comprises the former silicon chip of P type, and upper surface and the lower surface of the former silicon chip of this P type are all covered with P+ diffusion layer; P+ diffusion layer is connected with phosphorus impurities diffusion layer phase by U-shaped PN junction structure; Phosphorus impurities diffusion layer is positioned at the groove of U-shaped PN junction structure, and the upper surface of phosphorus impurities diffusion layer is covered with alloy-layer; Two of U-shaped PN junction structure uprightly end ends all have and mixes oxychloride layer, be covered with glass passivation layer mixing on oxychloride layer.
Beneficial effect of the present invention is: (1) is diffused with boron impurity on the former silicon chip of P type, makes the former silicon chip of P type increase P+ diffusion layer, P+ diffusion layer adds expansion phosphorus impurities, obtains phosphorus impurities diffusion layer, make P+ diffusion layer and phosphorus impurities diffusion layer form U-shaped PN junction.Diffused with boron impurity on the former silicon chip of P type, the gradient of phosphorus impurities diffusion is restrained by the boron impurity of high concentration, reach the gradual object to abrupt junction transition, such diffusion gradient is steep, improve diffusion gradient, make to spread the CONCENTRATION DISTRIBUTION close to PN junction, and also reduce depletion layer, reach the object reducing electric leakage, fully can reduce electrical leakage.
(2) diffusion of phosphorus impurities adopts the interim diffusion way of two-part, by the decomposition of diffusion impurity, accumulation, the process control that distributes again in line style little as far as possible diffusion, select the districution temperature of phosphorus impurities the best as diffusion temperature, distributing again the required time in conjunction with phosphorus impurities, diffusion junction depth is controlled more than 23 μm, ensure enough electric field width, also ensure that enough spaces reach the object of bonding to the alloy completing metal and silicon, be beneficial to carrying out smoothly of alloy, and avoid product to cross shallow and inefficacy that is that produce because of diffusion junction depth.
(3) when carrying out the cleaning of sodium ion, wafer is put into quartz ampoule be heated to 1200 DEG C and inject chlorine and oxygen, adopt the long-time oxidation technology of high temperature, the sodium ion at the U-shaped PN junction place of absorption pollutes, high temperature chlorine constraint sodium ion, control the mobility of sodium ion at U-shaped PN junction place, be adsorbed on by the sodium ion at U-shaped PN junction place by high temperature the produced silicon dioxide layer of silicon and oxide layer, prevention sodium ion moves caused electric leakage.Electrical leakage can be reduced further.
(4) use the passivation mode of glass protection to be protected by the exposed parts of U-shaped PN junction, improve stability and the reliability of product, eliminate the hidden danger that product may exist.Adopt the mode of glass passivation protection to protect U-shaped PN junction, use the reliability of product and stability to have one significantly to promote.
Technical target of the product is as follows: (1) product voltage bias value is in +/-about 3%; (2) product surveys electrical leakage at 30 below μ A under operating voltage; (3) product can bear the impact of 110% surge of setting; (4) product can complete the target of the reliability test zero failure shown in form 1.
Form 1
| Sequence number | Experimental project | Experiment condition | Experimental quantities | Inefficacy quantity |
| 1 | Can brave property | 5 seconds | 22 | 0 |
| 2 | Lead strain | 10 seconds | 70 | 0 |
| 3 | Lead-in wire antifatigue | 3 times | 35 | 0 |
| 4 | Working life | 1000 hours | 22 | 0 |
| 5 | High temperature reverse bias | 1000 hours | 40 | 0 |
| 6 | The discontinuous operation life-span | 1000 cycles | 22 | 0 |
| 7 | Reverse flow gushes electric current | 10/1000 | All | 0 |
| 8 | High-temperature storage life | 1000 hours | 22 | 0 |
| 9 | Humidity | 100 hours | 22 | 0 |
| 10 | Autoclaving | 4 hours | 22 | 0 |
| 11 | Thermal shock | 10 cycles | 22 | 0 |
| 12 | Temperature cycles | 10 cycles | 22 | 0 |
| 13 | Resistance to soldering heat | 10 seconds | 125 | 0 |
Accompanying drawing explanation
Fig. 1 is the structural representation of specific embodiment of the invention midplane low-voltage chip.
Wherein, 1 is the former silicon chip of P type, and 2 is P+ diffusion layer, and 3 is phosphorus impurities diffusion layer, and 4 is alloy-layer, and 5 is U-shaped PN junction structure, and 6 for mixing oxychloride layer, and 7 is glass passivation layer.
Embodiment
Describe the present invention below by specific embodiment.
Embodiment 1
A production technology for low-voltage chip, comprises the following steps:
(1) choose the former silicon chip of P type: select resistivity to be 0.002 ohm/cm, thickness is the former silicon chip of P type of 290 microns;
(2) preliminary treatment before boron impurity diffusion: first the former silicon chip of P type selected by step (1) is carried out chemical corrosion 30 seconds under 1 ~ 3 DEG C of temperature conditions in the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in No. I liquid by hydrogen peroxide, ammoniacal liquor and water proportioning after being rinsed well in pure water by former for P type silicon chip, make the former silicon chip of P type at 80 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Rinse well with water after cleaning in No. I liquid, former for P type silicon chip is placed in by No. II liquid heat temperature raising of hydrogen peroxide, hydrochloric acid and water proportioning again, make the former silicon chip of P type at 80 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: hydrochloric acid: water is 1:1:6; Finally bath cleans up and dries;
(3) boron impurity diffusion: be positioned in stove by the former silicon chip of pretreated P type, heat temperature raising, carries out the diffusion of boron impurity under 1200 DEG C of conditions, is then cooled to 500 DEG C and comes out of the stove, and the upper and lower surface of the former silicon chip of P type is formed P+ diffusion layer;
(4) brilliant point/clean: the former silicon chip of P type step (3) being completed boron impurity diffusion is positioned in hydrofluoric acid and soaks separately, then be positioned over pure water interior bath cleaning 1 hour, described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: enter stove under 200 DEG C of conditions, be heated to 900 DEG C and carry out the diffusion of first paragraph phosphorus impurities; Carry out the diffusion of second segment phosphorus impurities under being heated to 1200 DEG C of conditions again, complete the diffusion of whole phosphorus impurities, form phosphorus impurities diffusion layer, be finally cooled to 500 DEG C and come out of the stove, between P+ diffusion layer and phosphorus impurities diffusion layer, form U-shaped PN junction;
(6) brilliant point/cleaning: the former silicon chip of P type step (5) being completed phosphorus impurities diffusion is positioned in hydrofluoric acid and soaks separately, then cleaning 1 hour of washing by water in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblasting; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) cleaning before passivation: after first the wafer of completing steps (7) being cleaned a minute with the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then to wash by water cleaning after 10 minutes, then put into by the solution of hydrofluoric acid and water proportioning except oxide layer, wherein hydrofluoric acid by volume: water is 1:1; Last at 80 DEG C heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule and is heated to 1200 DEG C and injects chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped PN junction place sodium ion, scavenging period is 30 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product makes: cleaning before nickel plating; Nickel plating/alloy; Scribing; Test; Packaging.
In described step (5), the diffusion junction depth of U-shaped PN junction is greater than 23 microns.
Low-voltage chip prepared by described production technology, comprises the former silicon chip 1 of P type, and upper surface and the lower surface of the former silicon chip 1 of this P type are all covered with P+ diffusion layer 2; P+ diffusion layer 2 is connected with phosphorus impurities diffusion layer 3 by U-shaped PN junction structure 5; Phosphorus impurities diffusion layer 3 is positioned at the groove of U-shaped PN junction structure 5, and the upper surface of phosphorus impurities diffusion layer 3 is covered with alloy-layer 4; Two of U-shaped PN junction structure 5 uprightly end ends all have and mixes oxychloride layer 6, be covered with glass passivation layer 7 mixing on oxychloride layer 6.
Embodiment 2
A production technology for low-voltage chip, comprises the following steps:
(1) choose the former silicon chip of P type: select resistivity to be 0.0037 ohm/cm, thickness is the former silicon chip of P type of 340 microns;
(2) preliminary treatment before boron impurity diffusion: first the former silicon chip of P type selected by step (1) is carried out chemical corrosion 30 seconds under 1 ~ 3 DEG C of temperature conditions in the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in No. I liquid by hydrogen peroxide, ammoniacal liquor and water proportioning after being rinsed well in pure water by former for P type silicon chip, make the former silicon chip of P type at 95 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Rinse well with water after cleaning in No. I liquid, former for P type silicon chip is placed in by No. II liquid heat temperature raising of hydrogen peroxide, hydrochloric acid and water proportioning again, make the former silicon chip of P type at 95 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: hydrochloric acid: water is 1:1:6; Finally bath cleans up and dries;
(3) boron impurity diffusion: be positioned in stove by the former silicon chip of pretreated P type, heat temperature raising, carries out the diffusion of boron impurity under 1300 DEG C of conditions, is then cooled to 600 DEG C and comes out of the stove, and the upper and lower surface of the former silicon chip of P type is formed P+ diffusion layer;
(4) brilliant point/clean: the former silicon chip of P type step (3) being completed boron impurity diffusion is positioned in hydrofluoric acid and soaks separately, then be positioned over pure water interior bath cleaning 1 hour, described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: enter stove under 400 DEG C of conditions, be heated to 900 DEG C and carry out the diffusion of first paragraph phosphorus impurities; Carry out the diffusion of second segment phosphorus impurities under being heated to 1300 DEG C of conditions again, complete the diffusion of whole phosphorus impurities, form phosphorus impurities diffusion layer, be finally cooled to 600 DEG C and come out of the stove, between P+ diffusion layer and phosphorus impurities diffusion layer, form U-shaped PN junction;
(6) brilliant point/cleaning: the former silicon chip of P type step (5) being completed phosphorus impurities diffusion is positioned in hydrofluoric acid and soaks separately, then cleaning 1 hour of washing by water in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblasting; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) cleaning before passivation: after first the wafer of completing steps (7) being cleaned a minute with the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then to wash by water cleaning after 10 minutes, then put into by the solution of hydrofluoric acid and water proportioning except oxide layer, wherein hydrofluoric acid by volume: water is 1:1; Last at 95 DEG C heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule and is heated to 1200 DEG C and injects chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped PN junction place sodium ion, scavenging period is 60 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product makes: cleaning before nickel plating; Nickel plating/alloy; Scribing; Test; Packaging.
In described step (5), the diffusion junction depth of U-shaped PN junction is greater than 23 microns.
Low-voltage chip prepared by described production technology, comprises the former silicon chip 1 of P type, and upper surface and the lower surface of the former silicon chip 1 of this P type are all covered with P+ diffusion layer 2; P+ diffusion layer 2 is connected with phosphorus impurities diffusion layer 3 by U-shaped PN junction structure 5; Phosphorus impurities diffusion layer 3 is positioned at the groove of U-shaped PN junction structure 5, and the upper surface of phosphorus impurities diffusion layer 3 is covered with alloy-layer 4; Two of U-shaped PN junction structure 5 uprightly end ends all have and mixes oxychloride layer 6, be covered with glass passivation layer 7 mixing on oxychloride layer 6.
Embodiment 3
A production technology for low-voltage chip, comprises the following steps:
(1) choose the former silicon chip of P type: select resistivity to be 0.0035 ohm/cm, thickness is the former silicon chip of P type of 310 microns;
(2) preliminary treatment before boron impurity diffusion: first the former silicon chip of P type selected by step (1) is carried out chemical corrosion 30 seconds under 1 ~ 3 DEG C of temperature conditions in the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in No. I liquid by hydrogen peroxide, ammoniacal liquor and water proportioning after being rinsed well in pure water by former for P type silicon chip, make the former silicon chip of P type at 90 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Rinse well with water after cleaning in No. I liquid, former for P type silicon chip is placed in by No. II liquid heat temperature raising of hydrogen peroxide, hydrochloric acid and water proportioning again, make the former silicon chip of P type at 90 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: hydrochloric acid: water is 1:1:6; Finally bath cleans up and dries;
(3) boron impurity diffusion: be positioned in stove by the former silicon chip of pretreated P type, heat temperature raising, carries out the diffusion of boron impurity under 1240 DEG C of conditions, is then cooled to 550 DEG C and comes out of the stove, and the upper and lower surface of the former silicon chip of P type is formed P+ diffusion layer;
(4) brilliant point/clean: the former silicon chip of P type step (3) being completed boron impurity diffusion is positioned in hydrofluoric acid and soaks separately, then be positioned over pure water interior bath cleaning 1 hour, described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: enter stove under 300 DEG C of conditions, be heated to 900 DEG C and carry out the diffusion of first paragraph phosphorus impurities; Carry out the diffusion of second segment phosphorus impurities under being heated to 1220 DEG C of conditions again, complete the diffusion of whole phosphorus impurities, form phosphorus impurities diffusion layer, be finally cooled to 550 DEG C and come out of the stove, between P+ diffusion layer and phosphorus impurities diffusion layer, form U-shaped PN junction;
(6) brilliant point/cleaning: the former silicon chip of P type step (5) being completed phosphorus impurities diffusion is positioned in hydrofluoric acid and soaks separately, then cleaning 1 hour of washing by water in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblasting; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) cleaning before passivation: after first the wafer of completing steps (7) being cleaned a minute with the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then to wash by water cleaning after 10 minutes, then put into by the solution of hydrofluoric acid and water proportioning except oxide layer, wherein hydrofluoric acid by volume: water is 1:1; Last at 90 DEG C heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule and is heated to 1200 DEG C and injects chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped PN junction place sodium ion, scavenging period is 50 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product makes: cleaning before nickel plating; Nickel plating/alloy; Scribing; Test; Packaging.
In described step (5), the diffusion junction depth of U-shaped PN junction is greater than 23 microns.
Low-voltage chip prepared by described production technology, comprises the former silicon chip 1 of P type, and upper surface and the lower surface of the former silicon chip 1 of this P type are all covered with P+ diffusion layer 2; P+ diffusion layer 2 is connected with phosphorus impurities diffusion layer 3 by U-shaped PN junction structure 5; Phosphorus impurities diffusion layer 3 is positioned at the groove of U-shaped PN junction structure 5, and the upper surface of phosphorus impurities diffusion layer 3 is covered with alloy-layer 4; Two of U-shaped PN junction structure 5 uprightly end ends all have and mixes oxychloride layer 6, be covered with glass passivation layer 7 mixing on oxychloride layer 6.
Embodiment 4
A production technology for low-voltage chip, comprises the following steps:
(1) choose the former silicon chip of P type: select resistivity to be 0.0025 ohm/cm, thickness is the former silicon chip of P type of 320 microns;
(2) preliminary treatment before boron impurity diffusion: first the former silicon chip of P type selected by step (1) is carried out chemical corrosion 30 seconds under 1 ~ 3 DEG C of temperature conditions in the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in No. I liquid by hydrogen peroxide, ammoniacal liquor and water proportioning after being rinsed well in pure water by former for P type silicon chip, make the former silicon chip of P type at 85 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Rinse well with water after cleaning in No. I liquid, former for P type silicon chip is placed in by No. II liquid heat temperature raising of hydrogen peroxide, hydrochloric acid and water proportioning again, make the former silicon chip of P type at 85 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: hydrochloric acid: water is 1:1:6; Finally bath cleans up and dries;
(3) boron impurity diffusion: be positioned in stove by the former silicon chip of pretreated P type, heat temperature raising, carries out the diffusion of boron impurity under 1230 DEG C of conditions, is then cooled to 570 DEG C and comes out of the stove, and the upper and lower surface of the former silicon chip of P type is formed P+ diffusion layer;
(4) brilliant point/clean: the former silicon chip of P type step (3) being completed boron impurity diffusion is positioned in hydrofluoric acid and soaks separately, then be positioned over pure water interior bath cleaning 1 hour, described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: enter stove under 350 DEG C of conditions, be heated to 900 DEG C and carry out the diffusion of first paragraph phosphorus impurities; Carry out the diffusion of second segment phosphorus impurities under being heated to 1260 DEG C of conditions again, complete the diffusion of whole phosphorus impurities, form phosphorus impurities diffusion layer, be finally cooled to 570 DEG C and come out of the stove, between P+ diffusion layer and phosphorus impurities diffusion layer, form U-shaped PN junction;
(6) brilliant point/cleaning: the former silicon chip of P type step (5) being completed phosphorus impurities diffusion is positioned in hydrofluoric acid and soaks separately, then cleaning 1 hour of washing by water in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblasting; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) cleaning before passivation: after first the wafer of completing steps (7) being cleaned a minute with the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then to wash by water cleaning after 10 minutes, then put into by the solution of hydrofluoric acid and water proportioning except oxide layer, wherein hydrofluoric acid by volume: water is 1:1; Last at 85 DEG C heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule and is heated to 1200 DEG C and injects chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped PN junction place sodium ion, scavenging period is 55 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product makes: cleaning before nickel plating; Nickel plating/alloy; Scribing; Test; Packaging.
In described step (5), the diffusion junction depth of U-shaped PN junction is greater than 23 microns.
Low-voltage chip prepared by described production technology, comprises the former silicon chip 1 of P type, and upper surface and the lower surface of the former silicon chip 1 of this P type are all covered with P+ diffusion layer 2; P+ diffusion layer 2 is connected with phosphorus impurities diffusion layer 3 by U-shaped PN junction structure 5; Phosphorus impurities diffusion layer 3 is positioned at the groove of U-shaped PN junction structure 5, and the upper surface of phosphorus impurities diffusion layer 3 is covered with alloy-layer 4; Two of U-shaped PN junction structure 5 uprightly end ends all have and mixes oxychloride layer 6, be covered with glass passivation layer 7 mixing on oxychloride layer 6.
Claims (5)
1. a production technology for low-voltage chip, comprises the following steps:
(1) choose the former silicon chip of P type: select resistivity to be 0.002 ~ 0.0037 ohm/cm, thickness is the former silicon chip of P type of 290 ~ 340 microns;
(2) preliminary treatment before boron impurity diffusion: first the former silicon chip of P type selected by step (1) is carried out chemical corrosion 30 seconds under 1 ~ 3 DEG C of temperature conditions in the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then be positioned over heat temperature raising in No. I liquid by hydrogen peroxide, ammoniacal liquor and water proportioning after being rinsed well in pure water by former for P type silicon chip, make the former silicon chip of P type at 80 ~ 95 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: ammoniacal liquor: water is 1:1:6; Rinse well with water after cleaning in No. I liquid, former for P type silicon chip is placed in by No. II liquid heat temperature raising of hydrogen peroxide, hydrochloric acid and water proportioning again, make the former silicon chip of P type at 80 ~ 95 DEG C, carry out cleaning 10 minutes, wherein hydrogen peroxide by volume: hydrochloric acid: water is 1:1:6; Finally bath cleans up and dries;
(3) boron impurity diffusion: be positioned in stove by the former silicon chip of pretreated P type, heat temperature raising, carries out the diffusion of boron impurity under 1200 ~ 1300 DEG C of conditions, is then cooled to 500 ~ 600 DEG C and comes out of the stove, and the upper and lower surface of the former silicon chip of P type is formed P+ diffusion layer;
(4) brilliant point/clean: the former silicon chip of P type step (3) being completed boron impurity diffusion is positioned in hydrofluoric acid and soaks separately, then be positioned over pure water interior bath cleaning 1 hour, described hydrofluoric acid is electron level;
(5) phosphorus impurities diffusion: enter stove under 200 ~ 400 DEG C of conditions, be heated to 900 DEG C and carry out the diffusion of first paragraph phosphorus impurities; Carry out the diffusion of second segment phosphorus impurities under being heated to 1200 ~ 1300 DEG C of conditions again, complete the diffusion of whole phosphorus impurities, form phosphorus impurities diffusion layer, be finally cooled to 500 ~ 600 DEG C and come out of the stove, between P+ diffusion layer and phosphorus impurities diffusion layer, form U-shaped PN junction;
(6) brilliant point/cleaning: the former silicon chip of P type step (5) being completed phosphorus impurities diffusion is positioned in hydrofluoric acid and soaks separately, then cleaning 1 hour of washing by water in pure water; Described hydrofluoric acid is electron level;
(7) table top processing: sandblasting; Shakeout cleans; Oxidizing annealing; A moment; Mesa etch;
(8) cleaning before passivation: after first the wafer of completing steps (7) being cleaned a minute with the mixed acid by nitric acid, hydrofluoric acid and glacial acetic acid proportioning, wherein nitric acid by volume: hydrofluoric acid: glacial acetic acid is 18:1:1; Then to wash by water cleaning after 10 minutes, then put into by the solution of hydrofluoric acid and water proportioning except oxide layer, wherein hydrofluoric acid by volume: water is 1:1; Last at 80 ~ 95 DEG C heated wash 10 minutes;
(9) cleaning of sodium ion: the wafer of completing steps (8) is put into quartz ampoule and is heated to 1200 DEG C and injects chlorine and oxygen, wherein chlorine by volume: oxygen is 1:4; Carry out the cleaning of U-shaped PN junction place sodium ion, scavenging period is 30 ~ 60 minutes;
(10) glassivation: glass protection; Two quarters; Glass corrosion;
(11) finished product makes: cleaning before nickel plating; Nickel plating/alloy; Scribing; Test; Packaging.
2. the production technology of low-voltage chip according to claim 1, is characterized in that, in described step (3), the temperature of boron impurity diffusion is 1200 ~ 1240 DEG C.
3. the production technology of low-voltage chip according to claim 1, is characterized in that, in described step (5), the temperature of second segment phosphorus impurities diffusion is 1220 ~ 1260 DEG C.
4. the production technology of low-voltage chip according to claim 1, is characterized in that, in described step (5), the diffusion junction depth of U-shaped PN junction is greater than 23 microns.
5. the low-voltage chip prepared of production technology according to claim 1, it is characterized in that, comprise the former silicon chip of P type, upper surface and the lower surface of the former silicon chip of this P type are all covered with P+ diffusion layer; P+ diffusion layer is connected with phosphorus impurities diffusion layer phase by U-shaped PN junction structure; Phosphorus impurities diffusion layer is positioned at the groove of U-shaped PN junction structure, and the upper surface of phosphorus impurities diffusion layer is covered with alloy-layer; Two of U-shaped PN junction structure uprightly end ends all have and mixes oxychloride layer, be covered with glass passivation layer mixing on oxychloride layer.
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| US10431447B2 (en) * | 2014-09-30 | 2019-10-01 | Hemlock Semiconductor Corporation | Polysilicon chip reclamation assembly and method of reclaiming polysilicon chips from a polysilicon cleaning apparatus |
| CN111009457A (en) * | 2019-11-19 | 2020-04-14 | 江苏英锐半导体有限公司 | Diffusion pretreatment method |
| CN113156294B (en) * | 2021-03-23 | 2024-05-24 | 英特尔产品（成都）有限公司 | Thermal control method and device for chip burn-in test |
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