CN205508830U - High HTRB's fast recovery diode chip of high pressure - Google Patents
High HTRB's fast recovery diode chip of high pressure Download PDFInfo
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Abstract
The utility model discloses a high HTRB's fast recovery diode chip of high pressure belongs to the semiconductor chip field. A high HTRB's fast recovery diode chip of high pressure, includes chip, N+ cut -off ring, terminal structure and P+ positive pole, the chip be fast recovery diode chip, a chip section layer is followed a dextrad left side and is chip, N+ cut -off ring, terminal structure and P+ positive pole in proper order. Adopt a biasing metal field plate field limit ring sum composite terminal structure of limit ring of floating, is keeping away from the regional biasing metal field plate field limit ring that adopts of P+ positive pole, the short circuit chip surface electric charge, solved high -pressure fast recovery diode withstand voltage decay inefficacy problem in HTRB is ageing, being close to the regional limit ring that floats that adopts of P+ positive pole, avoid introducing the polycrystal field plate to the chip manufacture cost has been saved. It has high HTRB reliability, the low cost, and breakdown voltage is high, and the leakage current is little, and advantage that switching loss is low has prolonged life -span of diode.
Description
Technical field
This utility model relates to semiconductor chip field, more particularly, it relates to the high-voltage fast recovery chip of a kind of high HTRB.
Background technology
List of references: encapsulate, detect and equipment, the impact on HTRB working life of maximum reverse current IR of commutation diode, in JIUYUE, 2011 the 9th phase of volume 36, Bao Ailin, Fu Jianfeng, Deng Aimin.Rectifying device reliability at work often has substantial connection with its leakage current leakage current the most at high temperature, by the contrast test to room temperature Yu high-temperature current leakage, finding that high-temperature current leakage is the biggest, the high temperature reverse bias life-span is the shortest, illustrates that the high temperature reverse bias life-span is had a major impact by high-temperature current leakage.Generally rectifying device can work under the junction temperature of 3～4 times of room temperatures, leakage current under higher junction temperature just seems abnormal important, because compared with forward current, although it is the least but will not compare as forward current and be evenly distributed in whole tying, its major part is distributed in surface leakage raceway groove and passes in the internal electrical losses raceway groove tied.The area of raceway groove is the least, and therefore its electric current density exception is big, often results in the thermal runaway at this, can cause material molten time serious.Actually account for, because of the microcell overheating failure that junction temperature is too high, leakage current concentration of local causes, the overwhelming majority that rectifying device lost efficacy.High-temperature current leakage is significant on the impact in HTRB life-span, and its essence is that the increase of maximum reverse current IR accelerates the inefficacy under the device driven by junction temperature.
List of references: quasiconductor journal, improves the simulation study of power fast recovery diode performance by Localized Lifetime Control technology, the 5th phase of volume 24 in 2003, the 520-526 page, Wu He, Wu Yu, high precious position, Jia Yunpeng.Document describes as device for power switching, the most important performance parameter of high-voltage fast recovery (FRD) is reverse recovery time, in order to reduce reverse recovery time, parameter for the low lifetime region of local has carried out the simulation study of system to the fast impact recovering silicon power diode performance, obtain comprehensive and systematic result of study including complex centre energy level position in the forbidden band different reverse recovery time to fast recovery diode in the different lifetime region low with local in the low lifetime region of local position in the diode, the Reverse recovery softness factor, forward voltage drop, the leakage current impact on each individual event performance, and the impact that every combination property is comprehensively traded off.These results have important reference value to high-speed power engineering research device lifetime and device manufacturing engineering.
Produce high-voltage fast recovery (FRD) chip at present in semicon industry and generally use V-groove glassivation production technology.But there is various problems in prior art, main problem is as follows: 1), breakdown potential force down, leakage current is big.2), HTRB poor reliability, power consumption is relatively big, and diode easily burns.
Summary of the invention
1. to solve the technical problem that
For HTRB poor reliability present in prior art, breakdown potential is forced down, and leakage current is big, forward conduction voltage is relatively big, and power consumption is relatively big, and manufacturing cost is high, the easy burnout problems of diode chip for backlight unit, this utility model provides the high-voltage fast recovery chip of a kind of high HTRB, and it is high that it has HTRB reliability, low cost, easily fabricated, switching loss is low, and breakdown reverse voltage is high, extends the life-span of diode.
2. technical scheme
The purpose of this utility model is achieved through the following technical solutions.
The high-voltage fast recovery chip of a kind of high HTRB reliability low cost, including chip, also includes N+ cut-off ring, composite terminal structure and P+ anode, and described chip is fast recovery diode chip；Chip cuts layer and is followed successively by chip, N+ cut-off ring, composite terminal structure and P+ anode from right to left, described composite terminal structure is offset wire field plate field limiting ring and floating field limiting ring, described floating field limiting ring ends ring side near P+ anode side, offset wire field plate field limiting ring near N+.
Further, described offset wire field plate field limiting ring area amasss more than floating field limit anchor ring.
A kind of high-voltage fast recovery chip production process of above-mentioned high HTRB, its step is as follows:
1) oxidation front surface in field cleans:
Configuration hydrofluoric acid solution, by volume ratio water: Fluohydric acid .=6:1 solution is mixed to get, described hydrofluoric acid solution mass concentration is 40%；
Configuring No. 1 liquid, volume ratio be ammonia: hydrogenperoxide steam generator: water=1:1:5-1:2:7 is mixed to get, described ammonia concn mass concentration is 27%；
Configuring No. 2 liquid, by volume ratio hydrogen chloride: hydrogenperoxide steam generator: water=1:1:6-1:2:8 is mixed to get, described hydrogen chloride mass concentration is 37%, hydrogenperoxide steam generator mass concentration is 30%；Cleaning sequence is as follows:
A. use hydrofluoric acid solution to soak silicon chip 30s, use deionized water rinsing；
B. with No. 1 immersion bubble silicon chip 10min, deionized water rinsing is used；
C. the silicon chip 30s after using described hydrofluoric acid solution soaking step b to process, after use deionized water rinsing；
D. with No. 2 immersion bubble silicon chip 10min, afterwards with deionized water rinsing, use described hydrofluoric acid solution to soak 1min, finally with deionized water rinsing, complete silicon chip surface to clean；
2) growth of silicon chip surface field oxide: by step 1) silicon chip that processed is placed in oxidation furnace growth, generates one layer of field oxide, field oxide thickness 1-2um, and oxidation furnace temperature is 1000-1100 DEG C；
3) P+ boron diffusion photoetching: to step 2) silicon chip that processed carries out photoetching, is formed at the P+ anode of P+ anode region, composite terminal structural region formation offset wire field plate field limiting ring and floating field limiting ring；
4) wet etching corrosion field oxide: to step 3) silicon chip that processed carries out wet etching corrosion, removal step 2 in P+ boron spreads the region of photoetching) field oxide that deposits；Remove the photoresist of P+ boron diffusion photoetching；
5) ion implanting protection oxidation front surface clean: use step 1) same procedure previous step has been processed after silicon chip surface be carried out；
6) growth of ion implanting protection oxide layer: by step 5) silicon chip that processed is placed in oxidation furnace growth, and oxide layer is protected in the patterned area growth one layer in the diffusion of P+ boron, and oxidation furnace temperature is 900-1000 DEG C；
7) P+ boron ion implanting: by step 6) silicon chip that processed carries out boron ion bom bardment, boron Implanted Silicon Wafer surface under 40KeV-80KeV energy, and form PN junction, and complete offset wire field plate field limiting ring and the injection of floating field limiting ring；
8) wet etching corrosive ions injects protection oxide layer: by step 7) silicon chip that processed, the ammonium fluoride using volume ratio to be 6:1 and the oxide layer of hydrofluoric acid solution removal P+ boron diffused region；
9) ion propulsion front surface cleans: use step 1) same procedure previous step processed silicon chip carried out surface clean；
10) ion propulsion: by step 9) silicon chip that processed is placed in diffusion furnace, is diffused, and the junction depth of PN junction increases, and completes, to offset wire field plate field limiting ring and the diffusion of floating field limiting ring, to activate the boron ion injected；Diffusion furnace temperature is 1100-1200 DEG C；
11) N+ ends ring photoetching: to step 10) silicon chip that processed carries out photoetching, forms the N+ cut-off ring of the high-voltage fast recovery of high HTRB reliability low cost in silicon chip；
12) wet etching corrosion thermal oxide layer: by step 11) silicon chip that processed, the ammonium fluoride using volume ratio to be 6:1 and hydrofluoric acid solution remove the thermal oxide layer that N+ cut-off ring (2) patterned area deposits；
13) N+ ends ring ion implanting: by step 12) silicon chip that processed, use 40KeV-80KeV energy to carry out phosphonium ion injection at N+ cut-off ring (2), remove N+ with stripper at normal temperatures and end the photoresist of ring surface；
14) front metal contact window photoetching: to step 14) silicon chip that processed carries out photoetching, forms the region of metal contact window in the region of P+ anode and composite terminal structure；
15) wet etching corrosion thermal oxide layer: by step 15) silicon chip that processed, use wet etching corrosion, the ammonium fluoride and the hydrofluoric acid solution that use volume ratio to be 6:1 in the region of front metal contact window photoetching remove the thermal oxide layer deposited；The photoresist of front metal contact window photoetching is removed at normal temperatures with stripper；
16) evaporation front metal: by step 16) silicon chip that processed, silicon chip is carried out electron beam evaporation, deposit isolating metal and front metal on silicon chip；
17) front metal photoetching: to step 17) silicon chip that processed carries out photoetching, and the front metal in front metal region is in P+ anode and composite terminal structure；
18) wet etching front metal: by step 18) silicon chip that processed, the phosphoric acid solution using volume ratio to be 85% at normal temperatures removes the front metal outside P+ anode region and composite terminal structure, the photoresist of coating when using stripper to remove front metal photoetching at normal temperatures；
19) front metal alloy: by step 19) silicon chip that processed inserts in alloy furnace tubes by adopting, and front metal part forms front metal alloy, and alloy furnace tubes by adopting temperature is 400-500 DEG C, and the alloy time is 20min；
20) thinning back side: to step 20) process the silicon chip obtained, by silicon wafer thickness from thinning back side to 200-300um；
21) back metal deposit: for step 21) process the silicon chip obtained, carry out direct current plasma sputtering deposit back metal at silicon chip back side, form backplate；
22) electron beam irradiation: to step 22) process the silicon chip obtained, with the electron beam irradiation of 200kGy-800kGy dosage, silicon chip introduces defect；
23) chip cutting: by step 23) silicon chip that produces, use scribing machine that silicon chip is divided into one single chip, form individual chips.
Further, step 8), 12) and 15) in, described ammonium fluoride and hydrofluoric acid solution, ammonium fluoride mass concentration is 40%, and Fluohydric acid. mass concentration is 40%.
Further, step 16) described in isolating metal and front metal be titanium and aluminum.
Further, step 20) described in thinning method for backing side be grinding, chemically mechanical polishing, wet etching, atmospheric plasma corrosion.
Further, step 21) described in back metal be silver.
3. beneficial effect
Compared to prior art, the utility model has the advantage of:
(1) chip structure is simple, turns left from the right side and is divided into four-layer structure, it is easy to manufacturing, adaptability is good, compatible high；
(2) offset wire field plate field limiting ring and the composite terminal structure of floating field limiting ring are used, offset wire field plate field limiting ring is being used away from P+ anode region, short circuit chip surface electric charge, solve high-voltage fast recovery pressure decay Problem of Failure in HTRB is aging, improve the HTRB reliability of fast recovery diode；Floating field limit ring region territory the widest general area, within 100 microns.And offset wire field plate field limiting ring region, area is the widest, typically between 100-200 micron.
(3) use offset wire field plate field limiting ring and the composite terminal structure of floating field limiting ring, using floating field limiting ring near P+ anode region, it is to avoid introduce polycrystalline field plate, if introducing polycrystalline field plate, can increase by 2 layer photoetchings, considerably increasing chip manufacturing cost.This programme saves chip manufacturing cost, uses the composite terminal structure of above-mentioned offset wire field plate field limiting ring and floating field limiting ring without using special surface passivation layer simultaneously, improves the manufacturability of product.
(4) use novel diode chip for backlight unit production technology, reduce switching loss, reduce pressure drop, reduce chip power-consumption, enhance pressure stability and the reliability of diode, extend the life-span of diode；
(5) use front metal alloy and the method for thinning back side, reduce the forward conduction resistance of diode, improve the conduction property of diode, improve the reliability of diode；
(6) back metal grown uses silver so that diode chip for backlight unit has more preferable electric conductivity, and highly reliable, energy consumption is low.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of the high-voltage fast recovery chip of high HTRB reliability low cost；
Fig. 2 is the schematic cross-section of the high-voltage fast recovery chip of high HTRB reliability low cost；
Fig. 3 is the preparation technology flow chart of the high-voltage fast recovery chip of high HTRB reliability low cost.
Label declaration in figure:
1, chip；2, N+ ends ring；3, composite terminal structure；31, floating field limiting ring；32, offset wire field plate field limiting ring；4, P+ anode.
Detailed description of the invention
Below in conjunction with Figure of description and specific embodiment, this utility model is described in detail.
Embodiment 1
As shown in Figure 1 and Figure 2, the high-voltage fast recovery chip of a kind of high HTRB, end ring 2, composite terminal structure 3 and P+ anode 4 including chip 1, N+, described chip 1 is fast recovery diode chip；Composite terminal structure 3 comprises the offset wire field plate field limiting ring 32 away from P+ anode region and floating field limiting ring 31 structure near P+ anode region, short circuit chip surface electric charge, solve high-voltage fast recovery pressure decay Problem of Failure in HTRB is aging, improve the HTRB of fast recovery diode, save chip manufacturing cost, improve the manufacturability reliability of product.Floating field limiting ring 31 region is mainly avoided introducing polycrystalline field plate, so the widest general area, within 100 microns.The present embodiment uses 90 microns.And offset wire field plate field limiting ring 32 region is the effect in order to play dividing potential drop, area is also the widest, typically between 100-200 micron.The present embodiment uses 150 microns.Chip cuts that layer is followed successively by chip 1 from bottom to top, N+ ends ring 2, composite terminal structure 3 and P+ anode 4, and chip is turned left from the right side and is divided into four-layer structure, it is easy to manufacturing, adaptability is good, compatible high.
Chip parameter:
Breakdown voltage VBR >=800V；
Forward voltage VF (IF=15A)≤1.5V；
Reverse leakage current IR≤1 μ A；
Reverse recovery time Trr≤50nS；
By 150 DEG C, HTRB reliability testing under 800V.
The product made for structural approach, name of product U200800AA, electrical property is as follows: VBR (25 DEG C, IR=100uA)=960V, VF (25 DEG C, IF=15A)=1.1V, IR (25 DEG C, VR=600V)=0.5uA.
The HTRB reliability of chip is high, low cost, it is easy to manufacturing, switching loss is low, and breakdown reverse voltage is high, extends the life-span of diode.
As it is shown on figure 3, the high-voltage fast recovery chip production process of a kind of high HTRB, its step is as follows:
1) oxidation front surface in field cleans:
Configuration hydrofluoric acid solution, by volume ratio water: Fluohydric acid .=6:1 solution is mixed to get, described hydrofluoric acid solution mass concentration is 40%；
Configuring No. 1 liquid, volume ratio be ammonia: hydrogenperoxide steam generator: water=1:1:5-1:2:7 is mixed to get, described ammonia concn mass concentration is 27%；
Configuring No. 2 liquid, by volume ratio hydrogen chloride: hydrogenperoxide steam generator: water=1:1:6-1:2:8 is mixed to get, described hydrogen chloride mass concentration is 37%, hydrogenperoxide steam generator mass concentration is 30%；Cleaning sequence is as follows:
A. use hydrofluoric acid solution to soak silicon chip 30s, use deionized water rinsing；
B. with No. 1 immersion bubble silicon chip 10min, deionized water rinsing is used；
C. the silicon chip 30s after using described hydrofluoric acid solution soaking step b to process, after use deionized water rinsing；
D. with No. 2 immersion bubble silicon chip 10min, afterwards with deionized water rinsing, use described hydrofluoric acid solution to soak 1min, finally with deionized water rinsing, complete silicon chip surface to clean；
2) growth of silicon chip surface field oxide: by step 1) silicon chip that processed is placed in oxidation furnace growth, generates one layer of field oxide, field oxide thickness 1um, and oxidation furnace temperature is 1000 DEG C；
3) P+ boron diffusion photoetching: to step 2) silicon chip that processed carries out photoetching, forms P+ anode 4 in P+ anode 4 region, and composite terminal structure 3 region of offset wire field plate field limiting ring 32 and floating field limiting ring 31 forms electric field limiting ring；4) wet etching corrosion field oxide: to step 3) silicon chip that processed carries out wet etching corrosion, removal step 2 in P+ boron spreads the region of photoetching) field oxide that deposits；Remove the photoresist of P+ boron diffusion photoetching；
5) ion implanting protection oxidation front surface clean: use step 1) same procedure previous step has been processed after silicon chip surface be carried out；
6) growth of ion implanting protection oxide layer: by step 5) silicon chip that processed is placed in oxidation furnace growth, and oxide layer is protected in the patterned area growth one layer in the diffusion of P+ boron, and oxidation furnace temperature is 900 DEG C；
7) P+ boron ion implanting: by step 6) silicon chip that processed carries out boron ion bom bardment, boron Implanted Silicon Wafer surface under 40KeV energy, and form PN junction, complete offset wire field plate field limiting ring 32 and the injection of floating field limiting ring 31；
8) wet etching corrosive ions injects protection oxide layer: by step 7) silicon chip that processed; the ammonium fluoride using volume ratio to be 6:1 and hydrofluoric acid solution remove the oxide layer of P+ boron diffused region; wherein said ammonium fluoride and hydrofluoric acid solution; ammonium fluoride mass concentration is 40%, and Fluohydric acid. mass concentration is 40%；
9) ion propulsion front surface cleans: use step 1) same procedure previous step processed silicon chip carried out surface clean；
10) ion propulsion: by step 9) silicon chip that processed is placed in diffusion furnace, is diffused, and the junction depth of PN junction increases, and completes, to offset wire field plate field limiting ring 32 and the diffusion of floating field limiting ring 31, to activate the boron ion of injection simultaneously；Diffusion furnace temperature is 1100 DEG C；
11) N+ ends ring photoetching: to step 10) silicon chip that processed carries out photoetching, forms the N+ cut-off ring 2 of the high-voltage fast recovery of high HTRB reliability low cost in silicon chip；
12) wet etching corrosion thermal oxide layer: by step 11) silicon chip that processed, the ammonium fluoride using volume ratio to be 6:1 and hydrofluoric acid solution remove the thermal oxide layer of N+ cut-off ring 2 patterned area deposit, ammonium fluoride mass concentration is 40%, and Fluohydric acid. mass concentration is 40%；
13) N+ ends ring ion implanting: by step 12) silicon chip that processed, use 40KeV energy to carry out phosphonium ion injection at N+ cut-off ring 2, remove N+ with stripper at normal temperatures and end the photoresist on ring 2 surface；
14) deposit PETEOS oxide layer: depositing PETEOS oxide layer in the plasma chamber of 400 DEG C, the thickness of this oxide layer is step 19 by contrived experiment) the offset wire field plate that the formed optimized Electric Field Distribution of offer；
15) front metal contact window photoetching: to step 14) silicon chip that processed carries out photoetching, forms the region of metal contact window in the region of P+ anode 4 and the composite terminal structure 3 of offset wire field plate field limiting ring 32 and floating field limiting ring 31；
16) wet etching corrosion thermal oxide layer: by step 15) silicon chip that processed, use wet etching corrosion, the ammonium fluoride and the hydrofluoric acid solution that use volume ratio to be 6:1 in the region of front metal contact window photoetching remove the thermal oxide layer deposited；Remove the photoresist of front metal contact window photoetching at normal temperatures with stripper, ammonium fluoride mass concentration is 40%, and Fluohydric acid. mass concentration is 40%；
17) evaporation front metal: by step 16) silicon chip that processed, silicon chip is carried out electron beam evaporation, on silicon chip, deposit isolating metal and front metal, isolating metal and front metal are aluminum；
18) front metal photoetching: to step 17) silicon chip that processed carries out photoetching, and the front metal in front metal region is in the composite terminal structure 3 of P+ anode 4 and offset wire field plate field limiting ring 32 and floating field limiting ring 31；
19) wet etching front metal: by step 18) silicon chip that processed, the phosphoric acid solution using volume ratio to be 85% at normal temperatures removes the front metal outside the composite terminal structure 3 of P+ anode 4 region and offset wire field plate field limiting ring 32 and floating field limiting ring 31, the photoresist of coating when using stripper to remove front metal photoetching at normal temperatures；
20) front metal alloy: by step 19) silicon chip that processed inserts in alloy furnace tubes by adopting, and front metal part forms front metal alloy, and alloy furnace tubes by adopting temperature is 400 DEG C, and the alloy time is 20min；
21) thinning back side: to step 20) process the silicon chip obtained, chemically-mechanicapolish polish, by silicon wafer thickness from thinning back side to 200um, use thinning back side, reduce the forward conduction resistance of diode, improve the conduction property of diode, improve the reliability of diode；
22) back metal deposit: for step 21) process the silicon chip obtained, carry out direct current plasma sputtering deposit back metal at silicon chip back side, back metal is silver, form backplate, conducting electricity very well of silver so that chip has more preferable electric conductivity, and power consumption is lower；
23) electron beam irradiation: to step 22) process the silicon chip obtained, with the electron beam irradiation of 200kGy dosage, silicon chip introduces defect；
24) chip cutting: by step 23) silicon chip that produces, use scribing machine that silicon chip is divided into one single chip, form individual chips.
Embodiment 2:
A kind of high-voltage fast recovery chip production process of high HTRB reliability low cost, its step is as follows:
1) oxidation front surface in field cleans: configuration hydrofluoric acid solution, by volume ratio water: Fluohydric acid .=6:1 solution is mixed to get, described hydrofluoric acid solution mass concentration is 40%；
Configuring No. 1 liquid, volume ratio be ammonia: hydrogenperoxide steam generator: water=1:1:5-1:2:7 is mixed to get, described ammonia concn mass concentration is 27%；
Configuring No. 2 liquid, by volume ratio hydrogen chloride: hydrogenperoxide steam generator: water=1:1:6-1:2:8 is mixed to get, described hydrogen chloride mass concentration is 37%, hydrogenperoxide steam generator mass concentration is 30%；Cleaning sequence is as follows:
A. use hydrofluoric acid solution to soak silicon chip 30s, use deionized water rinsing；
B. with No. 1 immersion bubble silicon chip 10min, deionized water rinsing is used；
C. the silicon chip 30s after using described hydrofluoric acid solution soaking step b to process, after use deionized water rinsing；
D. with No. 2 immersion bubble silicon chip 10min, afterwards with deionized water rinsing, use described hydrofluoric acid solution to soak 1min, finally with deionized water rinsing, complete silicon chip surface to clean；
2) growth of silicon chip surface field oxide: by step 1) silicon chip that processed is placed in oxidation furnace growth, generates one layer of field oxide, field oxide thickness 1um, and oxidation furnace temperature is 1100 DEG C；
3) P+ boron diffusion photoetching: to step 2) silicon chip that processed carries out photoetching, and 31 composite terminal structure 3 regions being formed at the P+ anode 4 in P+ anode 4 region, offset wire field plate field limiting ring 32 and floating field limiting ring form electric field limiting ring；
4) wet etching corrosion field oxide: to step 3) silicon chip that processed carries out wet etching corrosion, removal step 2 in P+ boron spreads the region of photoetching) field oxide that deposits；Remove the photoresist of P+ boron diffusion photoetching；
5) ion implanting protection oxidation front surface clean: use step 1) same procedure previous step has been processed after silicon chip surface be carried out；
6) growth of ion implanting protection oxide layer: by step 5) silicon chip that processed is placed in oxidation furnace growth, and oxide layer is protected in the patterned area growth one layer in the diffusion of P+ boron, and oxidation furnace temperature is 1000 DEG C；
7) P+ boron ion implanting: by step 6) silicon chip that processed carries out boron ion bom bardment, boron Implanted Silicon Wafer surface under 80KeV energy, and form PN junction, and complete offset wire field plate field limiting ring 32 and the injection of floating field limiting ring 31；
8) wet etching corrosive ions injects protection oxide layer: by step 7) silicon chip that processed; the ammonium fluoride using volume ratio to be 6:1 and hydrofluoric acid solution remove the oxide layer of P+ boron diffused region; wherein said ammonium fluoride and hydrofluoric acid solution; ammonium fluoride mass concentration is 40%, and Fluohydric acid. mass concentration is 40%；Step 12) with 16) in identical.
9) ion propulsion front surface cleans: use step 1) same procedure previous step processed silicon chip carried out surface clean；
10) ion propulsion: by step 9) silicon chip that processed is placed in diffusion furnace, is diffused, and the junction depth of PN junction increases, and completes, to offset wire field plate field limiting ring 32 and the diffusion of floating field limiting ring 31, to activate the boron ion of injection simultaneously；Diffusion furnace temperature is 1200 DEG C；
11) N+ ends ring photoetching: to step 10) silicon chip that processed carries out photoetching, forms the N+ cut-off ring 2 of the high-voltage fast recovery of high HTRB reliability low cost in silicon chip；
12) wet etching corrosion thermal oxide layer: by step 11) silicon chip that processed, the ammonium fluoride using volume ratio to be 6:1 and hydrofluoric acid solution remove the thermal oxide layer that N+ cut-off ring 2 patterned area deposits；
13) N+ ends ring ion implanting: by step 12) silicon chip that processed, use 80KeV energy to carry out phosphonium ion injection at N+ cut-off ring 2, remove N+ with stripper at normal temperatures and end the photoresist on ring 2 surface；
14) deposit PETEOS oxide layer: depositing PETEOS oxide layer in the plasma chamber of 500 DEG C, the thickness of this oxide layer is step 19 by contrived experiment) the offset wire field plate that the formed optimized Electric Field Distribution of offer；
15) front metal contact window photoetching: to step 14) silicon chip that processed carries out photoetching, forms the region of metal contact window in the region of P+ anode 4 and the composite terminal structure 3 of offset wire field plate field limiting ring 32 and floating field limiting ring 31；
16) wet etching corrosion thermal oxide layer: by step 15) silicon chip that processed, use wet etching corrosion, the ammonium fluoride and the hydrofluoric acid solution that use volume ratio to be 6:1 in the region of front metal contact window photoetching remove the thermal oxide layer deposited；The photoresist of front metal contact window photoetching is removed at normal temperatures with stripper；
17) evaporation front metal: by step 16) silicon chip that processed, silicon chip is carried out electron beam evaporation, on silicon chip, deposit isolating metal and front metal, isolating metal and front metal are aluminum；
18) front metal photoetching: to step 17) silicon chip that processed carries out photoetching, and the front metal in front metal region is in the composite terminal structure 3 of P+ anode 4 and offset wire field plate field limiting ring 32 and floating field limiting ring 31；
19) wet etching front metal: by step 18) silicon chip that processed, the phosphoric acid solution using volume ratio to be 85% at normal temperatures removes the front metal outside the composite terminal structure 3 of P+ anode 4 region and offset wire field plate field limiting ring 32 and floating field limiting ring 31, the photoresist of coating when using stripper to remove front metal photoetching at normal temperatures；
20) front metal alloy: by step 19) silicon chip that processed inserts in alloy furnace tubes by adopting, and front metal part forms front metal alloy, and alloy furnace tubes by adopting temperature is 500 DEG C, and the alloy time is 20min；
21) thinning back side: to step 20) process the silicon chip obtained, it is ground thinning, by silicon wafer thickness from thinning back side to 300um；
22) back metal deposit: for step 21) process the silicon chip obtained, carry out direct current plasma sputtering deposit back metal at silicon chip back side, back metal is silver, forms backplate；
23) electron beam irradiation: to step 22) process the silicon chip obtained, with the electron beam irradiation of 800kGy dosage, silicon chip introduces defect；
24) chip cutting: by step 23) silicon chip that produces, use scribing machine that silicon chip is divided into one single chip, form individual chips.
Embodiment 3:
Embodiment 3 is substantially the same manner as Example 1, and difference is step 21) in the method for thinning back side be wet etching.
Embodiment 4:
Embodiment 4 is substantially the same manner as Example 1, and difference is step 21) in the method for thinning back side be atmospheric plasma corrosion.
Below being schematically described the invention and embodiment thereof, this description does not has restricted, and shown in accompanying drawing is also one of embodiment of the invention, and actual structure is not limited thereto.So, if those of ordinary skill in the art is enlightened by it, in the case of without departing from this creation objective, design the frame mode similar to this technical scheme and embodiment without creative, the protection domain of this patent all should be belonged to.
Claims (2)
1. the high-voltage fast recovery chip of a high HTRB, including chip (1), it is characterized in that: also including N+ cut-off ring (2), composite terminal structure (3) and P+ anode (4), described chip (1) is fast recovery diode chip；Chip cuts layer and is followed successively by chip (1), N+ cut-off ring (2), composite terminal structure (3) and P+ anode (4) from right to left, described composite terminal structure (3) is offset wire field plate field limiting ring (32) and floating field limiting ring (31), described floating field limiting ring (31) is near P+ anode (4) side, and offset wire field plate field limiting ring (32) ends ring (2) side near N+.
The high-voltage fast recovery chip of a kind of high HTRB the most according to claim 1, it is characterised in that: described offset wire field plate field limiting ring (32) area is more than floating field limiting ring (31) area.
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| CN201620032556.3U CN205508830U (en) | 2016-01-13 | 2016-01-13 | High HTRB's fast recovery diode chip of high pressure |
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| CN201620032556.3U CN205508830U (en) | 2016-01-13 | 2016-01-13 | High HTRB's fast recovery diode chip of high pressure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105489658A (en) * | 2016-01-13 | 2016-04-13 | 桑德斯微电子器件（南京）有限公司 | High-voltage fast recovery diode chip with high HTRB and production technology of high-voltage fast recovery diode chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105489658A (en) * | 2016-01-13 | 2016-04-13 | 桑德斯微电子器件（南京）有限公司 | High-voltage fast recovery diode chip with high HTRB and production technology of high-voltage fast recovery diode chip |
| CN105489658B (en) * | 2016-01-13 | 2018-06-05 | 桑德斯微电子器件（南京）有限公司 | The high-voltage fast recovery chip and its production technology of a kind of high HTRB |
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