CN101621002A - Manufacturing method of low-voltage transient voltage suppression diode chip - Google Patents
Manufacturing method of low-voltage transient voltage suppression diode chip Download PDFInfo
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- CN101621002A CN101621002A CN200910109522A CN200910109522A CN101621002A CN 101621002 A CN101621002 A CN 101621002A CN 200910109522 A CN200910109522 A CN 200910109522A CN 200910109522 A CN200910109522 A CN 200910109522A CN 101621002 A CN101621002 A CN 101621002A
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Abstract
The invention discloses a manufacturing method of a low-voltage transient voltage suppression diode chip, which is characterized by comprising the following steps: a. selecting a P type crystal orientation monocrystalline silicon piece with resistivity of 0.001-0.02 omega*cm; carrying out chemical polishing and heat treatment gettering technologies on the monocrystalline silicon piece to reduce the defects and the impurity concentration of the surface and near a P/N nodal area of the monocrystalline silicon piece so as to realize the characteristic of low internal current leakage; c. doping chlorine, thermally oxidizing and passivating a P/N nodal surface; and d. bending a P/N node on the edge part of the P/N nodal surface towards a P area through a thermal oxidation technology so as to realize the characteristic of low surface current leakage. The invention can effectively reduce the reverse current leakage.
Description
Technical field
The present invention relates to a kind of semiconductor diode chip manufacturing process, specifically a kind of manufacture method of low-voltage transient voltage suppression diode chip.
Background technology
Transient Suppression Diode (TVS) is clamper type diode again, is a kind of high-effect circuit brake that generally uses in the world at present, and its profile is identical with general-purpose diode, but can absorb the surge power up to thousands of watts.Be characterized under the applied in reverse condition; when bearing a high-octane big pulse, its working impedance is reduced to extremely low conduction value immediately, thereby allows big electric current to pass through; while built in predeterminated level, therefore can effectively be protected precision components in the electronic circuit Jiang Dian Ya Clamp-on.Can be used for anti-lightning strike, anti-overvoltage, anti-interference, absorb surge power etc., be a kind of desirable protection device.
The major parameter of TVS has: rated working reverse voltage VR, reverse breakdown voltage VB, Maximum Reverse Leakage Current IR, maximum clamping voltage VC and peak-peak pulse current IPP.In general the application, TVS works in cut-off state, 85% of its operating voltage VR＜puncture voltage, IR is meant that TVS is in the reverse leakage current under the working inverse voltage state, the size of IR has reflected its energy consumption in normal operation, it is little that we wish that IR tries one's best, to reduce its energy consumption in application.The PN junction reverse breakdown has Zener breakdown and avalanche breakdown, and general two kinds of punctures exist simultaneously, but the puncture when voltage is lower than 5-7V is based on Zener breakdown, and the puncture of voltage when being higher than 5-7V is based on avalanche breakdown.The main breakdown mode of the TVS of puncture voltage＞10V is avalanche breakdown; reverse leakage current IR＜1mA; reduction with puncture voltage; breakdown mode progressively changes to Zener breakdown; its reverse leakage current also can sharply increase; general glassivation technology device; puncture voltage is when＜7V; IR usually can be about 1mA; its I-V curve performance is as Fig. 2-A, and its work energy consumption is bigger, and has a strong impact on the stability of operating circuit; a lot of application scenarios require TVS device IR necessary＜500uA, general glassivation technology TVS can not use.
At these problems, now developed low breakdown voltage punch through voltage inhibitor, U.S. Patent No. 5880511 has been introduced the Transient Voltage Suppressor that N+P-P+N+ gangs up diode.This device has low breakdown voltage, and the leakage current characteristic that has simultaneously is better than the characteristic of the Transient Voltage Suppressor of some prior art.The N+P-P+N+ device that U.S. Patent No. 5880511 is introduced has asymmetric I-E characteristic.In order to make bidirectional transient voltage suppressor, a kind of circuit has been proposed at present, wherein two Transient Voltage Suppressors are antiparallel, and a this scheme not only device has increased expense to obtain intended function.
Summary of the invention
The purpose of this invention is to provide a kind of manufacture method that can effectively reduce the low-voltage transient voltage suppression diode chip of reverse leakage current.
Purpose of the present invention is achieved through the following technical solutions.
A kind of manufacture method of low-voltage transient voltage suppression diode chip is characterized in that: the manufacture method of described low-voltage transient voltage suppression diode chip is:
A, select P type (111) the crystal orientation monocrystalline silicon piece of 0.001～0.02 Ω cm resistivity for use;
B, monocrystalline silicon piece is carried out chemical polishing and heat treatment gettering process, to reduce surface and nearly P/N interface defective and impurity concentration, to realize leakage current characteristic in the low body;
Chlorine thermal oxidation passivation is mixed on c, P/N knot surface;
D, marginal surface part P/N knot is crooked to the P district by thermal oxidation technology is to realize low surface leakage properties of flow.
Described chemical polishing thinning single surface thickness is 10～30um.
High temperature-low temperature-high temperature three-step annealing technology is adopted in described heat treatment, and preferred 700～1000 ℃ of heat treatment temperature is to obtain the nearly cleaning surfaces district of 10～50um.
The described chlorine source of mixing is 1%～10% hydrochloric acid, and oxidizing temperature is 700～1000 ℃.
The thermal oxidation technology passivation is adopted on described P/N knot surface, and nearly surface region P/N knot is crooked to the N district in the oxidizing process, to reduce tracking current.
The present invention compared with prior art has the following advantages.
Low-voltage transient voltage suppression diode chip of the present invention adopts the monocrystalline silicon abrasive disc of P type crystal orientation 0.001～0.02 Ω cm resistivity, for reducing leakage current in the chip body, before diffusion, at first chemical method and heat treatment impurity absorption method are handled silicon chip to reduce defective in silicon slice surface defects and the body.In reasonable heat treatment process, inner a large amount of oxygen precipitations and the induced defect of forming of wafer produces stress field in silicon substrate, thereby helps absorbing the beavy metal impurity that silicon chip surface stains.Because the outdiffusion of wafer surface supersaturation oxygen during high annealing makes to form flawless clear area, so-called intrinsic gettering effect that Here it is on nearly top layer.In traditional systemic impurity process, generally adopt the technology of height-low-Gao three-step annealing.At first, make the oxygen outdiffusion on nearly top layer, oxygen content is lower than forms the required oxygen content of oxygen precipitation wafer high temperature anneal.First step high-temperature heat treatment also can make the dissolving of nearly rim surface zona oxygen precipitation, and ensuing low temperature and high annealing are in order to make oxygen precipitation forming core and growth in the wafer bulk, these oxygen precipitations and induce defective and will absorb the center as metal impurities.
The chip diffusion that the present invention relates to adopts liquid phosphorus diffuse source or the P of solid state of phosphorous diffuse source after processing to sink to the bottom silicon chip surface diffusion N+, forms the N+P single side abrupt junction.Adopt mesa technique to etch the P/N knot.Junction depth scope 5～50um.
The chip P/N knot surface passivation employing that the present invention relates to is mixed the oxychloride mode and is captured the alkali metal ion ability to strengthen oxide layer, stop that alkali metal penetrates oxide layer and can play good passivation effect, oxidizing temperature adopts 700～1000 ℃, utilize oxide layer to inhale boron row phosphorus characteristic and realize that surperficial P/N knot is crooked to the N district, increase marginal surface part P/N junction depth, edge breakdown voltage can reduce tracking current greatly greater than puncture voltage in the body.
Chip I R by the technical solution of the present invention manufacturing can be reduced to below the 100uA, its I-V curve performance is as Fig. 2-B, the low pressure TVS device IR that makes than general glassivation technology reduces an order of magnitude, from the I-V curve ratio more as can be seen the inventive method to make the I-V curve turning of chip obviously steep.
Description of drawings
Fig. 1 is an invention low-voltage transient voltage suppression diode chip process chart;
Fig. 2 is the low pressure TVS device (A) of general glassivation technology manufacturing and the I-V curve chart of the low pressure TVS device (B) that the present invention makes.
Embodiment
Describe in further detail below in conjunction with the manufacture method of accompanying drawing the invention low-voltage transient voltage suppression diode chip.
As Fig. 1 and shown in Figure 2, the present invention adopts the monocrystalline silicon abrasive disc of P type crystal orientation 0.001 ~ 0.02 Ω cm resistivity, carries out chemical polishing earlier and handles, to remove grinding silicon chip blemish layer.Use nitric acid, hydrofluoric acid, glacial acetic acid mixed acid cuts open optical processing to silicon chip at low temperatures in cuing open light proportioning ratio, and the single face corrosion thickness is 5-30um.
Cut open silicon chip behind the light and do the heat treatment of height-low-high-temperature curve.At first carry out a step high annealing, continue 750～900 ℃ of multisteps warm treatment process that edges up then.Annealing is carried out in diffusion furnace, the protection of high pure nitrogen atmosphere, and annealing temperature and time are: 1000 ℃ (1 ~ 6h)+700～950 ℃ (temperature edges up)+1000 ℃ (1 ~ 6h).Can obtain the clear area of 15-55um width by this Technology for Heating Processing.
Carry out phosphorous diffusion through heat treated silicon chip, adopt liquid phosphorus diffuse source or solid state of phosphorous diffuse source, this diffusion technology is comparative maturity in the industry, adopt 1100～1280 ℃ of diffusion temperatures, be 0.5～20 hour diffusion time, in conjunction with the clear area that heat treatment obtains, and diffusion junction depth＜clear area width.
Silicon chip after the diffusion adopts the mesa technique etched trench; expose the P/N knot; carry out P/N knot surface oxidation passivation protection then; oxidation technology adopts and does-wet-dry oxidation technology; 700～1000 ℃ of oxidizing temperatures, the dried oxygen 10～30min of dried oxygen 10～30min+ wet oxygen 10～30min+, wet oxygen of the present invention is chloride wet oxygen; the chlorine source is 1%～10% hydrochloric acid, adopts 60-95 ℃ of constant temperature of water-bath heating.
Accomplish metallization by general glassivation technology again after the groove oxidation, the entire chip flow process is finished in scribing.
Claims (5)
1, a kind of manufacture method of low-voltage transient voltage suppression diode chip is characterized in that: the manufacture method of described low-voltage transient voltage suppression diode chip is:
A, select the P type crystal orientation monocrystalline silicon piece of 0.001～0.02 Ω cm resistivity for use;
B, monocrystalline silicon piece is carried out chemical polishing and heat treatment gettering process, to reduce surface and nearly P/N interface defective and impurity concentration, to realize leakage current characteristic in the low body;
Chlorine thermal oxidation passivation is mixed on c, P/N knot surface;
D, marginal surface part P/N knot is crooked to the P district by thermal oxidation technology is to realize low surface leakage properties of flow.
2, the manufacture method of low-voltage transient voltage suppression diode chip according to claim 1 is characterized in that: described chemical polishing thinning single surface thickness is 10～30um.
3, the manufacture method of low-voltage transient voltage suppression diode chip according to claim 1, it is characterized in that: high temperature-low temperature-high temperature three-step annealing technology is adopted in described heat treatment, preferred 700～1000 ℃ of heat treatment temperature is to obtain the nearly cleaning surfaces district of 10～50um.
4, the manufacture method of low-voltage transient voltage suppression diode chip according to claim 1 is characterized in that: the described chlorine source of mixing is 1%～10% hydrochloric acid, and oxidizing temperature is 700～1000 ℃.
5, the manufacture method of low-voltage transient voltage suppression diode chip according to claim 1 is characterized in that: the thermal oxidation technology passivation is adopted on described P/N knot surface, and nearly surface region P/N knot is crooked to the N district in the oxidizing process, to reduce tracking current.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194894A (en) * | 2011-05-06 | 2011-09-21 | 杭州杭鑫电子工业有限公司 | Electrical-surge-resistance low-voltage-protection silicon diode and manufacturing method thereof |
| CN102543720A (en) * | 2010-12-07 | 2012-07-04 | 中国振华集团永光电子有限公司 | Silicon two-way transient voltage suppression diode and manufacture method thereof |
| CN103107086A (en) * | 2013-01-29 | 2013-05-15 | 淄博晨启电子有限公司 | Manufacturing technique of low-voltage chip and low-voltage chip thereof |
| CN103617953A (en) * | 2013-12-12 | 2014-03-05 | 天津中环半导体股份有限公司 | Manufacturing method of matrix type transient suppression diode |
| CN103779205A (en) * | 2014-01-17 | 2014-05-07 | 上海瞬雷电子科技有限公司 | Manufacturing method of transient voltage suppressor chip having tunneling effect |
| CN103956324A (en) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | Production technology for transient voltage suppressor chip with channeling effect |
| CN105374900A (en) * | 2015-10-14 | 2016-03-02 | 横店集团东磁股份有限公司 | Method for preparing monocrystalline silicon surface-passivated cell |
| CN107833834A (en) * | 2017-09-29 | 2018-03-23 | 天水天光半导体有限责任公司 | A kind of manufacture method of transient voltage suppression diode chip |
| CN109309142A (en) * | 2017-07-26 | 2019-02-05 | 天津环鑫科技发展有限公司 | A kind of blunt preceding liquid source diffusion technique of silicon wafer glass |
| CN111128698A (en) * | 2019-12-26 | 2020-05-08 | 安徽芯旭半导体有限公司 | Novel diffusion process of TVS chip |
| CN114171385A (en) * | 2022-02-14 | 2022-03-11 | 浙江里阳半导体有限公司 | Low-voltage transient suppression diode and manufacturing method thereof |
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| CN200972861Y (en) * | 2006-11-20 | 2007-11-07 | 绍兴科盛电子有限公司 | Low voltage transient curb diode chip |
| CN101425463A (en) * | 2007-10-30 | 2009-05-06 | 上海韦尔半导体股份有限公司 | TVS diode device construction with low voltage/low leakage current and production method thereof |
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2009
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN200972861Y (en) * | 2006-11-20 | 2007-11-07 | 绍兴科盛电子有限公司 | Low voltage transient curb diode chip |
| CN101425463A (en) * | 2007-10-30 | 2009-05-06 | 上海韦尔半导体股份有限公司 | TVS diode device construction with low voltage/low leakage current and production method thereof |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543720B (en) * | 2010-12-07 | 2015-03-04 | 中国振华集团永光电子有限公司 | Silicon two-way transient voltage suppression diode and manufacture method thereof |
| CN102543720A (en) * | 2010-12-07 | 2012-07-04 | 中国振华集团永光电子有限公司 | Silicon two-way transient voltage suppression diode and manufacture method thereof |
| CN102194894A (en) * | 2011-05-06 | 2011-09-21 | 杭州杭鑫电子工业有限公司 | Electrical-surge-resistance low-voltage-protection silicon diode and manufacturing method thereof |
| CN103107086A (en) * | 2013-01-29 | 2013-05-15 | 淄博晨启电子有限公司 | Manufacturing technique of low-voltage chip and low-voltage chip thereof |
| CN103107086B (en) * | 2013-01-29 | 2015-03-11 | 淄博晨启电子有限公司 | Manufacturing technique of low-voltage chip and low-voltage chip thereof |
| CN103617953A (en) * | 2013-12-12 | 2014-03-05 | 天津中环半导体股份有限公司 | Manufacturing method of matrix type transient suppression diode |
| CN103779205A (en) * | 2014-01-17 | 2014-05-07 | 上海瞬雷电子科技有限公司 | Manufacturing method of transient voltage suppressor chip having tunneling effect |
| CN103956324A (en) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | Production technology for transient voltage suppressor chip with channeling effect |
| CN103956324B (en) * | 2014-04-30 | 2017-01-18 | 天津中环半导体股份有限公司 | Production technology for transient voltage suppressor chip with channeling effect |
| CN105374900A (en) * | 2015-10-14 | 2016-03-02 | 横店集团东磁股份有限公司 | Method for preparing monocrystalline silicon surface-passivated cell |
| CN109309142A (en) * | 2017-07-26 | 2019-02-05 | 天津环鑫科技发展有限公司 | A kind of blunt preceding liquid source diffusion technique of silicon wafer glass |
| CN109309142B (en) * | 2017-07-26 | 2021-09-07 | 天津环鑫科技发展有限公司 | Liquid source diffusion process before silicon wafer glass passivation |
| CN107833834A (en) * | 2017-09-29 | 2018-03-23 | 天水天光半导体有限责任公司 | A kind of manufacture method of transient voltage suppression diode chip |
| CN111128698A (en) * | 2019-12-26 | 2020-05-08 | 安徽芯旭半导体有限公司 | Novel diffusion process of TVS chip |
| CN114171385A (en) * | 2022-02-14 | 2022-03-11 | 浙江里阳半导体有限公司 | Low-voltage transient suppression diode and manufacturing method thereof |
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| CN101621002B (en) | 2014-04-16 |
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