CN103779205A - Manufacturing method of transient voltage suppressor chip having tunneling effect - Google Patents
Manufacturing method of transient voltage suppressor chip having tunneling effect Download PDFInfo
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- CN103779205A CN103779205A CN201410021035.3A CN201410021035A CN103779205A CN 103779205 A CN103779205 A CN 103779205A CN 201410021035 A CN201410021035 A CN 201410021035A CN 103779205 A CN103779205 A CN 103779205A
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- 230000001052 transient effect Effects 0.000 title claims abstract description 22
- 230000000694 effects Effects 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000005641 tunneling Effects 0.000 title abstract 3
- 238000009792 diffusion process Methods 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000008021 deposition Effects 0.000 claims abstract description 17
- 238000001962 electrophoresis Methods 0.000 claims abstract description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000005245 sintering Methods 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 14
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 11
- 239000011574 phosphorus Substances 0.000 claims abstract description 11
- 238000007747 plating Methods 0.000 claims abstract description 9
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000005520 cutting process Methods 0.000 claims abstract description 5
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 48
- 229910052710 silicon Inorganic materials 0.000 claims description 48
- 239000010703 silicon Substances 0.000 claims description 48
- 230000001629 suppression Effects 0.000 claims description 17
- 239000008367 deionised water Substances 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- 229910021641 deionized water Inorganic materials 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 9
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 238000002203 pretreatment Methods 0.000 claims description 6
- 238000012958 reprocessing Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 5
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000006396 nitration reaction Methods 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 2
- 229960000583 acetic acid Drugs 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 239000012362 glacial acetic acid Substances 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 229910017604 nitric acid Inorganic materials 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 1
- 239000010931 gold Substances 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 238000013459 approach Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000004506 ultrasonic cleaning Methods 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 239000012459 cleaning agent Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- NUHSROFQTUXZQQ-UHFFFAOYSA-N isopentenyl diphosphate Chemical compound CC(=C)CCO[P@](O)(=O)OP(O)(O)=O NUHSROFQTUXZQQ-UHFFFAOYSA-N 0.000 description 2
- 101150012579 ADSL gene Proteins 0.000 description 1
- 102100020775 Adenylosuccinate lyase Human genes 0.000 description 1
- 108700040193 Adenylosuccinate lyases Proteins 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
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- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
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Abstract
The invention discloses a manufacturing method of a transient voltage suppressor chip having the tunneling effect. The method comprises the following steps: 1) treatment before oxidation; 2) oxidation; 3) photoetching; 4) single-sided oxide layer removal; 5) treatment before diffusion; 6) phosphorus diffusion pre-deposition; 7) treatment after pre-deposition; 8) phosphorus diffusion; 9) treatment after diffusion; 10) mesa etching; 11) electrophoresis; 12) sintering; 13) oxide layer removal; 14) nickel plating and gold plating; 15) and chip cutting. The manufacturing method disclosed in the invention can be used to realize the tunneling effect of the chip to reduce the chip Vc value, wherein the Ipp capability of the chip is greater than a same conventional chip.
Description
Technical field
The present invention relates to a kind of chip, in particular, relate to a kind of manufacture method of the Transient Suppression Diode chip with tunnel effect.
Background technology
Transient diode (TVS) is a kind of high-effect protection device of diode form.In the time that the two poles of the earth of TVS diode are subject to reverse transient state high energy impact events; it can be with 10 the speed of bearing 12 power second-times; the high impedance of its two interpolar is become to Low ESR; absorb the surge power up to thousands of watts; simultaneously by voltage clamp in a predetermined value; effectively protect the precision components in electronic circuit, avoid the damage of various surge pulses.Because it has fast response time, transient power is large, leakage current is low, puncture voltage deviation is little, clamping voltage is more easy to control, without damage limit, the advantages such as volume is little, be widely used at present computer system, communication apparatus, AC/DC power supply, automobile, electric ballast, household electrical appliance, instrument and meter (kilowatt-hour meter), RS232/422/423/485, I/O, LAN, ISDN, ADSL, USB, MP3, PDAS, GPS, CDMA, GSM, the protection of digital camera, common mode/differential mode protection, RF coupling/IC drives and receives protection, motor electromagnetic wave interference suppresses, audio/video input, transducer/speed changer, industry control loop, relay, the every field such as the inhibition of contactor noise.
The major parameter of TVS has: specified oppositely by operating voltage VRWM, and reverse breakdown voltage VBR, maximum clamping voltage VC and Maximum Peak Impulse Current IPP.Under normal circumstances, the VC value of TVS is 1.3 times of left and right of VBR, although can meet the device of conventional scheme uses, but flourish along with semiconductor technology, the integrated degree of IC chip is more and more higher, its withstand voltage also becomes more and more lower simultaneously, and the VC value of conventional TVS pipe can not meet whole demands of this respect.
Summary of the invention
The present invention is directed to the technical problem existing in above-mentioned prior art, a kind of manufacture method of the Transient Suppression Diode chip with tunnel effect is provided, not only make IPP ability promote greatly, make V simultaneously
cvalue approaches the V of a times
bR, better protect rear end IC chip to avoid the damage of various surges and other interference.
For achieving the above object, the technical solution adopted in the present invention is as follows:
There is a manufacture method for the Transient Suppression Diode chip of tunnel effect, comprise that step is as follows:
1) oxidation pre-treatment: silicon chip surface is carried out to chemical treatment;
2) oxidation: the layer of oxide layer of growing on original silicon chip is done mask, stops that boron diffusion source enters N+ face, open channels;
3) photoetching: the silicon chip after oxidation is formed to table top figure;
4) remove one side oxide layer: remove silicon chip one side oxide layer;
5) diffusion pre-treatment: the silicon chip after deoxidation layer is carried out to chemical treatment;
6) phosphorus diffusion pre-deposition: silicon chip is put into diffusion furnace, and pass into phosphorus oxychloride and carry out pre-deposition;
7) pre-deposition reprocessing: silicon chip is separated, and remove surface oxide layer;
8) phosphorus diffusion: the silicon chip after pre-deposition is spread at diffusion furnace, form PN junction;
9) diffusion reprocessing: silicon chip is separated, and remove surface oxide layer;
10) mesa etch: etching groove, gash depth arrives P
+layer, controls nitration mixture temperature, and washes down with deionized water;
11) electrophoresis: silicon chip is placed in the electrophoresis liquid configuring, the glass weight setup times that need deposit according to table top groove, carries out glass electrophoresis;
12) sintering: the silicon chip after electrophoresis is carried out in sintering furnace to sintering;
13) deoxidation layer: silicon chip surface oxide layer after cleaning removal sintering;
14) nickel plating, gold-plated: the silicon chip after deoxidation layer is carried out to nickel plating, gold-plated, dry;
15) chip cutting: the silicon chip after gold-plated is divided into one single chip from table top groove.
Described Transient Suppression Diode adopts the monocrystalline silicon abrasive disc of P type crystal orientation 0.090～0.2 Ω/cm resistivity.
The Transient Suppression Diode with tunnel effect provided by the present invention, by raw material and diffusion technology are redesigned, and carries out multiple batches of contrast, find optimization material, process program, realize tunnel effect, chip Vc value is reduced, Ipp ability is greater than identical conventional chip.
The chip diffusion the present invention relates to adopts liquid phosphorus diffuse source, the stability during having guaranteed and consistency.Adopt mesa technique to etch P/N knot.Junction depth scope 30-70 μ m.
Its Ipp ability of the chip of manufacturing by technical solution of the present invention is still more than 2 of identical stock size chip times, and makes its Vc value approach V
bR.
Accompanying drawing explanation
Fig. 1 is the process chart of manufacture method of the present invention;
Fig. 2 is the Facad structure schematic diagram of chip of the present invention;
Fig. 3 is the I/V curve chart of the present invention's Transient Suppression Diode with tunnel effect.
Embodiment
Technical solution of the present invention is further described in detail in conjunction with Figure of description by specific embodiment below.
Please refer to Fig. 1, the manufacture method flow chart with tunnel effect characteristic chip disclosed in this invention, mainly comprises that step is as follows:
1) oxidation pre-treatment:
By the operation such as electronic cleaning agent, washed with de-ionized water, silicon chip surface is carried out to chemical treatment;
2) oxidation:
The original silicon chip cleaning up, in the oxidation furnace of 1100～1200 ℃, long layer of oxide layer is done mask, stops that boron diffusion source enters N+ face, groove;
3) photoetching:
Silicon chip after oxidation is carried out to gluing, exposure, developing procedure, form table top figure;
4) remove one side oxide layer:
Remove silicon chip one side oxide layer by process silicon etching solution, deionized water operation;
5) diffusion pre-treatment:
Silicon chip by electronic cleaning agent, the ultrasonic spilling water of deionized water after to deoxidation layer carries out chemical treatment;
6) phosphorus diffusion pre-deposition:
Silicon chip is put into the diffusion furnace of 1100～1150 ℃, and passed into phosphorus oxychloride and carry out pre-deposition;
7) pre-deposition reprocessing:
With acid soak, deionized water ultrasonic cleaning, silicon chip is separated, and remove surface oxide layer;
8) phosphorus diffusion:
Silicon chip after pre-deposition is spread at 1200～1250 ℃ of diffusion furnaces, form PN junction.
9) diffusion reprocessing:
With acid soak, deionized water ultrasonic cleaning, silicon chip is separated, and remove surface oxide layer;
10) mesa etch:
Use hydrofluoric acid, nitric acid, glacial acetic acid, according to the ratio etching groove of 8:3:3, gash depth arrives P
+layer, nitration mixture temperature is controlled at 0～10 ℃, and washes down with deionized water;
11) electrophoresis:
Silicon chip is placed in the electrophoresis liquid configuring, the glass weight setup times that need deposit according to table top groove, carries out glass electrophoresis;
12) sintering:
Silicon chip after electrophoresis is carried out in the sintering furnace of 800～820 ℃ to sintering;
13) deoxidation layer:
By silicon chip surface oxide layer after the hydrofluoric acid dips of diluting, deionized water ultrasonic cleaning removal sintering;
14) nickel plating, gold-plated:
Silicon chip after deoxidation layer is carried out in special coating bath to nickel plating, gold-plated, dry;
15) chip cutting:
Silicon chip after gold-plated is divided into one single chip from table top groove with scribing machine.
After chip cutting completes, carry out the performance test of chip.
Figure 2 shows that the Facad structure schematic diagram of chip of the present invention, in figure, etching groove 1, passivation glass 2, nickel plating, gold-plated metal level 3.
The present invention shown in Fig. 3 has the I/V curve chart of the Transient Suppression Diode of tunnel effect, visible in figure, the chip that technical solution of the present invention is manufactured, and its Ipp ability is not still more than 2 of identical stock size chip times, and its Vc value approaches V
bR.
Above-described embodiment is only for the present invention is described, but and is not used in the protection range that limits claim.Every equivalents of carrying out on the basis of technical solution of the present invention and improvement, all should not get rid of outside protection scope of the present invention.
Claims (8)
1. a manufacture method with the Transient Suppression Diode chip of tunnel effect, is characterized in that, comprises that step is as follows:
1) oxidation pre-treatment: silicon chip surface is carried out to chemical treatment;
2) oxidation: the layer of oxide layer of growing on original silicon chip is done mask, stops that boron diffusion source enters N+ face, open channels;
3) photoetching: the silicon chip after oxidation is formed to table top figure;
4) remove one side oxide layer: remove silicon chip one side oxide layer;
5) diffusion pre-treatment: the silicon chip after deoxidation layer is carried out to chemical treatment;
6) phosphorus diffusion pre-deposition: silicon chip is put into diffusion furnace, and pass into phosphorus oxychloride and carry out pre-deposition;
7) pre-deposition reprocessing: silicon chip is separated, and remove surface oxide layer;
8) phosphorus diffusion: the silicon chip after pre-deposition is spread at diffusion furnace, form PN junction;
9) diffusion reprocessing: silicon chip is separated, and remove surface oxide layer;
10) mesa etch: etching groove, gash depth arrives P
+layer, controls nitration mixture temperature, and washes down with deionized water;
11) electrophoresis: silicon chip is placed in the electrophoresis liquid configuring, the glass weight setup times that need deposit according to table top groove, carries out glass electrophoresis;
12) sintering: the silicon chip after electrophoresis is carried out in sintering furnace to sintering;
13) deoxidation layer: silicon chip surface oxide layer after cleaning removal sintering;
14) nickel plating, gold-plated: the silicon chip after deoxidation layer is carried out to nickel plating, gold-plated, dry;
15) chip cutting: the silicon chip after gold-plated is divided into one single chip from table top groove.
2. the manufacture method of the Transient Suppression Diode chip with tunnel effect according to claim 1, is characterized in that, described Transient Suppression Diode adopts the monocrystalline silicon abrasive disc of P type crystal orientation 0.090～0.2 Ω/cm resistivity.
3. the manufacture method of the Transient Suppression Diode chip with tunnel effect according to claim 1, it is characterized in that, described step 2) middle oxidation, by the original silicon chip cleaning up, in the oxidation furnace of 1100～1200 ℃, long layer of oxide layer is done mask, stops that boron diffusion source enters N+ face, groove.
4. the manufacture method of the Transient Suppression Diode chip with tunnel effect according to claim 1, it is characterized in that, in described step 6), phosphorus diffusion pre-deposition, is silicon chip to be put into the diffusion furnace of 1100～1150 ℃, and passes into phosphorus oxychloride and carry out pre-deposition.
5. the manufacture method of the Transient Suppression Diode chip with tunnel effect according to claim 1, is characterized in that, in described step 8), phosphorus diffusion, is that the silicon chip after pre-deposition is spread at 1200～1250 ℃ of diffusion furnaces, forms PN junction.
6. the manufacture method of the Transient Suppression Diode chip with tunnel effect according to claim 1, it is characterized in that mesa etch in described step 10) is to use hydrofluoric acid, nitric acid, glacial acetic acid, according to the ratio etching groove of 8:3:3, gash depth arrives P
+layer, nitration mixture temperature is controlled at 0～10 ℃, and washes down with deionized water.
7. the manufacture method of the Transient Suppression Diode chip with tunnel effect according to claim 1, it is characterized in that electrophoresis in described step 11) is that silicon chip is placed in the electrophoresis liquid configuring, the glass weight setup times that need deposit according to table top groove, carries out glass electrophoresis.
8. the manufacture method of the Transient Suppression Diode chip with tunnel effect according to claim 1, is characterized in that, sintering in described step 12) is the silicon chip after electrophoresis to be carried out in the sintering furnace of 800～820 ℃ to sintering.
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| CN201410021035.3A CN103779205A (en) | 2014-01-17 | 2014-01-17 | Manufacturing method of transient voltage suppressor chip having tunneling effect |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201102A (en) * | 2014-08-28 | 2014-12-10 | 苏州启澜功率电子有限公司 | Fast recovery diode FRD chip and production process for same |
| CN104392899A (en) * | 2014-10-08 | 2015-03-04 | 程德明 | Sand-blasting-free diffusion nickel plating technology of rectification monocrystalline silicon wafer |
| CN104466606A (en) * | 2014-11-18 | 2015-03-25 | 宁波日鼎电子科技有限公司 | Electrophoresis processing method with connector outer shell being partially connected |
| CN104810281A (en) * | 2015-03-11 | 2015-07-29 | 苏州启澜功率电子有限公司 | Transient voltage suppression diode array chip according to mesa trench isolation method and production technology thereof |
| CN107346790A (en) * | 2016-05-06 | 2017-11-14 | 杭州东沃电子科技有限公司 | A kind of Transient Voltage Suppressor（TVS）Chip and manufacture method |
| CN109755112A (en) * | 2017-11-01 | 2019-05-14 | 天津环鑫科技发展有限公司 | Secondary diffusion process before glass passivation of unidirectional TVS chip |
| CN111276393A (en) * | 2020-03-11 | 2020-06-12 | 天水天光半导体有限责任公司 | Manufacturing method of wafer-level packaging transient voltage suppression diode |
| CN114843180A (en) * | 2022-05-03 | 2022-08-02 | 江苏晟驰微电子有限公司 | Chemical corrosion junction removing equipment and process for manufacturing rectifier tube |
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| CN101621002A (en) * | 2009-08-05 | 2010-01-06 | 百圳君耀电子（深圳）有限公司 | Manufacturing method of low-voltage transient voltage suppression diode chip |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104201102A (en) * | 2014-08-28 | 2014-12-10 | 苏州启澜功率电子有限公司 | Fast recovery diode FRD chip and production process for same |
| CN104201102B (en) * | 2014-08-28 | 2017-12-12 | 苏州启澜功率电子有限公司 | A kind of fast recovery diode FRD chips and its manufacture craft |
| CN104392899A (en) * | 2014-10-08 | 2015-03-04 | 程德明 | Sand-blasting-free diffusion nickel plating technology of rectification monocrystalline silicon wafer |
| CN104466606A (en) * | 2014-11-18 | 2015-03-25 | 宁波日鼎电子科技有限公司 | Electrophoresis processing method with connector outer shell being partially connected |
| CN104810281A (en) * | 2015-03-11 | 2015-07-29 | 苏州启澜功率电子有限公司 | Transient voltage suppression diode array chip according to mesa trench isolation method and production technology thereof |
| CN104810281B (en) * | 2015-03-11 | 2017-12-19 | 苏州启澜功率电子有限公司 | A kind of chip and its production technology of mesa trench isolation method TVS array |
| CN107346790A (en) * | 2016-05-06 | 2017-11-14 | 杭州东沃电子科技有限公司 | A kind of Transient Voltage Suppressor（TVS）Chip and manufacture method |
| CN109755112A (en) * | 2017-11-01 | 2019-05-14 | 天津环鑫科技发展有限公司 | Secondary diffusion process before glass passivation of unidirectional TVS chip |
| CN109755112B (en) * | 2017-11-01 | 2021-09-07 | 天津环鑫科技发展有限公司 | Secondary diffusion process before glass passivation of unidirectional TVS chip |
| CN111276393A (en) * | 2020-03-11 | 2020-06-12 | 天水天光半导体有限责任公司 | Manufacturing method of wafer-level packaging transient voltage suppression diode |
| CN111276393B (en) * | 2020-03-11 | 2022-10-04 | 天水天光半导体有限责任公司 | Manufacturing method of wafer-level packaging transient voltage suppression diode |
| CN114843180A (en) * | 2022-05-03 | 2022-08-02 | 江苏晟驰微电子有限公司 | Chemical corrosion junction removing equipment and process for manufacturing rectifier tube |
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Application publication date: 20140507 |