CN212085008U

CN212085008U - Semiconductor discharge tube with negative resistance characteristic

Info

Publication number: CN212085008U
Application number: CN201921700554.7U
Authority: CN
Inventors: 单少杰; 苏海伟; 魏峰; 王帅; 张英鹏
Original assignee: Shanghai Wei'an Semiconductor Co ltd
Current assignee: Shanghai Wei'an Semiconductor Co ltd
Priority date: 2019-07-01
Filing date: 2019-10-12
Publication date: 2020-12-04
Anticipated expiration: 2029-10-12

Abstract

The utility model provides a semiconductor discharge tube with negative resistance characteristic. The method comprises the following steps: a substrate, a P2 region, an N1 region, a P1 region, a front metal electrode and a back metal electrode; the P2 area is prepared by utilizing a doping process on one side of the substrate; the N1 area is prepared on one side of the P2 area by using a doping process; the P1 area is prepared on one side of the N1 area by utilizing a doping process; the front metal electrode is prepared at one side of the P1 area; the back metal electrode carries out the metal contact for the back of the substrate after carrying out the attenuate processing and handles the preparation, the utility model discloses can realize reducing the purpose that the residual voltage improves the surge ability.

Description

Semiconductor discharge tube with negative resistance characteristic

Technical Field

The utility model belongs to the technical field of the semiconductor, in particular to semiconductor discharge tube with negative resistance characteristic.

Background

At present, semiconductor discharge tubes (thyristorsurgesuper) are also called: the device comprises a protective thyristor surge suppression thyristor, a thyristor surge suppressor, a surge suppression thyristor, a TSS and a solid discharge tube. The device is an overvoltage protection device, is manufactured by using the thyristor principle, is triggered to conduct and discharge by the breakdown current of a PN junction, and can flow a large surge current or pulse current. The device absorbs surge energy to protect the rear-stage circuit from being damaged by the surge. The device is widely applied to communication ports and signal ports. Strong surge capability and low residual voltage are the direction of device optimization.

The surge capacity is improved, so that the protection device can be effectively protected from being damaged when the device is interfered by worse surge. The influence of surge to the back-stage circuit can be better eliminated to low residual voltage, prevents that back-end circuit from receiving damage after the residual voltage influences. When the diffusion sheet is used for producing TSS devices in the industry at present, the structure is usually N₁P₁N₂P₂Structure (as in FIG. 1) or P² ₁N² ₁P² ₂N² ₂Structure (see fig. 2). Wherein N is₂(P² ₂) The structure is realized by doping the original substrate. Due to the limitation of the thinning process and the diffusion process N₂(P² ₂) The region thickness cannot be made very thin, and is generally larger than the minority carrier diffusion length.Due to the long base region length, the negative resistance effect of the device is difficult to generate. The residual voltage of the device is high, and the rear-stage circuit cannot be well protected. The negative resistance effect can effectively reduce the residual voltage. According to the semiconductor thermal burning theory, under the condition of large current injection, the negative resistance device has smaller equivalent resistance, and the larger surge current can pass. From the perspective of surge capacity and residual voltage, the stronger the negative resistance characteristic, the better the surge capacity and the lower the residual voltage.

Therefore, in view of the above-mentioned shortcomings in the actual manufacturing and implementation, the present invention is modified and improved, and is created with the help of professional knowledge and experience, and after many kinds of ingenuity and experiments, based on the spirit and concept of the present invention, and it is a particular object to provide a method for manufacturing a semiconductor discharge tube with negative resistance, which can reduce residual voltage and improve surge capability.

SUMMERY OF THE UTILITY MODEL

The utility model provides a semiconductor discharge tube manufacturing approach with negative resistance characteristic has solved the problem among the prior art.

The technical scheme of the utility model is realized like this: a semiconductor discharge tube having a negative resistance characteristic, comprising: a substrate, a P2 region, an N1 region, a P1 region, a front metal electrode and a back metal electrode; the P2 area is prepared by utilizing a doping process on one side of the substrate; the N1 area is prepared on one side of the P2 area by using a doping process; the P1 area is prepared on one side of the N1 area by utilizing a doping process; the front metal electrode is prepared at one side of the P1 area; the back metal electrode is prepared by carrying out metal contact treatment on the back of the substrate subjected to thinning treatment.

The substrate is an N-type diffusion sheet substrate.

The P1, N1, and P2 regions are on the same side of the N-type diffuser substrate.

The thickness of the P2 area is between 0-30 μm, and the width of the P2 area is less than the minority carrier diffusion length of the P2 area.

The thickness of the thinned substrate is 120-180 μm.

The method for manufacturing the semiconductor discharge tube with the negative resistance characteristic comprises the following steps:

s1: feeding sheets and blanking, and selecting a substrate;

s2: preparing a P2 area, and preparing a P2 area on one side of the substrate by using a doping process;

s3: preparing an N1 area, namely preparing an N1 area on one side of a P2 area by using a doping process;

s4: preparing a P1 area, namely preparing a P1 area on one side of the N1 area by using a doping process;

s5: preparing a front metal electrode on one side of the P1 area;

s6: thinning treatment, namely thinning the original substrate;

s7: and carrying out metal contact treatment on the back of the thinned substrate to manufacture a back electrode.

The doping process comprises an implantation process and/or a diffusion process.

Front metal electrode preparation is performed on the P1 region side in step S5 using NH₃And repairing the surface morphology of the electrode.

In step S7, the back surface of the thinned substrate is subjected to metal contact processing using NH₃And repairing the surface morphology of the electrode.

The thinning process in step S6 includes thinning the lift-off film to a thickness of 120 μm by a film-sticking thinning method.

After the technical scheme is adopted, the beneficial effects of the utility model are that: the utility model discloses the discharge tube device that the method was made is when the protection thunderbolt surge, and lower residual voltage is favorable to better protection back stage circuit. The high surge capability may make the device suitable for higher surge class requirements. The utility model discloses use the vertical technology of the short base region negative resistance of N type thin slice, realize reducing the purpose that the residual voltage improves the surge ability.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1: traditional diffusion sheet process section structure diagram (N)₁P₁N₂P₂Structure);

FIG. 2: cross-section structure diagram of traditional diffusion sheet process (P)² ₁N² ₁P² ₂N² ₂Structure);

FIG. 3: a cross-sectional view of a semiconductor discharge tube having negative resistance characteristics;

FIG. 4: a semiconductor discharge tube with negative resistance characteristics is disclosed;

FIG. 5: a semiconductor discharge tube with negative resistance characteristics is disclosed;

FIG. 6: a semiconductor discharge tube with negative resistance characteristics is disclosed;

FIG. 7: a diffusion sheet feeding and blanking schematic diagram;

FIG. 8: section view of P2 after preparation;

FIG. 9: schematic diagram after N1 zone process;

FIG. 10: p1 schematic post process;

FIG. 11: front electrode back profile;

FIG. 12: a cross-sectional view after thinning;

FIG. 13: back side metallization cross-sectional view;

FIG. 14: traditional TSS current-voltage profile curves;

FIG. 15: a negative resistance characteristic TSS current-voltage sweep curve;

FIG. 16: and comparing the surge residual voltage curves of the traditional TSS device and the negative resistance type TSS device.

Wherein: a region from N1 to N1; N2-N substrate; the P1-P1 region; the P2-P2 region; p² ₁-P² ₁A zone; n is a radical of² ₁–N² ₁A zone; p² ₂–P² ₂A zone; n is a radical of² ₂–N² ₂And (4) a zone.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

Fig. 3 to 6 are sectional views of semiconductor discharge tubes having negative resistance characteristics in different structures manufactured by the method for manufacturing a semiconductor discharge tube having negative resistance characteristics, respectively, in which, unlike fig. 3, the number of regions P1 in fig. 4 is several in a side-by-side arrangement, and, unlike fig. 3, fig. 5 is a view reversely arranged by two structures in fig. 3 with the middle connected by a P-type diffusion sheet, and, unlike fig. 4, fig. 6 is a view reversely arranged by two structures in fig. 4 with the middle connected by a P-type diffusion sheet.

The manufacturing method of the semiconductor discharge tube with the negative resistance characteristic comprises the following steps: sheet feeding and blanking: the appropriate resistivity polishing pad is selected according to the voltage. Typically a <111> crystal orientation, N-type substrate. The cross-sectional view is shown in fig. 7. Preparation of P2 zone: the P2 region preparation is performed using a doping process. Including but not limited to an implantation process, a diffusion process, etc. The cross-sectional view of the P2 area after preparation is shown in FIG. 8.

Zone N1 preparation: the N1 region preparation was performed using a doping process. Including but not limited to an implantation process, a diffusion process, etc. The cross-sectional view of the N1 region after preparation is shown in FIG. 9. Preparation of P1 zone: the P1 region preparation is performed using a doping process. Including but not limited to an implantation process, a diffusion process, etc. The cross-sectional view of the P1 area after preparation is shown in FIG. 10. And preparing a front metal electrode. The cross-sectional view of the device after the front electrode is prepared is shown in FIG. 11. And (5) thinning the original substrate. The thinning can be generally carried out by adopting a CMP or sand blowing process to a specified thickness. Usually the thickness values are around 150 μm. The cross-sectional view of the device after the thinning process is shown in fig. 12.

And back metal contact. The back side metallization process is shown in cross-section in fig. 13. And (4) scribing, packaging and packaging. And carrying out curve scanning test by using the packaged device. A conventional non-negative resistance device is shown in fig. 14. A semiconductor discharge device having a negative resistance characteristic is shown in fig. 15.

Surge tests are performed on the conventional device and the negative resistance device, and it can be seen that the semiconductor discharge device with the negative resistance has lower residual voltage under the same surge level as that in fig. 16. And adopting a negative resistance longitudinal process of the N-type substrate thin short base region.

The functional structure of the discharge tube manufactured by the method is doped into a PNPN type, and the surge-proof device comprises a unidirectional semiconductor discharge tube and a bidirectional semiconductor discharge tube, and the thickness of a finished chip is between 30 and 250 micrometers. The substrate type selects an N-type diffusion sheet as a substrate, and P1N1P2 structures in the P1N1P2N2 structure are on the same side of the substrate. The P1N1P2 region was prepared using a doping process. The thickness of the P2 region is between 0-30 μm, and the width of the P2 region is less than the minority carrier diffusion length of P2. The discharge tube is used for surge protection and electrostatic protection semiconductor devices. The working voltage range is between 6V and 300V. In the V-I scan curve (using 370, QT, etc. equipment), the semiconductor discharge tube has a negative resistance phenomenon before it is not triggered. When the discharge tube device manufactured by the method is used for protecting lightning surge, lower residual voltage is beneficial to better protecting a rear-stage circuit. The high surge capability may make the device suitable for higher surge class requirements. The method uses the N-type thin sheet short base region negative resistance longitudinal process to achieve the purpose of reducing residual voltage and improving surge capacity.

Based on the above method, the following embodiments are further described by taking a unidirectional negative resistance semiconductor discharge tube as an example.

Feeding and blanking, crystal orientation [111], arsenic-doped substrate slice and resistivity of 2.0 omega cm. And then the cleaning process is carried out by HF + first liquid.

Growing an oxide layer at 900 ℃ for 60 minutes, carrying out wet oxygen treatment at 1050 ℃ for 62 minutes, and carrying out dry oxygen treatment. And photoetching, oxidizing into open holes by post-etching, etching the oxide layer by using an etching solution for 700 seconds to form long base region holes, and removing photoresist by using a photoresist removing solution wet method.

Using 60' O at 1000 DEG C₂Growing a pre-implantation oxide layer.

The boron implantation condition was 60keV3.0E14cm^-2Then annealing activation is carried out, and the annealing condition is 1200 ℃ and 40 minutesClock N₂Annealing in an atmosphere, and then growing an oxide layer by wet oxygen at 960 ℃ for 40 minutes.

And photoetching, opening an oxide layer, corroding the oxide layer for 200 seconds by using an oxide layer corrosive liquid, and removing the injected protective oxide layer. And removing the photoresist by using a photoresist removing liquid wet method.

And (4) coating phosphorus, and then carrying out phosphorus pre-expansion baking.

Oxidizing and pushing under the conditions of 850 ℃ and 10' H₂Or O₂And (6) annealing. The plug temperature was 1100 ℃ for 45 minutes with nitrogen oxide.

And photoetching, opening an oxide layer, corroding the oxide layer for 300 seconds by using an oxide layer corrosive solution, and removing the injected protective oxide layer. And removing the photoresist by using a photoresist removing liquid wet method.

The boron implantation condition was 20keV1.0E14cm^-2. Then annealing activation is carried out, wherein the annealing condition is 960 ℃ for 30 minutes N₂Annealing in an atmosphere enclosure.

NH annealing is carried out to repair the device under the condition of H at 400 ℃ for 30 minutes₂/N₂. Preparation of the front electrode, followed by NH₃And (5) annealing to restore the surface state.

Surface passivation Using LPCVD425 deg.C conditions

And photoetching and etching to form contact surface holes.

And thinning the pasting film, and thinning and uncovering the film to 120 mu m.

And preparing a back electrode, and then repairing the surface state by adopting NH annealing.

The chip is then diced and tested. And packaging by using a traditional SMB packaging and/or a holder process after the preparation of the chip sample.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor discharge tube having a negative resistance characteristic, comprising: a substrate, a P2 region, an N1 region, a P1 region, a front metal electrode and a back metal electrode; the P2 area is prepared by utilizing a doping process on one side of the substrate; the N1 area is prepared on one side of the P2 area by using a doping process; the P1 area is prepared on one side of the N1 area by utilizing a doping process; preparing the front metal electrode on the side of the P1 area; and carrying out metal contact treatment on the back of the thinned substrate to prepare the back metal electrode.

2. The semiconductor discharge tube having a negative resistance characteristic of claim 1, wherein the substrate is an N-type diffusion sheet substrate.

3. The semiconductor discharge tube with negative resistance characteristic of claim 2, wherein the P1 region, N1 region and P2 region are located on the same side of the N-type diffusion sheet substrate.

4. The discharge tube of claim 1, wherein the P2 region has a thickness of 0-30 μm, and the P2 region has a width less than the P2 region minority carrier diffusion length.

5. The discharge tube of claim 1, wherein the thinned substrate has a thickness of 120 μm to 180 μm.