CN111276547A - High-surge-capability low-residual-voltage TVS anti-surge device and manufacturing method thereof - Google Patents
High-surge-capability low-residual-voltage TVS anti-surge device and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 36
- 239000010703 silicon Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000002360 preparation method Methods 0.000 claims abstract description 18
- 238000002161 passivation Methods 0.000 claims abstract description 14
- 230000015556 catabolic process Effects 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
- 239000011574 phosphorus Substances 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 238000004021 metal welding Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 3
- 238000013467 fragmentation Methods 0.000 claims description 2
- 238000006062 fragmentation reaction Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims 2
- 238000003486 chemical etching Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 238000004377 microelectronic Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 208000025274 Lightning injury Diseases 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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Abstract
The invention relates to a TVS anti-surge device with high surge capacity and low residual voltage and a manufacturing method thereof, belonging to the technical field of microelectronics, and the TVS anti-surge device with high surge capacity and low residual voltage comprises a P-type or N-type substrate silicon wafer, wherein a longitudinal TVS anti-surge device is formed by a thinning process and a secondary homotype doping diffusion junction after the preparation of a PN junction main junction on the two sides of the P-type or N-type substrate, the junction depth of the PN junction is 15-35 mu m, a contact metal layer is arranged on the surface of the doping surface, and a passivation layer covers the side surface of the substrate. The invention also provides a preparation method of the device. The present invention is directed to devices that require long wavelength surge capability, such as: the IEC6100010/1000 mu s surge waveform and the ISO 7637-25A/5B waveform have obvious improvement effect.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a TVS anti-surge device with low residual voltage and high surge and a manufacturing method thereof.
Background
The surge (electrical supply) is a peak value exceeding a stable value, which includes a surge voltage and a surge current. In essence, a surge is a sharp pulse that occurs in only a few millionths of a second. The reasons that surge may be caused are: lightning strikes, power line splices, vehicle load rejection, and the like.
When lightning surge occurs, dangerous overvoltage can be generated within the range of 1.5-2 KM by taking lightning as the center. The surge caused by lightning stroke is characterized by single-phase pulse type and huge energy. The voltage of the external surge can rise rapidly from a few hundred volts to 20000V in a few microseconds and can travel a considerable distance. The instantaneous surge can be up to 20000V, and the instantaneous current can reach 10000A. Causing great damage to the electronic equipment.
A Transient Voltage Suppressor (TVS), which is a high-performance electrostatic surge protection device and plays an important role in protecting circuits. With the continuous application of handheld devices, electrostatic protection devices are widely used. Strong surge capability, low residual voltage is the direction of device optimization.
The improvement of surge capacity and the reduction of residual voltage are always pursued targets of TVS devices, and the improvement of surge capacity can effectively protect the devices from being damaged when the devices are interfered by worse surge. The influence on the rear-stage circuit when surge can be better eliminated to low residual voltage when passing through, prevents that the rear-stage circuit from receiving the damage after the residual voltage influences. At present, the surge capacity in unit area is improved by using the process technologies such as a negative resistance process, a resistivity adjustment process, a sheet process and the like. But still fails to meet our requirements.
Disclosure of Invention
The semiconductor surge protection device aims at solving the problem that a traditional semiconductor surge protection device is high in residual voltage and weak in surge capacity, and particularly weak in long-wavelength surge capacity. The invention aims to: a TVS anti-surge device with high surge capacity and low residual voltage is provided.
Another objective of the present invention is to provide a method for manufacturing the TVS surge protection device.
The purpose of the invention is realized by the following scheme: a TVS surge-preventing device with high surge capacity and low residual voltage comprises a P-type or N-type substrate silicon wafer, wherein a longitudinal TVS surge-preventing device is formed by a thinning process and a secondary homotype doping diffusion junction after double-sided or single-sided preparation of a P-type or N-type substrate through a PN junction main junction, the junction depth of the PN junction is 15-35 mu m, a contact metal layer is arranged on the surface of the doping surface, and a passivation layer covers the side surface of the substrate.
On the basis of the scheme, the substrate silicon wafer is a P-type substrate silicon wafer, the double surfaces of the silicon wafer are subjected to primary main junction doping diffusion and then subjected to a main junction preparation thinning process, the junction depth after thinning is 10-35 mu m, and the thickness of the silicon wafer is 150-400 mu m; and then, carrying out second-time doping diffusion junction with the same type to form a longitudinal NPN structure, wherein the depth of the second-time diffusion junction is less than or equal to half of the depth of the junction after the first-time doping diffusion thinning, and finally forming the TVS anti-surge device with the longitudinal NPN structure, wherein the breakdown voltage of the TVS anti-surge device is 8-150V.
On the basis of the scheme, the substrate silicon wafer is an N-type substrate silicon wafer, the thinning process after the main junction preparation is carried out after the two sides of the silicon wafer are subjected to primary main junction doping diffusion, the junction depth after thinning is 10-35 mu m, and the wafer thickness is 150-400 mu m; and then, carrying out second-time doping diffusion junction with the same type to form a longitudinal PNP structure, wherein the depth of the second-time diffusion junction is less than or equal to half of the depth of the junction after the first-time doping diffusion thinning, and finally forming the TVS anti-surge device with the longitudinal PNP structure, wherein the breakdown voltage of the TVS anti-surge device is 8-150V.
The invention has more obvious effect on improving the long-wavelength surge.
The invention also provides a preparation method of the TVS anti-surge device, which comprises the following main steps:
(1) taking a P-type boron-doped silicon substrate slice, and adopting double-sided junction preparation: taking a P-type boron-doped 4-inch substrate, carrying out double-sided phosphorus preliminary diffusion by adopting a paper source diffusion method, carrying out fragmentation after preliminary diffusion doping, carrying out main junction push-out diffusion at the diffusion temperature of 1200-1260 ℃ for 16 hours to form an NPN structure, wherein the breakdown voltage is 26V, and the junction depth is 40 mu m;
(2) the main structure preparation post-thinning process comprises the following steps: adopting a double-sided CMP process, reducing the depth by 20 mu m and the residual junction depth by 30 mu m;
(3) and (3) second diffusion: performing primary diffusion by using a phosphorus source, wherein the diffusion temperature is 800 ℃ for 20 minutes, then performing secondary diffusion by using the condition of 900 ℃ for 10 minutes to form N + heavy doping of a concentrated phosphorus layer, and the second-time diffusion junction depth is less than or equal to half of the junction depth remained after the first-time doping diffusion thinning;
(4) preparing double-sided metal: evaporating AL metal as contact metal, and photoetching to obtain independent AL metal welding spots to obtain the TVS anti-surge device with the NPN structure.
The invention also provides another preparation method of the TVS anti-surge device, which comprises the following main steps:
(1) taking an N-type silicon substrate slice, and adopting double-sided junction preparation: taking an N-type phosphorus-doped 6-inch substrate, preparing a junction by adopting a boron predeposition method, after primary diffusion doping is finished, performing junction-pushing diffusion on a main junction, wherein the diffusion temperature is 1160 ℃ for 24 hours, so as to form a PNP structure, the breakdown voltage of a device is determined to be 64V, and the junction depth is 50 microns;
(2) the main structure preparation post-thinning process comprises the following steps: adopting a double-sided CMP process to reduce the depth by 35 mu m and the residual junction depth by 15 mu m;
(3) and (3) second diffusion: carrying out boron pre-deposition diffusion again, carrying out re-diffusion at 900 ℃ for 10 minutes to form a concentrated phosphorus layer, wherein the second diffusion junction depth is less than or equal to half of the junction depth remained after the first doping diffusion thinning;
(4) preparing double-sided metal: evaporating AL metal on the front surface and the back surface to be used as contact metal, and photoetching and corroding to obtain an independent AL metal welding spot to manufacture the TVS anti-surge device with the PNP structure.
In the preparation steps, the breakdown voltage meeting the requirements is obtained by diffusion and junction pushing; the junction depth is reduced by thinning after the junction is manufactured; and a surface heavily doped region is formed by secondary doping, so that ohmic contact is formed better, and ohmic contact resistance is reduced.
The invention has the following positive effects: the present invention is directed to devices that require long wavelength surge capability, such as: the IEC6100010/1000 mu s surge waveform and the ISO 7637-25A/5B waveform have obvious improvement effect.
Drawings
Fig. 1 is a schematic cross-sectional view of a TVS surge protection device with a mesa NPN structure in embodiment 1;
FIGS. 2 to 6 are schematic cross-sectional views of silicon wafer structures formed in the steps of example 1;
fig. 7 is a schematic cross-sectional view of a TVS surge protection device with a mesa PNP structure in embodiment 2;
FIGS. 8 to 12 are schematic cross-sectional views of silicon wafer structures formed in the steps of example 2;
fig. 13 is a schematic cross-sectional view of a TVS unidirectional anti-surge device with a planar NPN structure;
the reference numbers in the figures illustrate:
example 1
100-P type substrate;
101. 102-front and back side N type doping
103. 104-second doping of front and back N +;
105. 106-left and right mesa trenches;
107-passivation layer;
108. 109-front and back metal contact layers;
in example 2
200-N type substrate;
201. 202-front and back P-type doping;
203. 204-front and back P + type doping;
205. 206-left and right mesa trenches;
207-passivation layer;
208. 209-front and back metal contact layers;
in example 3:
300-P type substrate;
301. 302-doping of front and back N type;
303. 304-doping of positive and back N +;
305-passivation layer;
306. 307-front and back metal contact layers.
Detailed Description
Example 1
A TVS anti-surge device with a mesa NPN structure is shown in figure 1, a substrate silicon wafer is a P-type substrate 111 silicon wafer, the resistivity is 0.046 omega cm, a longitudinal NPN structure is formed by secondary N-type doping on two sides of the silicon wafer, the concentration of first front and back N- type doping 101 and 102 is lower than that of second front and back N + doping 103 and 104, left and right mesa grooves 105 and 106 are formed in two sides of the silicon wafer and are coated by a glass passivation layer 107, front and back metal contact layers 108 and 109 are formed on two sides of the longitudinal NPN structure, the TVS anti-surge device with the mesa NPN structure is formed, and the working voltage of the device is 20V.
The TVS anti-surge device with the NPN structure on the table top is prepared by the following steps:
(1) the P-type substrate 111 is prepared by feeding a P-type boron-doped 4-inch substrate, firstly carrying out preliminary phosphorus diffusion, and then carrying out junction-pushing diffusion, wherein the diffusion temperature is 1260 ℃, the diffusion time is 16 hours, an NPN structure with N- type doping 101 and 102 on the front surface and the back surface is formed, the junction depth is about 40 mu m, and the obtained silicon wafer is shown in figure 2;
(2) thinning the silicon wafer by adopting a double-sided CMP process, wherein the thinning depth is 10 mu m, and the residual junction depth is about 30 mu m, as shown in FIG. 3;
(3) performing primary diffusion by using a phosphorus source, wherein the diffusion temperature is 800 ℃ for 20 minutes, and then performing re-diffusion at 900 ℃ for 10 minutes to obtain positive and back N + doped layers 103 and 104, as shown in FIG. 4;
(4) photoetching and etching to form left and right mesa grooves 105 and 106, as shown in FIG. 5;
(5) carrying out passivation treatment, covering the side surface with a glass passivation layer 107, and then photoetching and etching to open a metal connecting hole, as shown in FIG. 6;
(6) evaporating the AL metal to form front and back metal contact layers 108 and 109, and performing photolithography corrosion to obtain independent AL metal solder joints, thereby obtaining the TVS surge protection device with the mesa NPN structure shown in fig. 1.
When the device of the embodiment is tested, the breakdown voltage of the device is 26V, the leakage under 20V is less than 0.1 muA, the 10-100 waveform surge strength of the device packaged by adopting the traditional process is 800V, and the surge of the device packaged by adopting the new process is more than 1000V. The surge capacity is improved by 25 percent.
Example 2
A TVS surge-proof device with a mesa PNP structure is disclosed, as shown in FIG. 7, a substrate silicon wafer is an N-type substrate 200 silicon wafer, a longitudinal PNP structure is formed on two surfaces of the silicon wafer through secondary P-type doping, wherein the concentrations of primary front and back P- type doping 201 and 202 are lower than those of secondary front and back P + type doping 203 and 204, left and right mesa grooves 205 and 206 are formed in two sides and are coated by a glass passivation layer 207, and a front and back metal contact layers 208 and 209 are formed in the longitudinal PNP structure, so that the TVS surge-proof device with the mesa PNP structure is formed. The breakdown voltage of the device is 68V.
The TVS anti-surge device with the table top PNP structure is prepared by the following steps:
(1) the N-type substrate 200 is prepared by selecting an N-type phosphorus-doped 6-inch substrate, preparing a junction by a boron predeposition method, performing junction-pushing diffusion after initial diffusion doping is completed, wherein the diffusion temperature is 1260 ℃, the diffusion temperature is 24 hours, front and back P- type dopings 201 and 202 are arranged on a silicon wafer to form a longitudinal PNP structure, and the junction depth is about 50 mu m, as shown in FIG. 8;
(2) thinning by adopting a double-sided CMP process, wherein the thinning depth is 35 mu m, and the residual junction depth is about 15 mu m, as shown in FIG. 9;
(3) performing boron pre-deposition diffusion again, and performing re-diffusion at 900 ℃ for 10 minutes to form P + type doped front and back sides 203 and 204 of the concentrated phosphorus layer, as shown in FIG. 10;
(4) photoetching and etching to form left and right mesa grooves 205 and 206, as shown in FIG. 11;
(5) carrying out passivation treatment, covering the side surface with a glass passivation layer 207, and then photoetching and etching to open a metal connecting hole, as shown in FIG. 12;
(6) evaporating the AL metal as a contact metal to form front and back metal contact layers 208 and 209, and performing photolithography corrosion to obtain independent AL metal welding spots, so as to obtain the mesa PNP structure TVS surge protection device as shown in fig. 7.
For the device test of the embodiment: the breakdown voltage of the device is 68V, and the leakage is less than 0.05 muA under the working voltage of 58V. Compared with the traditional process, the surge capacity of the device is improved by more than 10%.
Example 3
A TVS unidirectional anti-surge device with a planar NPN structure is only a longitudinal NPN structure, as shown in FIG. 13, the substrate silicon wafer is a P-type substrate 300 silicon wafer, a longitudinal NPN structure is formed on two sides of the silicon wafer through secondary N-type doping, wherein the concentration of N- type doping 301 and 302 on the front side and the back side formed by the primary N-type doping is lower than that of N + type doping 303 and 304 on the back side and the front side and the back side, the silicon wafer is covered by a silicon dioxide passivation layer 305, metal contact holes are formed in the silicon dioxide passivation layer, front metal contact layers 306 and back metal contact layers 307 are arranged in the metal contact holes, and the TVS unidirectional anti-surge device with the planar NPN.
Claims (6)
1. A TVS surge-proof device with high surge capacity and low residual voltage comprises a P-type or N-type substrate silicon chip and is characterized in that a longitudinal TVS surge-proof device is formed by a thinning process and a secondary homotype doping diffusion junction after the two sides of the P-type or N-type substrate are prepared through a PN junction main junction, the junction depth of the PN junction is 15-35 mu m, a contact metal layer is arranged on the surface of the doping surface, and a passivation layer covers the side surface of the substrate.
2. The TVS surge suppressor with high surge capability and low residual voltage according to claim 1, wherein the substrate silicon wafer is a P-type substrate silicon wafer, a thinning process is performed after main junction preparation is performed after the two surfaces of the silicon wafer are subjected to primary main junction doping diffusion, the junction depth is 10-35 μm after thinning, and the sheet thickness is 150-400 μm; and then, carrying out second-time doping diffusion junction with the same type to form a longitudinal NPN structure, wherein the depth of the second-time diffusion junction is less than or equal to half of the depth of the junction after the first-time doping diffusion thinning, and finally forming the TVS anti-surge device with the longitudinal NPN structure, wherein the breakdown voltage of the TVS anti-surge device is 8-150V.
3. The TVS surge suppressor with high surge capability and low residual voltage according to claim 1, wherein the substrate silicon wafer is an N-type substrate silicon wafer, a thinning process is performed after primary main junction doping diffusion is performed on two surfaces of the silicon wafer, the junction depth is 10-35 μm after thinning, and the wafer thickness is 150-400 μm; and then, carrying out second-time doping diffusion junction with the same type to form a longitudinal PNP structure, wherein the depth of the second-time diffusion junction is less than or equal to half of the depth of the junction after the first-time doping diffusion thinning, and finally forming the TVS anti-surge device with the longitudinal PNP structure, wherein the breakdown voltage of the TVS anti-surge device is 8-150V.
4. A method for preparing a TVS anti-surge device as claimed in claim 1 or 2, comprising the steps of:
(1) taking a P-type boron-doped silicon substrate slice, and adopting double-sided junction preparation: taking a P-type boron-doped 4-inch substrate, carrying out double-sided phosphorus preliminary diffusion by adopting a paper source diffusion method, carrying out fragmentation after preliminary diffusion doping, carrying out main junction push-out diffusion at the diffusion temperature of 1200-1260 ℃ for 16 hours to form an NPN structure, wherein the breakdown voltage is 26V, and the junction depth is 40 mu m;
(2) the main structure preparation post-thinning process comprises the following steps: adopting a double-sided CMP process, reducing the depth by 20 mu m and the residual junction depth by 30 mu m;
(3) and (3) second diffusion: performing primary diffusion by using a phosphorus source, wherein the diffusion temperature is 800 ℃ for 20 minutes, then performing secondary diffusion by using the condition of 900 ℃ for 10 minutes to form N + heavy doping of a concentrated phosphorus layer, and the second-time diffusion junction depth is less than or equal to half of the junction depth remained after the first-time doping diffusion thinning;
(4) preparing double-sided metal: evaporating AL metal as contact metal, and photoetching to obtain independent AL metal welding spots to obtain the TVS anti-surge device with the NPN structure.
5. A method for preparing a TVS anti-surge device as claimed in claim 1 or 3, comprising the steps of:
(1) taking an N-type silicon substrate slice, and adopting double-sided junction preparation: taking an N-type phosphorus-doped 6-inch substrate, preparing a junction by adopting a boron predeposition method, after primary diffusion doping is finished, performing junction-pushing diffusion on a main junction, wherein the diffusion temperature is 1160 ℃ for 24 hours, so as to form a PNP structure, the breakdown voltage of a device is determined to be 64V, and the junction depth is 50 microns;
(2) the main structure preparation post-thinning process comprises the following steps: adopting a double-sided CMP process to reduce the depth by 35 mu m and the residual junction depth by 15 mu m;
(3) and (3) second diffusion: carrying out boron pre-deposition diffusion again, carrying out re-diffusion at 900 ℃ for 10 minutes to form a concentrated phosphorus layer, wherein the second diffusion junction depth is less than or equal to half of the junction depth remained after the first doping diffusion thinning;
(4) preparing double-sided metal: evaporating AL metal on the front surface and the back surface to be used as contact metal, and photoetching and corroding to obtain an independent AL metal welding spot to manufacture the TVS anti-surge device with the PNP structure.
6. The method for preparing TVS anti-surge device according to claim 4 or 5, wherein the main junction is thinned after preparation without being limited to Chemical Mechanical Polishing (CMP), and the thinning is performed by chemical etching and mechanical polishing, and the thinning thickness is not more than the junction depth.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114171416A (en) * | 2022-02-14 | 2022-03-11 | 浙江里阳半导体有限公司 | TVS chip and glass passivation method and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114171416A (en) * | 2022-02-14 | 2022-03-11 | 浙江里阳半导体有限公司 | TVS chip and glass passivation method and manufacturing method thereof |
| CN114171416B (en) * | 2022-02-14 | 2022-06-03 | 浙江里阳半导体有限公司 | TVS chip and glass passivation method and manufacturing method thereof |
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