CN205385026U - Two -way discharge tube chip - Google Patents
Two -way discharge tube chip Download PDFInfo
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- CN205385026U CN205385026U CN201620041983.8U CN201620041983U CN205385026U CN 205385026 U CN205385026 U CN 205385026U CN 201620041983 U CN201620041983 U CN 201620041983U CN 205385026 U CN205385026 U CN 205385026U
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Abstract
The utility model provides a two -way discharge tube chip, two -way discharge tube chip's structure is the N+ -P+ -N - -N -P++ -P+ type, two -way discharge tube chip's planar structure in proper order for diffusion N+ district, diffusion P+ district, pour into N - district, diffusion P++ district, metal area, oxide isolation district, passivation glass layer and chip into and draw and say the district, two -way discharge tube chip's section cut the layer structure in proper order for diffusion N+ district, diffusion P+ district, pour into N - district, substrate N district, diffusion P++ district, metal area, oxide isolation district, passivation glass layer and chip into and draw and say the district. The utility model has the advantages of it is following: adopting the dark knot diffusion in solid -state diffusion source (boron nitride piece) to form the P++ knot, making junction depth evenness, homogeneity good, the antisurge is the reinforce more, can reduce simultaneously the width of base region, make the cut in voltage reduce, response speed is fast, and the consumption is little, the P++ knot can also reduce the bulk resistor, increases the power that bears of discharge tube.
Description
Technical field
This utility model relates to the production technical field of semiconductor discharge tube chip, the low-power consumption two-way discharge die that specifically a kind of voltage is more concentrated.
Background technology
Semiconductor discharge tube is widely used in the programme-controlled exchange in communication exchange device, telephone set, facsimile machine, distributing frame, communication interface, communication transmitting equipment etc., and all need the field of lightning protection, to protect its internal IC from the impact of transient overvoltage and destruction.In current industry, many employing planar technologies make semiconductor discharge tube, there are some technical defects: 1) relatively costly, complex process；2) switching loss is big, and response speed is slow；3) PN junction is formed on surface, adopts silicon dielectric film protection, it is easy to damaged, voltage is in surface breakdown；4) two-way discharge pipe symmetry is poor, can produce one end bad in circuit uses.
Utility model content
For defect of the prior art, this utility model purpose is in that to provide a kind of cut-in voltage low, fast response time；The two-way discharge die that breakdown voltage is more concentrated.
For solving above-mentioned technical problem, this utility model provides a kind of two-way discharge die, and the structure of described two-way discharge die is N+-P+-N--N-P++-P+Type；The planar structure of described two-way discharge die is followed successively by diffusion N+District, diffusion P+District, injection N-District, diffusion P++District, metal area, oxide isolation regions, passivation glass floor and chip road plan district；The section of described two-way discharge die cuts Rotating fields and is followed successively by described diffusion N+District, described diffusion P+District, described injection N-District, substrate N district, described diffusion P++District, described metal area, described oxide isolation regions, described passivation glass floor and described chip road plan district.
The manufacture method of a kind of two-way discharge die, comprises the steps:
Step 1, is carried out silicon chip surface；
Step 2, silicon chip is two-sided growth oxide layer mask in the oxidation furnace of 1100 DEG C～1200 DEG C, and the thickness of oxide layer mask is 1.5 microns～2.5 microns；
Step 3, produces N by photoetching and development the two-sided of silicon chip after oxidation-District's figure；
Step 4, adopts ammonium fluoride etchant to etch N-District；
Step 5, grows sacrificial oxide layer at silicon chip surface；
Step 6, at the N made by lithography-District injects phosphonium ion and advances the deep N of formation-District；
Step 7, with hydrofluoric acid dips, deionized water ultrasonic cleaning, removes surface oxide layer；
Step 8, silicon chip is two-sided growth oxide layer mask in the oxidation furnace of 1100 DEG C～1200 DEG C, and the thickness of oxide layer mask is 1.2 microns～2.0 microns；
Step 9, at N-P is produced by photoetching and development in the adjacent two-sided region in district++District；
Step 10, making P by lithography++The silicon chip in district is put on the quartz boat being provided with boron nitride sheet, then carries out pre-deposition；
Step 11, the silicon chip after pre-deposition carries out deep knot propelling in diffusion furnace and diffuses to form deep P++District；
Step 12, with hydrofluoric acid dips, deionized water ultrasonic cleaning, removes the oxide layer of silicon chip surface；
Step 13, is put into the silicon chip after cleaning on the quartz boat being provided with boron nitride sheet, carries out pre-deposition in diffusion furnace；
Step 14, the silicon chip after pre-deposition carries out propelling in diffusion furnace and diffuses to form P+District；
Step 15, silicon chip is two-sided growth oxide layer mask in the oxidation furnace of 1100 DEG C～1200 DEG C, and the thickness of oxide layer mask is 1.5 microns～2.5 microns；
Step 16, at N-N is produced in region+District；
Step 17, making N by lithography+The silicon chip in district is put in diffusion furnace and is passed into phosphorus oxychloride and carries out pre-deposition；
Step 18, the silicon chip of phosphorus deposition is diffused in diffusion furnace, forms N+District；
Step 19, silicon chip is two-sided growth oxide layer mask in the oxidation furnace of 1100 DEG C～1200 DEG C, and the thickness of oxide layer mask is 0.7 micron～1 micron；
Step 20, by gluing, exposure, development, oxide layer operation, forms mesa trench figure；
Step 21, etched mesa groove also washes down with deionized water；
Step 22, is placed on silicon chip in electrophoresis liquid and carries out glass electrophoresis；
Step 23, is sintered the silicon chip after electrophoresis in 800 DEG C～820 DEG C sintering furnaces；
Step 24, carries out gluing, photoetching, development, oxide layer and glass the silicon chip after sintering, forms metal area and dicing lane；
Step 25, carries out nickel plating, gold-plated, dry to silicon chip；
Step 26, is divided into one single chip the silicon chip after gold-plated from dicing lane with laser cutting machine.
Preferably, in described step 6, at the N made by lithography-District injects 5 × 10 by ion injection method15Kev～8 × 1015The phosphonium ion of kev, and adopt the temperature of 1250 DEG C～1280 DEG C to advance 50 hours～60 hours, form deep N-District.
Preferably, in described step 10, making P by lithography++The silicon chip in district is put on the quartz boat being provided with boron nitride sheet, and silicon chip intersects with boron nitride sheet to be put, and carries out pre-deposition in the diffusion furnace of 1150 DEG C～1200 DEG C.
Preferably, in described step 11, the silicon chip after pre-deposition carries out deep knot in 1250 DEG C～1260 DEG C diffusion furnaces and advances diffusion 20 hours～30 hours, forms deep P++District.
Preferably, in described step 13, the silicon chip after cleaning being put on the quartz boat being provided with boron nitride sheet, silicon chip intersects with boron nitride sheet to be put, and carries out pre-deposition in the diffusion furnace of 1150 DEG C～1200 DEG C.
Preferably, in described step 14, the silicon chip after pre-deposition carries out advancing diffusion 8 hours～12 hours in 1250 DEG C～1260 DEG C diffusion furnaces, forms P+District；
Preferably, in described step 17, making multiple N by lithography+The silicon chip in district is put into and is passed into phosphorus oxychloride in the diffusion furnace of 1100 DEG C～1200 DEG C and carry out pre-deposition.
Preferably, in described step 18, the silicon chip of phosphorus deposition is diffused 4 hours～8 hours in the diffusion furnace of 1150 DEG C～1250 DEG C, forms N+District.
Preferably, in described step 21, using nitric acid, Fluohydric acid., glacial acetic acid to become nitration mixture according to the proportions of 5:3.3:1, etched mesa groove, gash depth is more than P+1.2 times of layer depth～1.5 times, nitration mixture temperature is 0 DEG C～5 DEG C, and washes down with deionized water.
Compared with prior art, this utility model two-way discharge die has the advantage that
1, the deep knot adopting solid-state diffusion source (boron nitride sheet) diffuses to form P++Knot, makes junction depth flatness, homogeneity good, and antisurge more power is strong；Can reducing the width of base simultaneously, make cut-in voltage reduce, fast response time, power consumption is little；P++Knot can also reduce bulk resistor, strengthens the load power of discharge tube；
2, phosphonium ion forms one layer of sacrificial oxide layer method before injecting, it is possible to play the effect of adsorbing contaminant, make phosphonium ion be evenly distributed, reduce leakage current；
3, the method that phosphonium ion injects is adopted to form deep N-Knot, dosage is controlled, even concentration, it is possible to make breakdown voltage more concentrate, and voltage punctures in vivo simultaneously, does not puncture in mesa surfaces, makes the resistance to good fluidity of table top, and Surge handling capability improves；
4, table top adopts double-sided glass powder electrophoresis to form passivation protection layer, has good symmetry, enhances the resistant to mechanical damage ability of two-way discharge pipe, improve the reliability of discharge tube；
5, adopt dicing lane design to use cut chip, reduce the damage of chip, improve production efficiency simultaneously.
Accompanying drawing explanation
By reading detailed description non-limiting example made with reference to the following drawings, further feature of the present utility model. purpose and advantage will become more apparent upon.
Fig. 1 is this utility model two-way discharge die structural plan figure；
Fig. 2 is this utility model two-way discharge die section of structure；
Fig. 3 is the manufacturing approach craft flow chart of this utility model two-way discharge die.
In figure:
1-spreads N+District 2-spreads P+District 3-injects N-District
4-substrate N district 5-spreads P++6-metal area, district
8-passivation glass floor 9-chip road plan district, 7-oxide isolation regions
Detailed description of the invention
Below in conjunction with specific embodiment, this utility model is described in detail.Following example will assist in those skilled in the art and are further appreciated by this utility model, but do not limit this utility model in any form.It should be pointed out that, to those skilled in the art, without departing from the concept of the premise utility, it is also possible to make some changes and improvements.These broadly fall into protection domain of the present utility model.
As shown in FIG. 1 to 3, this utility model provides specifically comprising the following steps that of the manufacture method of a kind of two-way discharge die
1) clean before oxidation: by operations such as electronic cleaning agent SC1 (ammonia+hydrogen peroxide) and SC2 (hydrochloric acid+hydrogen peroxide), deionized water ultrasonic cleaning, silicon chip surface is carried out chemical treatment, obtains clean original silicon chip；
2) oxidation: silicon chip two-sided growth oxide layer mask, the oxide layer mask thickness 1.5 microns～2.5 microns in the oxidation furnace of 1100 DEG C～1200 DEG C that will clean up；
3) photoetching N-: produce the asymmetric N of positive and negative by two-sided for the silicon chip after oxidation by photoetching, development method-District's figure；
4) N is removed-District's oxide layer: adopt ammonium fluoride etchant to etch N-District；
5) long sacrificial oxide layer: grow sacrificial oxide layer one layer thin at silicon chip surface；
6) phosphorus is injected: at the N made by lithography-District injects 5 × 10 by ion injection method15Kev～8 × 1015The phosphonium ion of kev, and adopt temperature be 1250 DEG C～1280 DEG C carry out advance 50 hours～60 hours, form deep N-District；
7) post processing is advanced: with hydrofluoric acid dips, deionized water ultrasonic cleaning, remove surface oxide layer；
8) oxidation: the silicon chip two-sided growth oxide layer mask in the oxidation furnace of 1100 DEG C～1200 DEG C that will clean up, the thickness of oxide layer mask is 1.2 microns～2.0 microns；
9) photoetching P++District: at N-P is produced by photoetching, development in the adjacent two-sided region in district++District；
10) boron source pre-deposition: making P by lithography++The silicon chip in district is put on the quartz boat being provided with boron nitride sheet, and silicon chip intersects with boron nitride sheet to be put, and carries out pre-deposition in the diffusion furnace of 1150 DEG C～1200 DEG C；
11) boron source advances: the silicon chip after pre-deposition carries out deep knot in 1250 DEG C～1260 DEG C diffusion furnaces and advances diffusion 20 hours～30 hours, forms deep P++District；
12) post processing is advanced: with hydrofluoric acid dips, deionized water ultrasonic cleaning, remove surface oxide layer；
13) boron source pre-deposition: the silicon chip after cleaning is put on the quartz boat being provided with boron nitride sheet, and silicon chip intersects with boron nitride sheet to be put, and carries out pre-deposition in the diffusion furnace of 1150 DEG C～1200 DEG C；
14) boron source advances: the silicon chip after pre-deposition carries out advancing diffusion 8 hours～12 hours in 1250 DEG C～1260 DEG C diffusion furnaces, forms P+District；
15) oxidation: silicon chip is two-sided growth oxide layer mask in the oxidation furnace of 1100 DEG C～1200 DEG C, and the thickness of oxide layer mask is 1.5 microns～2.5 microns；
16) photoetching N+District: at N-Produce high concentration by photoetching, development, multiple do not connect N in region+District；
17) phosphorus source pre-deposition: making multiple N by lithography+The silicon chip in district is put into and is passed into phosphorus oxychloride in the diffusion furnace of 1100 DEG C～1200 DEG C and carry out pre-deposition；
18) phosphorus diffusion: the silicon chip of phosphorus deposition is diffused 4 hours～8 hours in the diffusion furnace of 1150 DEG C～1250 DEG C, forms N+District；
19) oxidation: silicon chip is two-sided growth oxide layer mask in the oxidation furnace of 1100 DEG C～1200 DEG C, and the thickness of oxide layer mask is 0.7 micron～1 micron；
20) photoetching mesa trench: by gluing, exposure, development, oxide layer operation, forms mesa trench figure；
21) mesa trench corrosion: using nitric acid, Fluohydric acid., glacial acetic acid to become nitration mixture according to the proportions of 5:3.3:1, etched mesa groove, gash depth is more than P+1.2 times of layer depth～1.5 times, nitration mixture temperature is 0 DEG C～5 DEG C, and washes down with deionized water；
22) electrophoresis glass: configuration electrophoresis liquid, is placed on silicon chip in the electrophoresis liquid configured, and arranges the time (being preferably 50 seconds～200 seconds) according to the glass weight that the mesa trench degree of depth need to deposit, carries out glass electrophoresis；
23) sintering: the silicon chip after electrophoresis is sintered in 800 DEG C～820 DEG C sintering furnaces；
24) photolithographic district and dicing lane: the silicon chip after sintering is carried out gluing, photoetching, development, oxide layer and glass, forms metal area and dicing lane；
25) nickel plating, gold-plated: the silicon chip after oxide layer and dicing lane glass to be carried out nickel plating in metal electric coating bath, gold-plated, dry；
26) chip cutting: the silicon chip after gold-plated is divided into one single chip from mesa trench dicing lane with laser cutting machine.
As shown in Figure 1 and Figure 2, two-way discharge die structure is N+-P+-N--N-P++-P+Type；Plane is cut Rotating fields and is followed successively by diffusion N+District 1, spreads P+District 2, injects N-District 3, spreads P++District 5, metal area 6, oxide isolation regions 7, passivation glass layer 8, chip road plan district 9；Section cuts Rotating fields and is followed successively by diffusion N+District, 1 diffusion P+District 2, injects N-District 3, substrate N district 4, spreads P++District 5, metal area 6, oxide isolation regions 7, passivation glass layer 8, chip road plan district 9.
The parameter of the low-power consumption two-way discharge pipe that the voltage according to said method made more is concentrated, in Table 1:
| Parameter | VDRM | Idm | Vs | IH | VT | Capacitance |
| Test condition | IDRM=1.2uA | VDRM=320V | Is=800mA | IT=2.2A | 1MHz, 2Vbias | |
| Unit | V | uA | V | mA | V | (Pf) |
| Standard value | ≥320 | ≤5 | ≤400 | ≥150 | ≤4 | ≤40 4 --> |
| Measured value | 360 | 0.8 | 380 | 200 | 2.8 | 25 |
Above specific embodiment of the utility model is described.It is to be appreciated that this utility model is not limited to above-mentioned particular implementation, those skilled in the art can make a variety of changes within the scope of the claims or revise, and this has no effect on flesh and blood of the present utility model.When not conflicting, embodiments herein and the feature in embodiment can arbitrarily be mutually combined.
Claims (1)
1. a two-way discharge die, it is characterised in that the structure of described two-way discharge die is N+-P+-N--N-P++-P+Type；
The planar structure of described two-way discharge die is followed successively by diffusion N+District, diffusion P+District, injection N-District, diffusion P++District, metal area, oxide isolation regions, passivation glass floor and chip road plan district；
The section of described two-way discharge die cuts Rotating fields and is followed successively by described diffusion N+District, described diffusion P+District, described injection N-District, substrate N district, described diffusion P++District, described metal area, described oxide isolation regions, described passivation glass floor and described chip road plan district.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620041983.8U CN205385026U (en) | 2016-01-15 | 2016-01-15 | Two -way discharge tube chip |
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| CN201620041983.8U CN205385026U (en) | 2016-01-15 | 2016-01-15 | Two -way discharge tube chip |
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| CN205385026U true CN205385026U (en) | 2016-07-13 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105609549A (en) * | 2016-01-15 | 2016-05-25 | 上海瞬雷电子科技有限公司 | Bi-directional discharge tube chip and manufacturing method thereof |
| WO2017118028A1 (en) * | 2016-01-05 | 2017-07-13 | 深圳市槟城电子有限公司 | Surge protector device |
| CN108933164A (en) * | 2017-05-25 | 2018-12-04 | 程德明 | Laser stereo lithography high-power semiconductor device chip |
-
2016
- 2016-01-15 CN CN201620041983.8U patent/CN205385026U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017118028A1 (en) * | 2016-01-05 | 2017-07-13 | 深圳市槟城电子有限公司 | Surge protector device |
| CN105609549A (en) * | 2016-01-15 | 2016-05-25 | 上海瞬雷电子科技有限公司 | Bi-directional discharge tube chip and manufacturing method thereof |
| CN105609549B (en) * | 2016-01-15 | 2019-04-12 | 上海瞬雷电子科技有限公司 | The manufacturing method of two-way discharge tube chip |
| CN108933164A (en) * | 2017-05-25 | 2018-12-04 | 程德明 | Laser stereo lithography high-power semiconductor device chip |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201023 Address after: Room j9215, building 2, No. 4268, Zhennan Road, Jiading District, Shanghai, 201800 Patentee after: Shanghai sunray Technology Co.,Ltd. Address before: 200443 Shanghai City, Jiading District Nanxiang Town, Fengxiang Road No. 88 Building 1, 1 floor of the South Patentee before: SHANGHAI STARHOPE ELECTRONICS Co.,Ltd. |
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| TR01 | Transfer of patent right |