CN108933164A - Laser stereo lithography high-power semiconductor device chip - Google Patents
Laser stereo lithography high-power semiconductor device chip Download PDFInfo
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- CN108933164A CN108933164A CN201710429684.0A CN201710429684A CN108933164A CN 108933164 A CN108933164 A CN 108933164A CN 201710429684 A CN201710429684 A CN 201710429684A CN 108933164 A CN108933164 A CN 108933164A
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- 238000001459 lithography Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title abstract description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 35
- GVVPGTZRZFNKDS-JXMROGBWSA-N geranyl diphosphate Chemical compound CC(C)=CCC\C(C)=C\CO[P@](O)(=O)OP(O)(O)=O GVVPGTZRZFNKDS-JXMROGBWSA-N 0.000 claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 238000004132 cross linking Methods 0.000 claims description 27
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 15
- 229910052698 phosphorus Inorganic materials 0.000 claims description 15
- 239000011574 phosphorus Substances 0.000 claims description 15
- 230000005540 biological transmission Effects 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 12
- 230000008569 process Effects 0.000 abstract description 11
- 230000004888 barrier function Effects 0.000 abstract description 4
- 238000005538 encapsulation Methods 0.000 abstract description 3
- 239000002210 silicon-based material Substances 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 26
- 238000005530 etching Methods 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
- B23K26/382—Removing material by boring or cutting by boring
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/40—Removing material taking account of the properties of the material involved
- B23K26/402—Removing material taking account of the properties of the material involved involving non-metallic material, e.g. isolators
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
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Abstract
The present invention provides a kind of technical solution of laser stereo lithography production power electronics high-power semiconductor device chip, it solves in technology today, GPP rectification chip and thyristor chip industry are manufactured using n type single crystal silicon material, diffuses into the technology barrier that depletion region causes product characteristic to deteriorate about sub- hole less；The leakage current of product is substantially reduced, and hot properties and rear road encapsulation yield rate are increased dramatically；Have many advantages, such as no investment risk, industrialization level height, simple process.
Description
Technical field
Laser stereo lithography belongs to the " height that state key in 2016 is supported for manufacturing high-power semiconductor device chip technology
In new technical field "：" the large power semiconductor device manufacturing technologies of the other new mechanism of electronic information-new electronic component-"
Scope.
Background technique
Power electronic devices belongs to large power semiconductor device, and core product is rectifier tube chip and thyristor chip,
The power electronic devices product of various specifications type can be made up in both of various sealing-in forms.Analyze two kinds of chip products
Technology shortcoming, studying other new mechanism manufacturing technologies to enhance product performance is the main side of the manufacturing technological innovation
To.
One, GPP rectification chip is due to the limitation of its structure process, and presently, there are a technology shortcoming, is analyzed as follows：
The physics cross-section structure of the GPP silicon substrate rectification chip of online production now is as shown in Fig. 1.In figure, A is that chip is thick
Degree；B is N-type base width, is designated as the area N- on figure；C is p type diffusion region width, and wherein D is P- sector width, be designated as on figure P+ and
The area P-；E is that N-type spreads sector width, is designated as the area N+ on figure；F is the area chip P plane etching groove width；W is chip chemical attack
Grooving depth；G is the mechanical cutoff area of chip edge；S is glass passivation protection area.
When GPP silicon substrate rectification chip is plus the highest backward voltage that the area P is negative, the area N is positive, the area N and the area P will all occur most
Wide depletion layer has marked the equipotential lines of 7 different potentials values in depletion layer in attached drawing 1 with 7 chain-dotted lines.Since charge is flat
Weigh principle, and in chemical attack grooving position W, equipotential lines occurs as shown in Fig. 1 upwarping phenomenon.
Under the action of mechanical cutting power, mechanical cutoff area G produces more silicon atom dislocation, these dislocations can be to core
Piece emits a large amount of electron-hole pair in vivo, especially in the case of a high temperature, square of the electron-hole pair compared to absolute temperature
Value surges, and hole is diffused into the depletion region in equipotential lines, and the direction as shown in arrow in attached drawing 1 will flow under the action of electric field
To the area P, reverse current is formed, has seriously damaged the reverse characteristic of GPP rectification chip, especially reversed hot properties.This is few
Sub- pollution technology barrier annoyings GPP rectification chip manufacturing always, there is no good technical solution can be to so far both at home and abroad
Give solution.
There is the commercial method for increasing etching groove depth W and increasing plane etching groove width F of manufacture, to elongate hole
Diffusion length weakens hole to the diffusion effect of depletion region in equipotential lines, has received certain effect.But it is deep to increase etching groove
Degree, can cause the increase of monocrystalline silicon piece fragment rate；Increase plane etching groove width, and the area the P area of chip can be reduced, increases
Add the forward voltage drop of product, while wasting raw material monocrystalline silicon piece.
Also the method that some manufactures commercial chemical attack mechanical cutoff area G subtracts to reduce the mechanical silicon atom dislocation in the area G
The yield of few electron-hole pair, also has received certain effect.But after chip cutting, at multiple little particles, to corrode place
Blocking district is managed, difficulty in process is difficult to industrialization；Separately in the rear road packaging technology of chip, pollution and heat that blocking district G is formed
Stress, can be repeatedly formed the silicon atom dislocation of blocking district, and this method is also difficult to fundamentally improve the reversed hot properties of product.
Two, thyristor chip is analyzed as follows due to the limitation of its structure process at present there is also a technology shortcoming：
The marginal texture of the thyristor chip of online production now is common, and there are three types of moulding, as shown in attached drawing 6,7,8.
A, attached drawing 6 is the just negative angle shaped sectional structure chart of single side, is usually used in high current product, and in figure, A is chip thickness；B
For N-type base width, the area N- is designated as on figure；C is p type diffusion region width, and wherein D is P- sector width, is designated as the area P+ and P- on figure,
The area P+ surface is the anode of chip；E is that N-type spreads sector width, is designated as the area N+ on figure, surface is the cathode of chip；Positive and negative two
Width shared by angle is F；G is positive angular region；W is negative angular region；S is insulation protection area.
When the thyristor chip area anode P+ adds negative voltage plus positive voltage, the area cathode N+, the internal base area N- and cathode
Depletion layer will all occur in the area P-, mark the equipotential lines of 6 different potentials values in depletion layer in attached drawing 6 with 6 chain-dotted lines.By
In charge balance concept, in the base area N-, equipotential lines occurs as shown in Fig. 6 upwarping phenomenon.
The area P+ and P- of thyristor chip anode can be emitted empty due to multi-hole by diffusion principle to depletion layer direction
Cave forms forward leakage current, arrow direction as shown in Fig. 6.The positive and negative angle surface of chip handles to obtain bright nothing through chemical attack
The service life of dislocation, hole increases considerably, and few sub- hole can easily pass through product surface and diffuse into depletion layer in large quantities,
Very big surface forward leakage current is produced, the forward characteristic of product is destroyed, especially positive hot properties makes many devices
At surface characteristic device.Thyristor chip process for treating surface annoyings thyristor chip manufacturing always.Manufacturer adopts
With a variety of methods, for example, by using surface polymorphic structure method or silica or semi-insulating polysilicon material and surface are used
Silicon atom coordination method, to reduce this influence, but it is unsatisfactory.
B, the double negative angle shaped sectional structure chart such as attached drawings 7 of thyristor chip single side, are usually used in low current product, and in figure, A is
Chip thickness；B is N-type base width, is designated as the area N- on figure；C is p type diffusion region width, and wherein D is P- sector width, figure subscript
For the area P+ and P-, the area P+ surface is the anode of chip；E is that N-type spreads sector width, is designated as the area N+ on figure, surface is chip
Cathode；Width shared by negative angle is F；G is anode negative angle area；W is cathode negative angle area；S is insulation protection area.
This structure of attached drawing 7 add forward voltage when, depletion layer is identical as attached drawing 6 with equipotential lines, equally have anode P+ with
The problem of hole in the area P- flows to cathode by surface along arrow direction as shown in the figure.
C, the two-sided double negative angle shaped sectional structure chart such as attached drawings 8 of thyristor chip, in figure, A is chip thickness；B is N-type base
Sector width is designated as the area N- on figure；C is p type diffusion region width, and wherein D is P- sector width, is designated as the area P+ and P-, the area P+ table on figure
Face is the anode of chip；E is that N-type spreads sector width, is designated as the area N+ on figure, surface is the cathode of chip；Width shared by negative angle
For F；G is anode negative angle area；W is cathode negative angle area；S is insulation protection area.
When this structure of attached drawing 8 adds forward voltage, depletion layer is also identical as attached drawing 6 as equipotential lines, equally there is anode P+
The problem of cathode is flowed to by surface along arrow direction as shown in the figure with the hole in the area P-.
To sum up, GPP rectification chip and thyristor chip industry are manufactured using N-type silicon materials, solves few sub- hole and diffuses into
Enter the technology barrier that depletion region causes product characteristic to deteriorate, so far without good technical solution.
Summary of the invention
The present invention provides a kind of technical solution of laser stereo lithography production power electronics high-power semiconductor device chip, solves
Using n type single crystal silicon material manufacture GPP rectification chip and thyristor chip industry described in background technique, about sub- hole less
Diffuse into the technology barrier that depletion region causes product characteristic to deteriorate；The leakage current of product is substantially reduced, hot properties and rear road
Encapsulation yield rate is increased dramatically；Have many advantages, such as no investment risk, industrialization level height, simple process.
One, the present invention is as follows for the principle of GPP rectification chip manufacture：
Monocrystalline silicon piece cross-section structure is as shown in Fig. 2, refers to before circular single crystal silicon wafer does not diffuse to form PN junction, expands in plan
On the surface of phosphorus, along I at the crosslinking of adjacent two GPP rectification chips in chip layout scheme, laser is controlled with blanking disc
Beam, burns blend-out a succession of similar taper half bore being arranged in a linear on monocrystalline silicon piece, the table of the open end in hole in monocrystalline silicon piece
On face, can rounded, class is oval or strip, the finish no requirement (NR) of the taper and hole wall in hole.
Laser stereo lithography is formed by similar taper half bore, there is two kinds of aligning methods：
The first aligning method forms list along I at the crosslinking of adjacent two GPP rectification chips in chip layout scheme
Round, the surface diameter in hole are 15~30 microns, and the depth in hole is that monocrystalline silicon piece thickness subtracts 50~150 microns.Such as 2 institute of attached drawing
Show.
Monocrystalline silicon piece at high temperature, laser boring face spread phosphorus when, phosphorus atoms will along taper half bore hole wall to
The direction diffusion of vertical hole wall, form the garden area cylindricality N+ as shown in Fig. 2, in phosphorus and boron (or boron aluminium) intersection, by
It is more than boron (or boron aluminium) in the concentration of phosphorus, the structure in the garden area cylindricality N+ is unaffected.
The monocrystalline silicon piece planar structure of the principle of the invention is as shown in Fig. 3, design of the adjacent two laser hole centers away from Δ
Follow following principle：Δ≤[(the overall diameter Φ in hole)+(the diffusion junction depth of 1.5 times of N+)], when hole surface diameter Φ be 15~
At 30 microns, when the diffusion junction depth of N+ is 50~80 microns, adjacent dual-laser hole center is 80~140 microns away from Δ.It is such
Design data is that the phosphorus diffusion area based on adjacent two laser holes can overlap each other linking, forms N+ wall.
Monocrystalline silicon piece after laser stereo lithography and Double side diffusion, continues the GPP rectification chip produced using GPP technique
Cross-section structure is as shown in Fig. 4, unlike attached drawing 1：At the mechanical cutoff area G of chip edge, the area You Liaoyiceng N+.?
Hole P and free electron number N in the area N+, meet i2The rule of=P*N, i is in the monocrystalline silicon formed due to temperature in formula
Intrinsic excitation, GPP rectification chip be in 150 DEG C when, i is about 1013cm-3Phosphorus diffusion area concentration 10 is compared in left and right21cm-3It is left
The right side, low 8 several magnitudes, so can only diffuse into and exhaust with the presence of minimal amount of hole, hole in the area G Chu N+
The quantity in area is greatly reduced, and reversed high-temperature current leakage is reduced in the order of magnitude, and the reversed hot properties of product has just obtained very big
It is promoted.
Second of aligning method with I at the crosslinking of adjacent two GPP rectification chips in chip layout design scheme be
Line forms symmetrical double laser hole in two side of middle line, as shown in Fig. 5.
GPP rectification chip has position deviation when with mechanical cutting at the crosslinking I along adjacent two chips, by the area N+
It cuts partially；For GPP rectification chip in rear road packaging technology, the geometry that certain pollution and thermal stress can be also formed to blocking district is deep
Degree, when stressed zone depth is more than N+ sector width, will affect design effect of the invention.So using second of arrangement scheme,
The area N+ is broadened with double laser hole.
The surface diameter Φ in hole is 15~30 microns, and the depth H in hole is that monocrystalline silicon piece thickness A subtracts 50~150 microns, together
Adjacent dual-laser hole center is arranged away from being 80~140 microns, symmetrical two rows laser hole center is 50~400 microns away from L.Monocrystalline silicon piece
After high temperature Double side diffusion phosphorus and boron (or boron aluminium), at the crosslinking I of adjacent two chips, form as shown in Fig. 5
Three areas N+.Obvious, double-row hole center is wider away from L, prevents the ability of mechanical cutting deviation stronger, while road encapsulates after reduction
The pollution of technique and the ability of thermal stress are also stronger, but excessively widen two hole centers away from L, will affect the utilization of monocrystalline silicon piece material
Rate.
Two, the present invention is as follows for the principle of thyristor chip manufacture：
The present invention is before circle N- monocrystalline silicon piece has spread P-, do not expanded phosphorus, on the cathode plane surface that phosphorus is expanded in plan, according to core
Two of chip layout are pressure-resistant, and angle design scheme is burnt blend-out a series of in straight with blanking disc control laser beam on monocrystalline silicon piece
The similar taper half bore of line arrangement, the open end in hole on the surface for planning cathode of monocrystalline silicon piece, can it is rounded, class is oval
Shape or strip, the finish no requirement (NR) of the taper and hole wall in hole.
Design scheme according to chip two pressure-resistant angles is different, there is following three kinds of laser hole location schemes：
1, the thyristor chip just negative angle shaped for single side, monocrystalline silicon piece cross-section structure such as attached drawing 9, along placement scheme
In positive negative angle crosslinking at I aperture, the overall diameter Φ in hole is 15~30 microns, and the depth H in hole is the 1/ of monocrystalline silicon piece thickness A
3~2/5, it is 70~190 microns.
After phosphorus diffusion, it is formed by around similar taper half bore, is formd as of fig. 9 shown in laser stereo lithography
The area N+.After road angulation process later, the surface at positive negative angle crosslinking I leaves certain N+ layer.Product adds forward voltage
Afterwards, equipotential lines chain-dotted line as shown in Fig. 9 upwarps, anode along surface by diffusion come hole blocked by this N+ layers,
It not can enter depletion region and form forward current, the forward characteristic of product is promoted.The tip of similar taper half bore stays in product
Surface has no effect on product characteristic due to N+ layers of protection.
2, negative angle shaped thyristor chips double for single side, monocrystalline silicon piece cross-section structure such as attached drawing 10, along layout side
Middle line I aperture at the crosslinking of double negative angles in case, the overall diameter Φ in hole are 15~30 microns, and the depth H in hole is that monocrystalline silicon piece is thick
The 1/3~2/5 of A is spent, is 70~200 microns.
After phosphorus diffusion, it is formed by around similar taper half bore, is formd as shown in Fig. 10 in laser stereo lithography
The area N+.After road angulation process later, the surface at double negative angles crosslinking I leaves certain N+ layer, and product is plus positive electricity
After pressure, equipotential lines chain-dotted line as shown in Fig. 10 is upwarped, anode along surface by spread come hole blocked by this N+ layers, no
It can enter depletion region and form forward current, the forward characteristic of product is promoted.
3, for two-sided double negative angle shaped thyristor chips, laser stereo lithography is formed by similar taper half bore, there is two kinds
Aligning method：
Method one, monocrystalline silicon piece cross-section structure such as attached drawing 11, along middle line at two chip crosslinkings adjacent in placement scheme
Place I forms single laser hole, and the overall diameter Φ in hole is 15~30 microns, and the depth H in hole is the 1/2~3/ of monocrystalline silicon piece thickness A
5, it is 110~280 microns.
Method two, monocrystalline silicon piece cross-section structure such as attached drawing 12, it is contemplated that at the crosslinking I of adjacent two chips, cut with machinery
Position deviation is had when disconnected, and the crosslinking area I Chu N+ is cut partially；Chip, also can be certain to will form at crosslinking I in postchannel process
Pollution and stress, all will affect design effect of the invention.So using second of aligning method, with double laser hole by N+
Area's broadening., as middle line, to be formed in two side of middle line symmetrical double at adjacent two chip crosslinkings in chip layout design scheme
Round, the overall diameter Φ in hole are 15~30 microns, and the depth H in hole is the 1/2~3/5 of monocrystalline silicon piece thickness A, are 110~280 micro-
Rice, symmetrical double laser hole center are 50~300 microns away from L.
After phosphorus diffusion, it is formed by around similar taper half bore, is formd such as attached drawing 11, attached drawing in laser stereo lithography
The area N+ shown in 12.After road angulation process later, the surface at double negative angles crosslinking I leaves certain N+ layer, product adds
After forward voltage, equipotential lines chain-dotted line as shown in attached drawing 11, attached drawing 12 is upwarped, anode along surface by diffusion come it is aerial
Cave is blocked by this N+ layers, not can enter depletion region and is formed forward current, the forward characteristic of product is promoted.
The above-mentioned leakage current to three kinds of different surfaces angle moulding of thyristor chip is analyzed, and is based on product and forward voltage is added to produce
The case where raw forward leakage current.Above-mentioned analysis is equally applicable to the thyristor chip of three kinds of different surfaces angle moulding, in addition anode
It is negative, the backward voltage situation that cathode is positive, the area N+ of the generation as attached by the present invention also blocks the area cathode P- and passes through table
To the hole stream of anode, the reverse characteristic of product equally promoted surface current.
Detailed description of the invention
Fig. 1, GPP rectification chip sectional structure chart described in background technology.In figure, A is chip thickness；B is N-type base area
Width is designated as the area N- on figure；C is p type diffusion region width, and wherein D is P- sector width, is designated as the area P+ and P- on figure；E is N-type expansion
Sector width is dissipated, is designated as the area N+ on figure；W is etching groove depth；F is the area chip P plane etching groove width；G is chip edge
Mechanical cutoff area；S is glass passivation protection area, and figure chain lines are the equipotential lines in depletion layer.
Fig. 2, adjacent two GPP rectification chip sectional structure chart in the first of the invention scheme.In figure, A is that chip is thick
Degree；H is hole depth, H=A- (50~150) micron；I be placement scheme in adjacent two GPP rectification chips crosslinking in
Line, Φ are 15~30 microns of overall diameter of hole.
Fig. 3, the GPP rectification chip plane structure chart in the first of the invention scheme.In figure, Δ is in adjacent dual-laser hole
The heart is away from 80~140 microns；S is monocrystalline silicon piece material；K is the GPP rectification chip in chip layout design scheme.
Fig. 4, the GPP rectification chip sectional structure chart in the first of the invention scheme.In figure, A is chip thickness；B is N-type
Base width is designated as the area N- on figure；C is p type diffusion region width, and wherein D is P- sector width, is designated as the area P+ and P- on figure；E is N
Type spreads sector width, is designated as the area N+ on figure；W is etching groove depth；F is the area chip P plane etching groove width；G is chip
The mechanical cutoff area at edge；S is glass passivation protection area, and figure chain lines are the equipotential lines in depletion layer.It is different from Fig. 1
It is：At the mechanical cutoff area G of chip edge, the area You Liaoyiceng N+.
Fig. 5, adjacent two GPP rectification chip sectional structure chart in second scheme of the present invention.In figure, L is parallel phase
Adjacent two row's laser hole centers are away from 50~400 microns.Unlike Fig. 2：The centre of parallel adjacent two rows laser hole, more one
Locate the area N+.
Fig. 6, the just negative angle shaped sectional structure chart of thyristor chip single side described in background technique.In figure, A is that chip is thick
Degree；B is N-type base width, is designated as the area N- on figure；C is p type diffusion region width, and wherein D is P- sector width, be designated as on figure P+ and
The area P-, the area P+ surface are the anodes of chip；E is that N-type spreads sector width, is designated as the area N+ on figure, surface is the cathode of chip；Just
Width shared by minus two jiaos is F；G is positive angular region；W is negative angular region；S is insulation protection area；Arrow show the dispersal direction in hole.
Fig. 7, the two-sided double negative angle shaped sectional structure charts of thyristor chip described in background technique.In figure, A is that chip is thick
Degree；B is N-type base width, is designated as the area N- on figure；C is p type diffusion region width, and wherein D is P- sector width, be designated as on figure P+ and
The area P-, the area P+ surface are the anodes of chip；E is that N-type spreads sector width, is designated as the area N+ on figure, surface is the cathode of chip；It is negative
Width shared by angle is F；G is anode negative angle area；W is cathode negative angle area；S is insulation protection area；Arrow show the diffusion in hole
Direction.
Fig. 8, the double negative angle shaped sectional structure charts of thyristor chip single side described in background technique.In figure, A is that chip is thick
Degree；B is N-type base width, is designated as the area N- on figure；C is p type diffusion region width, and wherein D is P- sector width, be designated as on figure P+ and
The area P-, the area P+ surface are the anodes of chip；E is that N-type spreads sector width, is designated as the area N+ on figure, surface is the cathode of chip；It is negative
Width shared by angle is F；G is anode negative angle area；W is cathode negative angle area；S is insulation protection area；Arrow show the diffusion in hole
Direction.
Fig. 9, the just negative angle shaped thyristor chip of single side of the present invention, monocrystalline silicon piece sectional structure chart.I is in placement scheme
Middle line at positive and negative angle crosslinking, Φ are 15~30 microns of overall diameter of laser hole, and A is monocrystalline silicon piece thickness, and H is the depth in hole, H
=(1/3~2/5) * A is 70~200 microns.
Figure 10, the double negative angle shaped thyristor chips of single side of the present invention, monocrystalline silicon piece sectional structure chart.I is placement scheme
In middle line at double negative angle crosslinkings, positive Φ is 15~30 microns of overall diameter of laser hole, and A is monocrystalline silicon piece thickness, and H is the depth in hole
Degree, H=(1/3~2/5) * A are 70~200 microns.
Figure 11, the two-sided double negative angle shaped single laser hole schemes of thyristor chip of the present invention, monocrystalline silicon piece cross-section structure
Figure.I is middle line at the crosslinking of adjacent two chips in placement scheme, and Φ is 15~30 microns of overall diameter of laser hole, and A is single
Crystal silicon chip thickness, H are the depth in hole, and H=(1/2~3/5) * A is 110~300 microns.
Figure 12, the two-sided double negative angle shaped double laser hole schemes of thyristor chip of the present invention, monocrystalline silicon piece cross-section structure
Figure.I is middle line at the crosslinking of adjacent two chips in placement scheme, and 15~30 microns of the overall diameter of laser hole, A is monocrystalline silicon piece
Thickness, H be hole depth, H=(1/2~3/5) * A, be 110~300 microns, L be symmetrical two rows laser hole center away from, be 50
~300 microns.
Figure 13, blanking disc plan view when laser stereo lithography of the present invention.In figure, (aluminium is stainless with common metal for blanking disc
Steel) thin plate production, with a thickness of 0.5~3mm；N is shading disk diameter, is 160~200mm；R is shading disk center into laser beam
Heart distance is 70~80mm；Z is light transmission hole length, is 10~20mm；X is loophole angle；Y is non-transparent hole angle, and M is
High-speed motor mounting hole.
Specific embodiment
Implementation technical difficulty of the invention be at high speed, accurately by laser beam in monocrystalline silicon sheet surface by design scheme
Burn blend-out similar taper half bore.Two kinds of embodiments can be used：
Mode one：Will similar taper half bore arrangement design scheme, be incorporated into laser machine control program, when board (or light
Beam) in when needing half hole site of taper, sending laser beam burns blend-out half bore on monocrystalline silicon piece；When board (or light beam) is in not
When needing half hole site of taper, closes laser beam and do not punch.Adjustment laser machine controls program repeatedly, makes the items of similar taper half bore
Geometric dimension requires to meet the principle of the invention and the parameter area.
Mode two：Using common laser wafer cutting machine, a blanking disc, blanking disc are set on the path of laser beam
It is made of common metal thin plate, planar structure is as shown in Fig. 12, with a thickness of 0.5~3mm, is centrally mounted at high-speed motor
On (3000~5000 revs/min), blanking disc is between laser generator and monocrystalline silicon piece, disk plane perpendicular to laser beam and
Not on laser depth of focus, so laser is not damaged to blanking disc.Shading disk diameter N is 160~300mm, and shading disk center is to sharp
Beam center distance R is 70~100mm.Loophole is provided in blanking disc plane, light transmission hole length Z is 10~20mm, loophole
Angle X and non-transparent hole angle Y, which are equal on monocrystalline silicon piece, hole and the distance between non-porous ratio, the quantity and high speed electricity of loophole
The product of machine revolving speed is equal to the laser stereo lithography hole count in the unit time.The power for adjusting laser machine output, by similar bellmouth
It is deep-controlled in Suitable depth range of the present invention.
According to the supplemental characteristic in this specification, the superior GPP rectification chip of hot properties and thyristor have been produced
Chip, production acceptance rate and rear road encapsulation yield rate are all greatly improved.The present invention only increases laser stereo lithography work
Sequence has many advantages, such as no investment risk, industrialization level height, simple process.Using the principle of the invention, have adjusted in the present invention
Other technical solutions of relative dimensions parameter, also belong to the scope of the invention certainly.
Claims (9)
1. a kind of laser stereo lithography GPP rectification chip, structure feature are：The rectification chip, refer to circular single crystal silicon wafer not
Before diffuseing to form PN junction, on the surface that phosphorus is expanded in plan, along the crosslinking of adjacent two GPP rectification chips in placement scheme
Place controls laser beam with blanking disc, blend-out a succession of similar taper half bore being arranged in a linear is burnt on monocrystalline silicon piece, hole is opened
Mouthful end on the surface of monocrystalline silicon piece, can rounded, class is oval or strip, the finish of the taper in hole and hole wall is without wanting
It asks.
2. similar taper half bore according to claim 1, the structure feature of the first aligning method are：Along chip cloth
Single row of holes is formed at the crosslinking of adjacent two GPP rectification chips in office's design scheme, the surface diameter in hole is 15~30 microns,
The depth in hole is that monocrystalline silicon piece thickness subtracts 50~150 microns, and adjacent dual-laser hole center is away from being 80~140 microns.
3. similar taper half bore according to claim 1, the structure feature of second of aligning method are：With chip layout
It is middle line at the crosslinking of adjacent two GPP rectification chips in design scheme, forms symmetrical double-row hole in two side of middle line, hole
Surface diameter is 15~30 microns, and the depth in hole is that monocrystalline silicon piece thickness subtracts 50~150 microns, with row in adjacent dual-laser hole
The heart is away from being 80~140 microns, and symmetrical double laser hole center is away from being 50~400 microns.
4. a kind of laser stereo lithography thyristor chip, structure feature are：The thyristor chip refers in circle N- monocrystalline silicon piece
Before having spread P-, not expanded phosphorus, on the cathode plane surface that phosphorus is expanded in plan, laser beam is controlled with blanking disc, is burnt on monocrystalline silicon piece
The blend-out a series of similar taper half bore being arranged in a linear, the open end in hole, can be in circles on the surface of monocrystalline silicon piece
Shape, class ellipse or strip, the finish no requirement (NR) of the taper and hole wall in hole.
5. similar taper half bore according to claim 4, special for the structure of the just negative angle shaped thyristor chip of single side
Sign is：Along middle line aperture at the crosslinking of the positive negative angle in placement scheme, the surface diameter in hole is 15~30 microns, the depth in hole
Degree is 70~190 microns.
6. the structure of similar taper half bore according to claim 4, negative angle shaped thyristor chips double for single side is special
Sign is：Along middle line aperture at the crosslinking of double negative angles in placement scheme, the surface diameter in hole is 15~30 microns, the depth in hole
Degree is 70~200 microns.
7. similar taper half bore according to claim 4, the structure of the thyristor chips negative angle shaped for two-sided pair, the
A kind of aligning method is characterized in that：Single row of holes, the table in hole are formed along middle line at two chip crosslinkings adjacent in placement scheme
Face diameter is 15~30 microns, and the depth in hole is 110~280 microns.
8. similar taper half bore according to claim 4, the structure of the thyristor chips negative angle shaped for two-sided pair, the
Two kinds of aligning methods are characterized in that：Using at adjacent two chip crosslinkings in chip layout design scheme as middle line, in middle line
Two sides form symmetrical double-row hole, and the surface diameter in hole is 15~30 microns, and the depth in hole is 110~280 microns, symmetrical double
Laser hole center is away from being 50~300 microns.
9. according to claim 1, blanking disc as claimed in claim 4, structure feature are：Blanking disc common metal thin plate
Production, with a thickness of 0.5~3mm, disk center is mounted on high-speed motor, blanking disc be in laser generator and monocrystalline silicon piece it
Between, for disk plane perpendicular to laser beam, shading disk diameter is 160~300mm, shading disk center to laser beam centre distance for 70~
100mm；Loophole is provided in blanking disc plane, light transmission hole length is 10~20mm, loophole angle and non-transparent hole angle etc.
In having hole and the distance between non-porous ratio on monocrystalline silicon piece, when the quantity of loophole and the product of high-speed motor revolving speed are equal to unit
Interior laser stereo lithography hole count.
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| CN201710429684.0A CN108933164A (en) | 2017-05-25 | 2017-05-25 | Laser stereo lithography high-power semiconductor device chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109509794A (en) * | 2018-12-08 | 2019-03-22 | 程德明 | The P+-I-N+ type power diode of N+ area edge arc-shaped structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1783511A (en) * | 2004-11-30 | 2006-06-07 | 安徽省祁门县黄山电器有限责任公司 | Thyrister, chip special for producing thyrister and its producing method |
| CN1783516A (en) * | 2004-11-30 | 2006-06-07 | 安徽省祁门县黄山电器有限责任公司 | Rectifier diode, chip special for producing rectifier diode and producing method |
| US20110281406A1 (en) * | 2010-05-17 | 2011-11-17 | Fuji Electric Co., Ltd. | Semiconductor device manufacturing method |
| CN205385026U (en) * | 2016-01-15 | 2016-07-13 | 上海瞬雷电子科技有限公司 | Two -way discharge tube chip |
| CN208157415U (en) * | 2017-05-25 | 2018-11-27 | 程德明 | Laser stereo lithography high-power semiconductor device chip |
-
2017
- 2017-05-25 CN CN201710429684.0A patent/CN108933164A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1783511A (en) * | 2004-11-30 | 2006-06-07 | 安徽省祁门县黄山电器有限责任公司 | Thyrister, chip special for producing thyrister and its producing method |
| CN1783516A (en) * | 2004-11-30 | 2006-06-07 | 安徽省祁门县黄山电器有限责任公司 | Rectifier diode, chip special for producing rectifier diode and producing method |
| US20110281406A1 (en) * | 2010-05-17 | 2011-11-17 | Fuji Electric Co., Ltd. | Semiconductor device manufacturing method |
| CN205385026U (en) * | 2016-01-15 | 2016-07-13 | 上海瞬雷电子科技有限公司 | Two -way discharge tube chip |
| CN208157415U (en) * | 2017-05-25 | 2018-11-27 | 程德明 | Laser stereo lithography high-power semiconductor device chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109509794A (en) * | 2018-12-08 | 2019-03-22 | 程德明 | The P+-I-N+ type power diode of N+ area edge arc-shaped structure |
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