CN110098254A - Utilize the single table surface high-voltage thyristor chip and manufacturing method of the two-way scribing of symmetry - Google Patents
Utilize the single table surface high-voltage thyristor chip and manufacturing method of the two-way scribing of symmetry Download PDFInfo
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- CN110098254A CN110098254A CN201910360164.8A CN201910360164A CN110098254A CN 110098254 A CN110098254 A CN 110098254A CN 201910360164 A CN201910360164 A CN 201910360164A CN 110098254 A CN110098254 A CN 110098254A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 61
- 239000010703 silicon Substances 0.000 claims abstract description 61
- 238000002955 isolation Methods 0.000 claims abstract description 46
- 238000001259 photo etching Methods 0.000 claims abstract description 32
- 238000009792 diffusion process Methods 0.000 claims abstract description 30
- 230000009849 deactivation Effects 0.000 claims abstract description 24
- 238000002347 injection Methods 0.000 claims abstract description 12
- 239000007924 injection Substances 0.000 claims abstract description 12
- 239000004411 aluminium Substances 0.000 claims abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000956 alloy Substances 0.000 claims abstract description 7
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 7
- 229910052796 boron Inorganic materials 0.000 claims abstract description 7
- 238000001704 evaporation Methods 0.000 claims abstract description 7
- 230000008020 evaporation Effects 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 7
- 239000011574 phosphorus Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 21
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 18
- 238000002513 implantation Methods 0.000 claims description 18
- 239000007788 liquid Substances 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 239000003292 glue Substances 0.000 claims description 12
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 239000000243 solution Substances 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 4
- 238000003908 quality control method Methods 0.000 claims description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 3
- 241001673391 Entandrophragma candollei Species 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 claims description 3
- 239000011230 binding agent Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 238000001816 cooling Methods 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 3
- 229910001882 dioxygen Inorganic materials 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 3
- 239000000843 powder Substances 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000004857 zone melting Methods 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- 238000007689 inspection Methods 0.000 abstract 1
- 238000003466 welding Methods 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66386—Bidirectional thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66393—Lateral or planar thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7424—Thyristor-type devices, e.g. having four-zone regenerative action having a built-in localised breakdown/breakover region, e.g. self-protected against destructive spontaneous, e.g. voltage breakover, firing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/747—Bidirectional devices, e.g. triacs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
The invention discloses a kind of single table surface high-voltage thyristor chips using the two-way scribing of symmetry, it links into an integrated entity including the N-type growing base area short base area of positive p-type with N+ type emitter region, the back side base area PXing Duan at the N-type growing base area back side is connected to logical isolation ring with the short base area of positive p-type by p-type.Manufacturing method: silicon wafer inspection, growth oxidation film, photoetching isolation window, isolation scribing, two-sided injection aluminium, isolation diffusion, two-sided injection boron, two-sided injection aluminium, the short base area diffusion of p-type, photoetching emitter region, emitter region phosphorus diffusion, photoetching deactivation slot, the protection of deactivation slot burn into deactivation slot, photoetching lead district, two-sided evaporation electrode, photoetching anti-carve area, alloy, test, cutting-up.Because flash leads to the voltage Problem of Failure of production tube when the present invention solves solder(ing) paste welding；It solves because production tube inner air breakdown problem not exclusively occurs in resin filling；It solves the problems such as divergence occurred due to using sheet, uncontrolled, improves production efficiency and yields.
Description
Technical field
The present invention relates to technology of semiconductor chips field more particularly to a kind of single table surface using the two-way scribing of symmetry are high
Press controlled silicon chip and manufacturing method.
Background technique
At this stage in silicon-controlled technical field, high-voltage thyristor is typically prepared into two kinds of cores because of the requirement of its breakdown voltage
Chip architecture:
(1) double mesa structures are prepared into.The general sheet for using 400-430um, if the silicon single crystal of this thickness is prepared into single table surface
Structure then exists slow to logical isolation crossed loops diffuser efficiency and cannot be connected, and forms angle to logical isolation ring and mesa trench
Spend a series of problems, such as uncontrolled.And there is also certain risks when being encapsulated as production tube for the chip of this double mesa structures:
When chip back and copper soleplate frame are welded with solder(ing) paste, after solder(ing) paste flash, be laid on the table top of chip back, cause finally at
The voltage of quality control fails, and causes economic loss；The radian of chip table groove and the mismatch of copper soleplate frame, lead to ring type filling
When oxygen insulation resin is protected, it cannot be filled up completely at chip table groove, it may appear that the inside of production tube in application process
Air breakdown and fail, cause economic loss.
(2) it is prepared into planar structure.Although this chip structure overcomes as dual stage face fabric chip is being encapsulated as production tube
When a series of problems, but the sheet for similarly using 400-430um because of it, however it remains to logical isolation crossed loops diffuser efficiency
Slowly a series of problems, such as and cannot being connected.At this stage offshore company because its equipment advance, accuracy and controllability, therefore make
For at such planar structure；But domestic corporation, because of the limitation of its equipment, if being prepared into such chip structure, it will cause good
Phenomena such as rate is low, increased costs.
Summary of the invention
To solve drawbacks described above, the present invention provides a kind of single table surface high-voltage thyristor chip using the two-way scribing of symmetry
And manufacturing method.
The technical scheme is that a kind of single table surface high-voltage thyristor chip using the two-way scribing of symmetry, including
Anode electrode A, the back side base area PXing Duan, p-type are to logical isolation ring, gate electrode G, N-type growing base area, the short base area of positive p-type, N+ type
In positive oxidation film, the short base area setting of front p-type is long in N-type for emitter region, cathode electrode K, isolation deactivation slot and setting
Base area front, and link into an integrated entity with N+ type emitter region, positive electricity is formed between the N-type growing base area and the short base area of positive p-type
PN junction is pressed, in the short base area top surface of positive p-type, the cathode electrode K is arranged on N+ type emitter region top for the gate electrode G setting
Face；Shape is arranged between the N-type growing base area back side, the N-type growing base area and the back side base area PXing Duan in the base area the back side PXing Duan
At backward voltage PN junction, the base area back side PXing Duan top surface is equipped with anode electrode A；The base area the back side PXing Duan passes through p-type pair
Logical isolation ring is connected with the short base area of positive p-type, and the front short base area of p-type is surrounded by cricoid isolation deactivation slot.
Further, width of the p-type to logical isolation ring are as follows: 150-200 um.
Further, the ditch groove deep of the isolation deactivation slot: 130-150 um.
Further, the junction depth of the forward voltage PN junction and backward voltage PN junction are as follows: 80-95 um.
A kind of manufacturing method of the single table surface high-voltage thyristor chip using the two-way scribing of symmetry, which is characterized in that packet
Include following steps:
(1) silicon wafer Incoming Quality Control: selection resistivity is 50-70 Ω cm, edge<111>the direction growth of thickness 350-450um
Pulling of crystals or zone melting single-crystal；
(2) grow oxidation film: high temperature wet oxygen method growth thickness is greater than the oxide layer of 1um；
(3) photoetching isolation window: in silicon wafer dual coating photoresist, through exposure and development, after post bake, using the removal of BOE corrosive liquid every
From the oxide layer in window, sulfuric acid removes the photoresist of surface residual；
(4) two-sided isolation scribing: utilizing grinding wheel cutting-up equipment, carries out cutting-up, depth 60- at two-sided isolation ring in advance
90um；
(5) two-sided injection aluminium: the silicon source in ion implantation apparatus injects silicon chip surface, Implantation Energy 120- after accelerating by high pressure
150KeV, implantation dosage 2.5-4E15/cm 2；
(6) isolation diffusion: 1200-1300 DEG C of diffusion temperature, diffusion time 10-15 hour is passed through nitrogen and oxygen is protected,
Nitrogen flow 2-6L/min, oxygen flow 0.2-0.6L/min；Heating rate be 3-5 DEG C/min, rate of temperature fall be 1-3 DEG C/
Min, it is uncrossed 50um to just intersecting that the isolation of formation, which intersects ring width,；
(7) two-sided injection boron: Implantation Energy 40-80KeV, implantation dosage 0.5-1.5E15/cm 2；
(8) two-sided injection aluminium: Implantation Energy 120-150KeV, implantation dosage 1-2E15/cm 2；
(9) the short base area diffusion of p-type: 1200-1300 DEG C of diffusion temperature, diffusion time 15-20 hour；Diffusion atmosphere: nitrogen and oxygen
Gas ratio 10:1, wherein nitrogen flow 2-6L/min, oxygen flow 0.2-0.6L/min, 3-5 DEG C of heating rate/min, cooling are fast
1-3 DEG C of rate/min forms the short base area of positive p-type and the back side base area PXing Duan, wherein the junction depth of boron is 35-45um, the junction depth of aluminium
For 80-95um, isolation ring width is 150-200um；
(10) photoetching emitter region: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and the oxide layer in BOE corrosive liquid removal emitter region is recycled, and sulfuric acid removes the photoresist of surface residual；
(11) it emitter region phosphorus diffusion: is spread using phosphorus oxychloride (POCl3) liquid source, 1050-1150 DEG C of pre-expansion temperature, when pre-expansion
Between 60-90 minutes, 15-20 DEG C of source temperature, phosphorus expands 1150-1200 DEG C of temperature again, time 4-5 hour, and R is 0.5-1.5 Ω/,
Diffusion junction depth is 10-25um, forms front N+ type emitter region；
(12) photoetching deactivation slot: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and the oxide layer in BOE corrosive liquid removal deactivation slot is recycled；
(13) it is passivated groove corrosion: using silicon etch solution erosion grooves, ditch groove deep: 130-150um；
(14) deactivation slot is protected: one layer of Sipos protective film is grown with LPCVD method corroding in deactivation slot out, with a thickness of 9000-
11000A is subsequently filled the glass paste stirred into glass powder and binder by 1.4-2:1 and is uniformly applied to front side of silicon wafer, passes through
It is sintered at high temperature into glass, then grows one layer of LTO film with LPCVD method and covers silicon chip surface, with a thickness of 3000-6000A；
(15) photoetching lead district: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and BOE corrosive liquid and silicon etch solution is recycled successively to remove the LTO-Sipos-SiO2 in lead district, sulfuric acid removal
The photoresist of surface residual；
(16) two-sided evaporation electrode: titanium-nickel-silver is evaporated respectively at the positive back side of silicon wafer, titanium evaporates thickness requirement 1200-1600A, nickel
Thickness requirement 4500-5500A is evaporated, silver evaporation thickness requirement 4500-5500A forms gate electrode G, cathode electrode K and anode
Electrode A；
(17) photoetching anti-carves area: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and the removal of metal erosion liquid is recycled to anti-carve unwanted metal layer in area, and stripper removes the light of surface residual
Photoresist；
(18) alloy: vacuum alloy reinforces the binding force of metal and silicon；
(19) it tests: requiring to be tested according to chip parameter；
(20) cutting-up: silicon wafer cutting-up is at chip disconnected from each other.
Beneficial effects of the present invention: when 1) being welded there is no chip back and copper soleplate frame with solder(ing) paste, because of solder(ing) paste
Flash and cause the voltage of production tube to fail, so as to avoid economic loss；2) when being protected there is no filling epoxy resins insulation,
Occurs the inner air breakdown of production tube in application process because that cannot be filled up completely at chip table groove, to avoid
Economic loss；3) thoroughly solve occur due to using sheet it is slow to logical isolation crossed loops diffuser efficiency with cannot be connected,
And a series of problems, such as angle is uncontrolled is formed to logical isolation ring and mesa trench, to improve production efficiency and non-defective unit
Rate.
Detailed description of the invention
Fig. 1 is longitudinal schematic cross-sectional view of the chip in background technique.
Fig. 2 is longitudinal schematic cross-sectional view of the chip in background technique.
Fig. 3 is longitudinal schematic cross-sectional view of chip in the present invention.
Wherein: 1, gate electrode G, 2, cathode electrode K, 3, isolation deactivation slot, 4, anode electrode A, 5, the short base of positive p-type
Area, 6, N-type growing base area, 7, the back side base area PXing Duan, 8, p-type to logical isolation ring, 9, N+ type emitter region, 10, oxidation film, 11, anti-
To voltage PN junction, 12, forward voltage PN junction, 13, p-type pressurized ring.
Specific embodiment
The present invention is further described with reference to the accompanying drawing, be described below in be only the present invention in record it is attached
Figure, without any creative labor, can also be attached according to these for those skilled in the art
Figure obtains other attached drawings.
As shown in figure 3, a kind of single table surface high-voltage thyristor chip using the two-way scribing of symmetry, including anode electrode
A4, the back side base area PXing Duan 7, p-type send out logical isolation ring 8, gate electrode G1, N-type growing base area 6, the short base area 5 of positive p-type, N+ type
Area 9, cathode electrode K2, isolation deactivation slot 3 and setting are penetrated in positive oxidation film 10, the positive short setting of base area 5 of p-type is long in N-type
6 front of base area, and link into an integrated entity with N+ type emitter region 9, positive electricity is formed between N-type growing base area 6 and the short base area 5 of positive p-type
PN junction 12 is pressed, gate electrode G1 setting is arranged in short 5 top surface of base area of positive p-type, cathode electrode K2 in 9 top surface of N+ type emitter region；
The back side base area PXing Duan 7, which is arranged between 6 back side of N-type growing base area, N-type growing base area 6 and the back side base area PXing Duan 7, forms reversed electricity
PN junction 11 is pressed, 7 top surface of the back side base area PXing Duan is equipped with anode electrode A4；The back side base area PXing Duan 7 by p-type to logical isolation ring 8 with
The positive short base area 5 of p-type is connected, and the positive short base area 5 of p-type is surrounded by cricoid isolation deactivation slot 3.
P-type is 150-200 um to the width of logical isolation ring 8.The ditch groove deep of deactivation slot 3: 130-150um is isolated.It is positive
The junction depth of voltage PN junction 12 and backward voltage PN junction 11 is 80-95um.
A kind of manufacturing method of the single table surface high-voltage thyristor chip using the two-way scribing of symmetry, comprising the following steps:
(1) silicon wafer Incoming Quality Control: selection resistivity is 50-70 Ω cm, edge<111>the direction growth of thickness 350-450um
Pulling of crystals or zone melting single-crystal；
(2) grow oxidation film: high temperature wet oxygen method growth thickness is greater than the oxide layer of 1um；
(3) photoetching isolation window: in silicon wafer dual coating photoresist, through exposure and development, after post bake, using the removal of BOE corrosive liquid every
From the oxide layer in window, sulfuric acid removes the photoresist of surface residual；
(4) two-sided isolation scribing: utilizing grinding wheel cutting-up equipment, carries out cutting-up, depth 60- at two-sided isolation ring in advance
90um；
(5) two-sided injection aluminium: the silicon source in ion implantation apparatus injects silicon chip surface, Implantation Energy 120- after accelerating by high pressure
150KeV, implantation dosage 2.5-4E15/cm 2；
(6) isolation diffusion: 1200-1300 DEG C of diffusion temperature, diffusion time 10-15 hour is passed through nitrogen and oxygen is protected,
Nitrogen flow 2-6L/min, oxygen flow 0.2-0.6L/min；Heating rate be 3-5 DEG C/min, rate of temperature fall be 1-3 DEG C/
Min, it is uncrossed 50um to just intersecting that the isolation of formation, which intersects ring width,；
(7) two-sided injection boron: Implantation Energy 40-80KeV, implantation dosage 0.5-1.5E15/cm 2；
(8) two-sided injection aluminium: Implantation Energy 120-150KeV, implantation dosage 1-2E15/cm 2；
(9) the short base area diffusion of p-type: 1200-1300 DEG C of diffusion temperature, diffusion time 15-20 hour；Diffusion atmosphere: nitrogen and oxygen
Gas ratio 10:1, wherein nitrogen flow 2-6L/min, oxygen flow 0.2-0.6L/min, 3-5 DEG C of heating rate/min, cooling are fast
1-3 DEG C of rate/min forms the short base area of positive p-type and the back side base area PXing Duan, wherein the junction depth of boron is 35-45um, the junction depth of aluminium
For 80-95um, isolation ring width is 150-200um；
(10) photoetching emitter region: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and the oxide layer in BOE corrosive liquid removal emitter region is recycled, and sulfuric acid removes the photoresist of surface residual；
(11) it emitter region phosphorus diffusion: is spread using phosphorus oxychloride (POCl3) liquid source, 1050-1150 DEG C of pre-expansion temperature, when pre-expansion
Between 60-90 minutes, 15-20 DEG C of source temperature, phosphorus expands 1150-1200 DEG C of temperature again, time 4-5 hour, and R is 0.5-1.5 Ω/,
Diffusion junction depth is 10-25um, forms front N+ type emitter region；
(12) photoetching deactivation slot: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and the oxide layer in BOE corrosive liquid removal deactivation slot is recycled；
(13) it is passivated groove corrosion: using silicon etch solution erosion grooves, ditch groove deep: 130-150um；
(14) deactivation slot is protected: one layer of Sipos protective film is grown with LPCVD method corroding in deactivation slot out, with a thickness of 9000-
11000A is subsequently filled the glass paste stirred into glass powder and binder by 1.4-2:1 and is uniformly applied to front side of silicon wafer, passes through
It is sintered at high temperature into glass, then grows one layer of LTO film with LPCVD method and covers silicon chip surface, with a thickness of 3000-6000A；
(15) photoetching lead district: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and BOE corrosive liquid and silicon etch solution is recycled successively to remove the LTO-Sipos-SiO2 in lead district, sulfuric acid removal
The photoresist of surface residual；
(16) two-sided evaporation electrode: titanium-nickel-silver is evaporated respectively at the positive back side of silicon wafer, titanium evaporates thickness requirement 1200-1600A, nickel
Thickness requirement 4500-5500A is evaporated, silver evaporation thickness requirement 4500-5500A forms gate electrode G, cathode electrode K and anode
Electrode A；
(17) photoetching anti-carves area: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and the removal of metal erosion liquid is recycled to anti-carve unwanted metal layer in area, and stripper removes the light of surface residual
Photoresist；
(18) alloy: vacuum alloy reinforces the binding force of metal and silicon；
(19) it tests: requiring to be tested according to chip parameter；
(20) cutting-up: silicon wafer cutting-up is at chip disconnected from each other.
Claims (5)
1. using the single table surface high-voltage thyristor chip of the two-way scribing of symmetry, including anode electrode A, the back side base area PXing Duan, P
Type is passivated logical isolation ring, gate electrode G, N-type growing base area, the short base area of positive p-type, N+ type emitter region, cathode electrode K, isolation
Slot and setting are in positive oxidation film, it is characterised in that: the short base area setting of front p-type is positive in N-type growing base area, and and N
+ type emitter region links into an integrated entity, and forms forward voltage PN junction, the door between the N-type growing base area and the short base area of positive p-type
Electrode G setting in pole is arranged in the short base area top surface of positive p-type, the cathode electrode K in N+ type emitter region top surface；The back side p-type
Short base area, which is arranged between the N-type growing base area back side, the N-type growing base area and the back side base area PXing Duan, forms backward voltage PN junction,
The base area back side PXing Duan top surface is equipped with anode electrode A；The base area the back side PXing Duan is by p-type to logical isolation ring and front P
The short base area of type is connected, and the front short base area of p-type is surrounded by cricoid isolation deactivation slot.
2. the single table surface high-voltage thyristor chip according to claim 1 using the two-way scribing of symmetry, it is characterised in that:
Width of the p-type to logical isolation ring are as follows: 150-200 um.
3. the single table surface high-voltage thyristor chip according to claim 1 using the two-way scribing of symmetry, it is characterised in that:
The ditch groove deep of the isolation deactivation slot: 130-150 um.
4. the single table surface high-voltage thyristor chip according to claim 1 using the two-way scribing of symmetry, it is characterised in that:
The junction depth of the forward voltage PN junction and backward voltage PN junction are as follows: 80-95 um.
5. the manufacturing method of the single table surface high-voltage thyristor chip using the two-way scribing of symmetry, which is characterized in that including following
Step:
(1) silicon wafer Incoming Quality Control: selection resistivity is 50-70 Ω cm, edge<111>the direction growth of thickness 350-450um
Pulling of crystals or zone melting single-crystal；
(2) grow oxidation film: high temperature wet oxygen method growth thickness is greater than the oxide layer of 1um；
(3) photoetching isolation window: in silicon wafer dual coating photoresist, through exposure and development, after post bake, using the removal of BOE corrosive liquid every
From the oxide layer in window, sulfuric acid removes the photoresist of surface residual；
(4) two-sided isolation scribing: utilizing grinding wheel cutting-up equipment, carries out cutting-up, depth 60- at two-sided isolation ring in advance
90um；
(5) two-sided injection aluminium: the silicon source in ion implantation apparatus injects silicon chip surface, Implantation Energy 120- after accelerating by high pressure
150KeV, implantation dosage 2.5-4E15/cm 2；
(6) isolation diffusion: 1200-1300 DEG C of diffusion temperature, diffusion time 10-15 hour is passed through nitrogen and oxygen is protected,
Nitrogen flow 2-6L/min, oxygen flow 0.2-0.6L/min；Heating rate be 3-5 DEG C/min, rate of temperature fall be 1-3 DEG C/
Min, it is uncrossed 50um to just intersecting that the isolation of formation, which intersects ring width,；
(7) two-sided injection boron: Implantation Energy 40-80KeV, implantation dosage 0.5-1.5E15/cm 2；
(8) two-sided injection aluminium: Implantation Energy 120-150KeV, implantation dosage 1-2E15/cm 2；
(9) the short base area diffusion of p-type: 1200-1300 DEG C of diffusion temperature, diffusion time 15-20 hour；Diffusion atmosphere: nitrogen and oxygen
Gas ratio 10:1, wherein nitrogen flow 2-6L/min, oxygen flow 0.2-0.6L/min, 3-5 DEG C of heating rate/min, cooling are fast
1-3 DEG C of rate/min forms the short base area of positive p-type and the back side base area PXing Duan, wherein the junction depth of boron is 35-45um, the junction depth of aluminium
For 80-95um, isolation ring width is 150-200um；
(10) photoetching emitter region: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and the oxide layer in BOE corrosive liquid removal emitter region is recycled, and sulfuric acid removes the photoresist of surface residual；
(11) it emitter region phosphorus diffusion: is spread using phosphorus oxychloride (POCl3) liquid source, 1050-1150 DEG C of pre-expansion temperature, when pre-expansion
Between 60-90 minutes, 15-20 DEG C of source temperature, phosphorus expands 1150-1200 DEG C of temperature again, time 4-5 hour, and R is 0.5-1.5 Ω/,
Diffusion junction depth is 10-25um, forms front N+ type emitter region；
(12) photoetching deactivation slot: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and the oxide layer in BOE corrosive liquid removal deactivation slot is recycled；
(13) it is passivated groove corrosion: using silicon etch solution erosion grooves, ditch groove deep: 130-150um；
(14) deactivation slot is protected: one layer of Sipos protective film is grown with LPCVD method corroding in deactivation slot out, with a thickness of 9000-
11000A is subsequently filled the glass paste stirred into glass powder and binder by 1.4-2:1 and is uniformly applied to front side of silicon wafer, passes through
It is sintered at high temperature into glass, then grows one layer of LTO film with LPCVD method and covers silicon chip surface, with a thickness of 3000-6000A；
(15) photoetching lead district: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and BOE corrosive liquid and silicon etch solution is recycled successively to remove the LTO-Sipos-SiO2 in lead district, sulfuric acid removal
The photoresist of surface residual；
(16) two-sided evaporation electrode: titanium-nickel-silver is evaporated respectively at the positive back side of silicon wafer, titanium evaporates thickness requirement 1200-1600A, nickel
Thickness requirement 4500-5500A is evaporated, silver evaporation thickness requirement 4500-5500A forms gate electrode G, cathode electrode K and anode
Electrode A；
(17) photoetching anti-carves area: coating photoresist in front side of silicon wafer, through exposure and development, after post bake, coats photoetching in silicon chip back side
Glue is protected, and the removal of metal erosion liquid is recycled to anti-carve unwanted metal layer in area, and stripper removes the light of surface residual
Photoresist；
(18) alloy: vacuum alloy reinforces the binding force of metal and silicon；
(19) it tests: requiring to be tested according to chip parameter；
(20) cutting-up: silicon wafer cutting-up is at chip disconnected from each other.
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| CN111933684A (en) * | 2020-06-23 | 2020-11-13 | 济宁东方芯电子科技有限公司 | Silicon controlled rectifier isolation wall and short base region synchronous diffusion structure and method |
| CN112582480A (en) * | 2020-12-15 | 2021-03-30 | 扬州杰利半导体有限公司 | PN junction passivation process for low-medium voltage table top TVS product |
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| CN117174760A (en) * | 2023-11-02 | 2023-12-05 | 江西信芯半导体有限公司 | TVS chip with field ring structure and manufacturing method thereof |
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| CN117174747B (en) * | 2023-11-03 | 2024-03-08 | 江苏捷捷微电子股份有限公司 | Gate and anode coplanar bidirectional silicon controlled rectifier chip and manufacturing method thereof |
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