CN102244079A - Power transistor chip structure of mesa technology and implementation method - Google Patents
Power transistor chip structure of mesa technology and implementation method Download PDFInfo
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- CN102244079A CN102244079A CN2011102132779A CN201110213277A CN102244079A CN 102244079 A CN102244079 A CN 102244079A CN 2011102132779 A CN2011102132779 A CN 2011102132779A CN 201110213277 A CN201110213277 A CN 201110213277A CN 102244079 A CN102244079 A CN 102244079A
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Abstract
The invention relates to a power transistor chip structure of a mesa technology. The structure comprises an N+ emitter region, an emitting electrode aluminum electrode, a base pole aluminum electrode, a SiO2 protective film, glass passivation films, an N+ substrate diffusion layer, a P-type base region diffusion layer and a silicon single crystal chip; the front side of the silicon single crystal chip is provided with the P-type base region diffusion layer; the back side of the silicon single crystal chip is provided with the N+ substrate diffusion layer; the surface of the P-type base region diffusion layer is provided with the SiO2 protective film, the base pole aluminum electrode, the N+ emitter region and the emitting electrode aluminum electrode; front surface grooves are arranged on the silicon single crystal chip and the P-type base region diffusion layer; and the base parts and the side walls of the front surface grooves are provided with the glass passivation films. The structure is characterized in that the periphery of the back side of the N+ substrate diffusion layer is provided with a back side stress balance groove; the top part and the side wall of the back side stress balance groove are provided with glass films; and a plurality of layers of metal electrodes are arranged on the N+ substrate diffusion layer and the surfaces of the glass films. The structure provided by the invention has the advantages of mature structure and technology, simple manufacturing process, good breakdown voltage property of the manufactured chip, and high reliability of products.
Description
Technical field
The present invention relates to a kind of mesa technique power transistor chip structure, also relate to a kind of mesa technique power transistor chip implementation method, belong to power semiconductor device manufacturing technology field.
Background technology
Power transistor is in the manufacturing of middle and high piezoelectric forces semiconductor device chip, so far still extensively adopt the mesa technique manufacturing technology, shown in Fig. 1-4, the thick passivation glass film of one deck 30～50um of having grown in the groove in silicon wafer front, big a lot (coefficient of expansion of general passivation glass is 4.4 ± 0.4 * 10 because the coefficient of expansion of this glass-film is than silicon
-6/ ℃, and the coefficient of expansion of silicon is 2.6 * 10
-6/ ℃); after glass sintering is finished; glass-film in the groove of front has produced a very big shrinkage stress; the pulling silicon wafer is bent upwards, because the bending of silicon wafer makes silicon chip central area and lithography mask version not to be adjacent to and produce the slit, causes the waste product generation; fall sheet through regular meeting; the silicon wafer percentage of damage is very high, and this method only is suitable for the processing procedure of 4 inches silicon wafers of 2 inches～Φ of Φ, is difficult to above technology is used for the silicon wafer processing procedure of 4 inches of 5 inches～Φ of Φ.
Summary of the invention
The purpose of this invention is to provide a kind of mesa technique power transistor chip structure, a kind of mesa technique power transistor chip implementation method also is provided simultaneously.
The technical solution used in the present invention is: comprise N
+Emitter region, emitter aluminium electrode, base stage aluminium electrode, SiO
2Diaphragm, glassivation film, N
+Substrate diffusion layer, P type base diffusion layer and silicon single crystal flake, described silicon single crystal flake front are provided with P type base diffusion layer, and the described silicon single crystal flake back side is provided with N
+The substrate diffusion layer, described P type is provided with N in the base
+The emitter region, diffusion layer surface, described P type base and N
+The surface, emitter region is provided with SiO
2Diaphragm, base stage aluminium electrode and emitter aluminium electrode, described silicon single crystal flake and P type base diffusion layer are provided with the front groove, and described front channel bottom and sidewall are provided with the glassivation film, it is characterized in that: described N
+Substrate diffusion layer back periphery is provided with back side stress equilibrium groove, and stress equilibrium groove top, the described back side and sidewall are provided with glass-film, described N
+Substrate diffusion layer surface and glass-film surface are provided with the multiple layer metal electrode.
Described back side stress equilibrium groove depth is 50-110um, and described back side stress equilibrium well width is 100-240um.。
Mesa technique power transistor chip implementation method comprises N
+The step of substrate diffusing step, front polishing attenuate, the diffusion of the step of chemical corrosion or chemico-mechanical polishing, positive P type base and growth oxide layer step, the positive emitter window step of photoetching, N are carried out in the silicon chip front
+The emitter region phosphorous diffusion and the oxide layer step of growing, photoengraving groove step, in groove filling glass and carry out sintering step and subsequent processing steps, described N
+The substrate diffusing step is N
+The substrate diffusion forms the high concentration substrate layer; The step of described front polishing attenuate is for removing the N in silicon chip front with the method for mechanical lapping
+Substrate layer; Described photoengraving groove step is the corrosion window in photoetching front, and goes out the ring-shaped groove of certain depth at front etch; Described in groove filling glass and carry out sintering step and be filling glass and carry out sintering in groove, the glass-film after burning till is as the terminal passivating film of P-N knot; Described subsequent processing steps is growth LTO passivating film; glass-film is protected; fairlead in positive photoetching base and emitter region; at positive AM aluminum metallization film; anti-carve positive aluminium electrode; alloy; remove back side oxide layer, back side evaporation metal electrode, chip testing and sorting; scribing; carry out chip and separate, check; the packing, described photoengraving groove step be photoetching just; the corrosion window at the back side; and just; the back side erodes away groove simultaneously; gash depth is 50-110um, and groove width is 100-240um, filling glass and carry out sintering in the groove of front and back; burn till the passivating film of the glass-film of front, back groove as the P-N knot; the glass-film that burns till the back backside trench is used to flatten silicon chip as the convergent force in balance front, and ℃ following annealing 3-6h in glass transition point-(10～20) realizes reducing the glass swelling coefficient.
Advantage of the present invention is: structure and technical maturity, manufacture process is simple, the chip breakdown voltage characteristics of making is good, qualification rate is higher, and product reliability is higher, chip passive region at the silicon chip back side has dug out a groove that adjacent chips is shared, we are referred to as to call the stress equilibrium groove, glass and sintering have been filled in this stress equilibrium groove, formed one deck glass-film at its top and sidewall, this glass-film utilizes its bigger shrinkage stress to offset the shrinkage stress of face glass film, make silicon chip smooth, processing procedure after the glassivation is accessible, reduce the percentage of damage of silicon wafer in the processing procedure, adopted two sides method for processing simultaneously, in the temperature-fall period of glass sintering, increased " glass transition point-(10～20) ℃ " down annealing process the glass swelling coefficient is further reduced.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
The mesa technique power transistor chip structural representation that Fig. 1 mentions for background technology.
The mesa technique power transistor chip manufacture process schematic diagram that Fig. 2 mentions for background technology.
Fig. 3 is used for silicon chip flexibility schematic diagram behind the major diameter silicon wafer for background technology.
Fig. 4 is the glass sintering temperature curve of background technology.
Fig. 5 is a mesa technique power transistor chip structural representation of the present invention.
Fig. 6 is mesa technique power transistor chip manufacture process schematic diagram of the present invention, wherein a, N
+The substrate diffusion, b, front attenuate, c, positive mirror polish, d, the diffusion of positive P type base, e, positive base window, f, the N of sending out of photoetching
+Send out the base diffusion, g, dual surface lithography corrosion window and etching tank, filling glass and sintering in h, the groove, i, photoetching front fairlead, j, positive AM aluminum metallization film, anti-carve front side aluminum electrode, l, back metal electrode at k.
Fig. 7 is used for silicon chip flexibility schematic diagram behind the major diameter silicon wafer for the technology of the present invention.
Fig. 8 is the glass sintering temperature curve of the technology of the present invention.
Wherein: 1, N
+The emitter region, 2, emitter aluminium electrode, 3, base stage aluminium electrode, 4, SiO
2Diaphragm, 5, the glassivation film, 6, N
+The substrate diffusion layer, 7, P type base diffusion layer, 8, silicon single crystal flake, 9, the front groove, 10, metal electrode, 11, back side stress equilibrium groove, 12, glass-film.
Embodiment
As Fig. 5, Fig. 6, shown in Figure 8, mesa technique power transistor chip structure comprises N
+Emitter region 1, emitter aluminium electrode 2, base stage aluminium electrode 3, SiO
2Diaphragm 4, glassivation film 5, N
+ Substrate diffusion layer 6, P type base diffusion layer 7 and silicon single crystal flake 8, silicon single crystal flake 8 fronts are provided with P type base diffusion layer 7, and silicon single crystal flake 8 back sides are provided with N
+ Substrate diffusion layer 6 is provided with N in the P type base diffusion layer 7
+ Emitter region 1, P type base diffusion layer 7 and N
+The surface of emitter region 1 is provided with SiO
2Diaphragm 4, base stage aluminium electrode 3 and emitter aluminium electrode 2, silicon single crystal flake 8 and P type base diffusion layer 7 are provided with front groove 9, and front groove 9 bottoms and sidewall are provided with glassivation film 5, N
+ Substrate diffusion layer 6 back peripheries are provided with back side stress equilibrium groove 11, and back side stress equilibrium groove 11 degree of depth are 50um, and back side stress equilibrium groove 11 width are 100um, and stress equilibrium groove 11 tops, the back side and sidewall are provided with glass-film 12, N
+ Substrate diffusion layer 6 and glass-film 12 surfaces are provided with multiple layer metal electrode 10.
As Fig. 6, Fig. 7 and shown in Figure 8, mesa technique power transistor chip implementation method comprises:
N
+Substrate diffusing step: a, use HF:H
3PO
4: HNO
3=1:2:5 corrodes 30 Sec to silicon single crystal flake, removes the affected layer on silicon single crystal flake surface, uses deionized water rinsing 10 times; B, RCA clean, and use deionized water rinsing 15 times; C, drying; D, high concentration phosphorus give deposition, under 1195 ℃, feed and carry POCL
3Nitrogen and oxygen, spread 3.9 h, form N
+Sedimentary deposit requires R
=0.27 Ω/; E, knot under 1270 ℃, nitrogen and oxygen atmosphere, spread 156 h, form the dark N of 170um
+Substrate layer.
The step of front polishing attenuate: with wafer lapping machine the front of silicon chip is ground, remove positive N
+Substrate layer, silicon wafer thickness is 285 um behind the attenuate;
The silicon chip front is carried out the step of chemical corrosion or chemico-mechanical polishing: polish with the method for chemical corrosion or the chemico-mechanical polishing silicon chip front after to attenuate, the silicon wafer thickness after the polishing is 265um;
Base diffusion of positive P type and growth oxide layer step: a, silicon chip is carried out RCA clean, with deionized water rinsing 15 times; B, drying; C, silicon chip front are coated with the boron source; D, boron give deposition, under 945 ℃, nitrogen and oxygen atmosphere, spread 0.9 h, form P type sedimentary deposit, require R
=29 Ω/; E, knot under 1230 ℃, nitrogen and oxygen atmosphere, spread 12 h, form the dark p type diffused layer of 22um;
The positive emitter window step of photoetching: utilize sol evenning machine that photoresist is coated in the silicon chip front,, utilize mask aligner, mask to expose through the preceding baking of 95 ℃/20min, develop, post bake utilizes hydrofluoric acid buffered etch corrosion to remove the silicon dioxide film of window, remove cull, clean, dry;
N
+The emitter region phosphorous diffusion and oxide layer step: a that grows, silicon chip is carried out RCA clean, with deionized water rinsing 15 times; B, drying; C, phosphorus give deposition, under 920 ℃, feed and carry POCL
3Nitrogen and oxygen, spread 1 h, form N
+Sedimentary deposit requires R
=4 Ω/; D, knot, under 1170 ℃, nitrogen and oxygen atmosphere, diffusion 2.5h forms the emitter region, control h
FEMeet the requirements;
Photoengraving groove step: utilize sol evenning machine photoresist to be coated in the positive and negative two sides of silicon chip, preceding baking through 95 ℃/20min, utilize mask aligner, mask to carry out double-sided exposure, develop, post bake utilizes hydrofluoric acid buffered etch corrosion to remove the silicon dioxide film of window, cleans, oven dry utilizes HF:HN0
3 : CH
3 COOH=3:1:1 erodes away the groove of front and back simultaneously, removes cull, cleans, and dries;
Filling glass and carry out sintering step in groove: prepare glass paste, glass paste is scraped silicon chip surface, wipe the outer glass paste of groove, carry out sintering according to temperature curve shown in Figure 8;
Subsequent processing steps: a, growth LTO passivating film are used for the cover glass film; B, at the fairlead of positive photoetching base and emitter region; C, at positive AM aluminum metallization film; D, anti-carve positive aluminium electrode; E, alloy; F, removal back side oxide layer; G, back side evaporation metal electrode; H, chip testing and sorting; I, scribing are carried out chip and are separated; J, check; K, packing.
As Fig. 5, Fig. 6, shown in Figure 8, mesa technique power transistor chip structure comprises N
+Emitter region 1, emitter aluminium electrode 2, base stage aluminium electrode 3, SiO
2Diaphragm 4, glassivation film 5, N
+ Substrate diffusion layer 6, P type base diffusion layer 7 and silicon single crystal flake 8, silicon single crystal flake 8 fronts are provided with P type base diffusion layer 7, and silicon single crystal flake 8 back sides are provided with N
+ Substrate diffusion layer 6 is provided with N in the P type base diffusion layer 7
+ Emitter region 1, P type base diffusion layer 7 and N
+The surface of emitter region 1 is provided with SiO
2Diaphragm 4, base stage aluminium electrode 3 and emitter aluminium electrode 2, silicon single crystal flake 8 and P type base diffusion layer 7 are provided with front groove 9, and front groove 9 bottoms and sidewall are provided with glassivation film 5, N
+ Substrate diffusion layer 6 back peripheries are provided with back side stress equilibrium groove 11, and back side stress equilibrium groove 11 degree of depth are 80um, and back side stress equilibrium groove 11 width are 170um, and stress equilibrium groove 11 tops, the back side and sidewall are provided with glass-film 12, N
+ Substrate diffusion layer 6 and glass-film 12 surfaces are provided with multiple layer metal electrode 10.
As Fig. 6, Fig. 7 and shown in Figure 8, mesa technique power transistor chip implementation method comprises:
N
+Substrate diffusing step: a, use HF:H
3PO
4: HNO
3=1:2:5 corrodes 40 Sec to silicon single crystal flake, removes the affected layer on silicon single crystal flake surface, uses deionized water rinsing 10 times; B, RCA clean, and use deionized water rinsing 15 times; C, drying; D, high concentration phosphorus give deposition, under 1200 ℃, feed and carry POCL
3Nitrogen and oxygen, spread 4.2 h, form N
+Sedimentary deposit requires R
=0.30 Ω/; E, knot, under 1275 ℃, nitrogen and oxygen atmosphere, diffusion 168h forms the dark N of 175um
+Substrate layer.
The step of front polishing attenuate: with wafer lapping machine the front of silicon chip is ground, remove positive N
+Substrate layer, silicon wafer thickness is 290um behind the attenuate;
The silicon chip front is carried out the step of chemical corrosion or chemico-mechanical polishing: polish with the method for chemical corrosion or the chemico-mechanical polishing silicon chip front after to attenuate, the silicon wafer thickness after the polishing is 270um;
Base diffusion of positive P type and growth oxide layer step: a, silicon chip is carried out RCA clean, with deionized water rinsing 15 times; B, drying; C, silicon chip front are coated with the boron source; D, boron give deposition, and under 950 ℃, nitrogen and oxygen atmosphere, diffusion 1h forms P type sedimentary deposit, requires R
=30 Ω/; E, knot, under 1235 ℃, nitrogen and oxygen atmosphere, diffusion 14h forms the dark p type diffused layer of 25um;
The positive emitter window step of photoetching: utilize sol evenning machine that photoresist is coated in the silicon chip front,, utilize mask aligner, mask to expose through the preceding baking of 100 ℃/25min, develop, post bake utilizes hydrofluoric acid buffered etch corrosion to remove the silicon dioxide film of window, remove cull, clean, dry;
N
+The emitter region phosphorous diffusion and oxide layer step: a that grows, silicon chip is carried out RCA clean, with deionized water rinsing 15 times; B, drying; C, phosphorus give deposition, under 930 ℃, feed and carry POCL
3Nitrogen and oxygen, diffusion 1.2h forms N
+Sedimentary deposit requires R
=4.5 Ω/; D, knot, under 1180 ℃, nitrogen and oxygen atmosphere, diffusion 3h forms the emitter region, control h
FEMeet the requirements;
Photoengraving groove step: utilize sol evenning machine photoresist to be coated in the positive and negative two sides of silicon chip, preceding baking through 100 ℃/25min, utilize mask aligner, mask to carry out double-sided exposure, develop, post bake utilizes hydrofluoric acid buffered etch corrosion to remove the silicon dioxide film of window, cleans, oven dry utilizes HF:HN0
3 : CH
3 COOH=4:1:1 erodes away the groove of front and back simultaneously, removes cull, cleans, and dries;
Filling glass and carry out sintering step in groove: prepare glass paste, glass paste is scraped silicon chip surface, wipe the outer glass paste of groove, carry out sintering according to temperature curve shown in Figure 8;
Subsequent processing steps: a, growth LTO passivating film are used for the cover glass film; B, at the fairlead of positive photoetching base and emitter region; C, at positive AM aluminum metallization film; D, anti-carve positive aluminium electrode; E, alloy; F, removal back side oxide layer; G, back side evaporation metal electrode; H, chip testing and sorting; I, scribing are carried out chip and are separated; J, check; K, packing.
As Fig. 5, Fig. 6, shown in Figure 8, mesa technique power transistor chip structure comprises N
+Emitter region 1, emitter aluminium electrode 2, base stage aluminium electrode 3, SiO
2Diaphragm 4, glassivation film 5, N
+ Substrate diffusion layer 6, P type base diffusion layer 7 and silicon single crystal flake 8, silicon single crystal flake 8 fronts are provided with P type base diffusion layer 7, and silicon single crystal flake 8 back sides are provided with N
+ Substrate diffusion layer 6 is provided with N in the P type base diffusion layer 7
+ Emitter region 1, P type base diffusion layer 7 and N
+The surface of emitter region 1 is provided with SiO
2Diaphragm 4, base stage aluminium electrode 3 and emitter aluminium electrode 2, silicon single crystal flake 8 and P type base diffusion layer 7 are provided with front groove 9, and front groove 9 bottoms and sidewall are provided with glassivation film 5, N
+ Substrate diffusion layer 6 back peripheries are provided with back side stress equilibrium groove 11, and back side stress equilibrium groove 11 degree of depth are 110um, and back side stress equilibrium groove 11 width are 240um, and stress equilibrium groove 11 tops, the back side and sidewall are provided with glass-film 12, N
+ Substrate diffusion layer 6 and glass-film 12 surfaces are provided with multiple layer metal electrode 10.
As Fig. 6, Fig. 7 and shown in Figure 8, mesa technique power transistor chip implementation method comprises:
N
+Substrate diffusing step: a, use HF:H
3PO
4: HNO
3=1:2:5 corrodes 45 Sec to silicon single crystal flake, removes the affected layer on silicon single crystal flake surface, uses deionized water rinsing 10 times; B, RCA clean, and use deionized water rinsing 15 times; C, drying; D, high concentration phosphorus give deposition, under 1205 ℃, feed and carry POCL
3Nitrogen and oxygen, diffusion 4.5h forms N
+Sedimentary deposit requires R
=0.33 Ω/; E, knot, under 1280 ℃, nitrogen and oxygen atmosphere, diffusion 180h forms the dark N of 180um
+Substrate layer.
The step of front polishing attenuate: with wafer lapping machine the front of silicon chip is ground, remove positive N
+Substrate layer, silicon wafer thickness is 295um behind the attenuate;
The silicon chip front is carried out the step of chemical corrosion or chemico-mechanical polishing: polish with the method for chemical corrosion or the chemico-mechanical polishing silicon chip front after to attenuate, the silicon wafer thickness after the polishing is 275um;
Base diffusion of positive P type and growth oxide layer step: a, silicon chip is carried out RCA clean, with deionized water rinsing 15 times; B, drying; C, silicon chip front are coated with the boron source; D, boron give deposition, under 955 ℃, nitrogen and oxygen atmosphere, spread 1.1 h, form P type sedimentary deposit, require R
=31 Ω/; E, knot under 1240 ℃, nitrogen and oxygen atmosphere, spread 16 h, form the dark p type diffused layer of 28um;
The positive emitter window step of photoetching: utilize sol evenning machine that photoresist is coated in the silicon chip front,, utilize mask aligner, mask to expose through the preceding baking of 105 ℃/30min, develop, post bake utilizes hydrofluoric acid buffered etch corrosion to remove the silicon dioxide film of window, remove cull, clean, dry;
N
+The emitter region phosphorous diffusion and oxide layer step: a that grows, silicon chip is carried out RCA clean, with deionized water rinsing 15 times; B, drying; C, phosphorus give deposition, under 940 ℃, feed and carry POCL
3Nitrogen and oxygen, diffusion 1.4h forms N
+Sedimentary deposit requires R
=5 Ω/; D, knot under 1190 ℃, nitrogen and oxygen atmosphere, spread 3. 5 h, form the emitter region, control h
FEMeet the requirements;
Photoengraving groove step: utilize sol evenning machine photoresist to be coated in the positive and negative two sides of silicon chip, preceding baking through 105 ℃/30min, utilize mask aligner, mask to carry out double-sided exposure, develop, post bake utilizes hydrofluoric acid buffered etch corrosion to remove the silicon dioxide film of window, cleans, oven dry utilizes HF:HN0
3 : CH
3 COOH=4:1:1 erodes away the groove of front and back simultaneously, removes cull, cleans, and dries;
Filling glass and carry out sintering step in groove: prepare glass paste, glass paste is scraped silicon chip surface, wipe the outer glass paste of groove, carry out sintering according to temperature curve shown in Figure 8;
Subsequent processing steps: a, growth LTO passivating film are used for the cover glass film; B, at the fairlead of positive photoetching base and emitter region; C, at positive AM aluminum metallization film; D, anti-carve positive aluminium electrode; E, alloy; F, removal back side oxide layer; G, back side evaporation metal electrode; H, chip testing and sorting; I, scribing are carried out chip and are separated; J, check; K, packing.
Claims (3)
1. mesa technique power transistor chip structure comprises N
+Emitter region, emitter aluminium electrode, base stage aluminium electrode, SiO
2Diaphragm, glassivation film, N
+Substrate diffusion layer, P type base diffusion layer and silicon single crystal flake, described silicon single crystal flake front are provided with P type base diffusion layer, and the described silicon single crystal flake back side is provided with N
+The substrate diffusion layer, described P type is provided with N in the base
+The emitter region, diffusion layer surface, described P type base and N
+The surface, emitter region is provided with SiO
2Diaphragm, base stage aluminium electrode and emitter aluminium electrode, described silicon single crystal flake and P type base diffusion layer are provided with the front groove, and described front channel bottom and sidewall are provided with the glassivation film, it is characterized in that: described N
+Substrate diffusion layer back periphery is provided with back side stress equilibrium groove, and stress equilibrium groove top, the described back side and sidewall are provided with glass-film, described N
+Substrate diffusion layer surface and glass-film surface are provided with the multiple layer metal electrode.
2. mesa technique power transistor chip structure according to claim 1 is characterized in that: described back side stress equilibrium groove depth is 50-110um, and described back side stress equilibrium well width is 100-240um.
3. mesa technique power transistor chip implementation method comprises N
+The step of substrate diffusing step, front polishing attenuate, the diffusion of the step of chemical corrosion or chemico-mechanical polishing, positive P type base and growth oxide layer step, the positive emitter window step of photoetching, N are carried out in the silicon chip front
+The emitter region phosphorous diffusion and the oxide layer step of growing, photoengraving groove step, in groove filling glass and carry out sintering step and subsequent processing steps, described N
+The substrate diffusing step is N
+The substrate diffusion forms the high concentration substrate layer; The step of described front polishing attenuate is for removing the N in silicon chip front with the method for mechanical lapping
+Substrate layer; Described photoengraving groove step is the corrosion window in photoetching front, and goes out the ring-shaped groove of certain depth at front etch; Described in groove filling glass and carry out sintering step and be filling glass and carry out sintering in groove, the glass-film after burning till is as the terminal passivating film of P-N knot; Described subsequent processing steps is growth LTO passivating film; glass-film is protected; fairlead in positive photoetching base and emitter region; at positive AM aluminum metallization film; anti-carve positive aluminium electrode; alloy; remove back side oxide layer; back side evaporation metal electrode; chip testing and sorting; scribing; carry out chip and separate, check; the packing, it is characterized in that: described photoengraving groove step be photoetching just; the corrosion window at the back side; and just; the back side erodes away groove simultaneously; gash depth is 50-110um, and groove width is 100-240um, filling glass and carry out sintering in the groove of front and back; burn till the passivating film of the glass-film of front, back groove as the P-N knot; the glass-film that burns till the back backside trench is used to flatten silicon chip as the convergent force in balance front, and ℃ following annealing 3-6h in glass transition point-(10～20) realizes reducing the glass swelling coefficient.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390385A (en) * | 2015-11-03 | 2016-03-09 | 常州星海电子有限公司 | High-surge glass passivation chip |
| CN110098254A (en) * | 2019-04-30 | 2019-08-06 | 江苏捷捷微电子股份有限公司 | Utilize the single table surface high-voltage thyristor chip and manufacturing method of the two-way scribing of symmetry |
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| US20100025807A1 (en) * | 2008-07-30 | 2010-02-04 | Trion Technology, Inc. | Discrete Semiconductor Device and Method of Forming Sealed Trench Junction Termination |
| CN201402808Y (en) * | 2009-05-07 | 2010-02-10 | 无锡固电半导体股份有限公司 | Single-resistance Darlington pipe used in excitation device of generator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105390385A (en) * | 2015-11-03 | 2016-03-09 | 常州星海电子有限公司 | High-surge glass passivation chip |
| CN110098254A (en) * | 2019-04-30 | 2019-08-06 | 江苏捷捷微电子股份有限公司 | Utilize the single table surface high-voltage thyristor chip and manufacturing method of the two-way scribing of symmetry |
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|---|---|
| CN102244079B (en) | 2013-08-21 |
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