KR20110047828A - Silicon heterojunction solar cell and method for fabricating the same - Google Patents

Abstract

PURPOSE: A silicon hetero-junction and a manufacturing method thereof are provided to optimize the thickness of a passivation layer by forming the passivation layer through an oxide process using ultrapure water or HNO3 solutions. CONSTITUTION: A first type crystalline silicon substrate is prepared. A passivation layer(120) is formed on the first type crystalline silicon substrate by using an oxidation process. A second type amorphous silicon layer(130) is formed on the passivation layer. A transparent conductive layer and a top electrode(170) are formed on a second type amorphous silicon layer. A bottom electrode is formed on the bottom of the first type crystalline silicon substrate.

Description

Silicon heterojunction solar cell and method for manufacturing same {SILICON HETEROJUNCTION SOLAR CELL AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a silicon heterojunction solar cell and a method of manufacturing the same, and to prevent a decrease in efficiency of a solar cell due to recombination of electrons and holes due to defects present at an interface between heterojunction layers of a silicon solar cell. A technique for changing the structure.

Renewable energy using solar energy can be divided into solar power generation system using solar heat and solar cells using solar light.

Double solar cells have the opposite principle to LEDs or laser diodes that convert electrical energy into light energy, and are mostly composed of large-area P-N junction diodes.

The solar cell is composed of n-type region and p-type region, where n-type region has large electron density and small hole density, and p-type region is The opposite is true.

In this structure, in the thermal equilibrium, in the diode composed of a junction of a p-type semiconductor and an n-type semiconductor, an unbalance of charge occurs due to diffusion due to a difference in carrier concentration. An electric field is formed so that diffusion of the carrier no longer occurs.

When these diodes are subjected to light above the band gap energy, which is the difference in energy between the conduction band and valence band of the material, they receive this light energy and the electrons are excited from the valence band to the conduction band. (excited)

At this time, the electrons excited by the conduction band can move freely, and holes are generated in the valence band where electrons escape. This is called an excess carrier, and these excess carriers diffuse by concentration differences in the conduction band or the valence band.

At this time, electrons excited in the p-type region and holes made in the n-type region are referred to as minority carriers, and carriers in a p-type or n-type semiconductor before bonding are conventional. , n-type electrons) are called major carriers.

At this time, the main carriers are interrupted by the energy barrier caused by the electric field, but electrons, p-type minority carriers, move toward the n-type region and holes, n-type minority carriers, move toward the p-type region, respectively. Can be.

The diffusion of a small number of carriers breaks the electrical neutrality of the material, which leads to a potential drop. When the electromotive force generated at the anode terminal of the PN junction diode is connected to an external circuit, it acts as a solar cell. Done.

The solar cell using the solar light can be divided into homojunction and heterojunction according to the properties of p region and n region used for PN junction. When combined with other materials.

1 is a cross-sectional view showing a laminated structure of a heterojunction solar cell according to the prior art.

Referring to the basic structure of a conventional silicon heterojunction solar cell shown in FIG. 1, first, an amorphous silicon layer (a-Si) (emitter) is formed by using a plasma chemical vapor deposition apparatus (PECVD) on both surfaces of a crystalline silicon substrate (base) 10. 30, 35) can be seen to form an amorphous / crystalline PN junction structure.

Next, the basic structure of the silicon heterojunction solar cell is formed by forming the metal lines 50 and 55 spaced apart at equal intervals from the transparent conduction oxide (TCO) 40, 45 on the front surface where light enters. Lose.

At this time, the amorphous / crystalline silicon heterojunction solar cell has been attracting a lot of attention because it can be manufactured in a low temperature, simple process compared to the conventional diffusion-type crystalline silicon solar cell. The biggest factor influencing the characteristics of such heterojunction solar cells is known to be the defect density caused by dangling bonds or the like at the amorphous / crystalline interface.

In other words, when the defect density at the interface is large, it is known that the recombination rate of electrons and holes generated by light increases to decrease the efficiency of the solar cell.

In addition to the surface defects of the base silicon substrate 10, the defects may be caused by damage due to plasma exposure and dopants of the amorphous silicon layers 30 and 35. Surface treatment methods and growth methods are being studied.

As a structure for solving the above problems, a HIT (Heterojunction with Intrinsic Thin film) cell solar cell furnace sold by Sanyo, Japan, has been developed.

As shown in FIG. 1, an HIT cell solar cell includes an intrinsic amorphous silicon layer 20, 25 between an n-type silicon substrate 10 and an amorphous p-type silicon emitter 30, 35. It takes the structure which drastically improved the solar cell efficiency characteristic.

Here, the intrinsic amorphous silicon layers 20 and 25 are purely amorphous silicon layers containing the same number of electrons and the same number of holes, and thus the crystalline silicon substrate 10 and the amorphous silicon layers 30 and 35 are used. It is possible to prevent recombination of electrons and holes due to defects in the interface between them.

However, when the thickness of the intrinsic amorphous silicon layers 20 and 25 is thick, there is a problem in that the efficiency is lower than that of a typical amorphous / crystalline PN heterojunction silicon solar cell. The intrinsic amorphous silicon layers 20 and 25 are made of PE. Since it is formed using a device such as plasma-enhanced chemical vapor deposition (CVD) or hot-wire chemical vapor deposition (HW-CVD), there is a problem that thickness control is not easy.

 In particular, PE-CVD has a very high deposition rate because it is deposited by the VHF (Very High Frequency) method has a problem that can not be finely adjusted to a thickness of less than 10nm.

Therefore, the heterojunction solar cell including the intrinsic amorphous silicon layer has a problem that it is difficult and not easy to manufacture compared to the production of a typical amorphous / crystalline heterojunction solar cell. In addition, there is a problem that the process time is long and the manufacturing cost is increased.

An object of the present invention is to protect a crystalline interface with a material having a high passivation effect in an amorphous / crystalline silicon heterojunction solar cell, and to form a PN diode between the crystalline / amorphous regions, thereby forming a PN diode. It is to provide a heterojunction silicon solar cell having a low recombination rate due to defects and high efficiency stability and reproducibility and a method of manufacturing the same.

Method for manufacturing a silicon heterojunction solar cell according to the present invention comprises the steps of (a) preparing a first type crystalline silicon substrate, (b) forming a passivation layer on the first type crystalline silicon substrate using an oxidation process (C) forming a second type amorphous silicon layer on the passivation layer, (d) forming a transparent conductive film and an upper electrode on the second type amorphous silicon layer; and (e) Forming a lower electrode on the lower surface of the one-type crystalline silicon substrate.

Here, after the step (c), further comprising forming a passivation layer on the second type of amorphous silicon layer using an oxidation process, wherein the passivation layer is SiO ₂ , SiC, SiNx, It is characterized in that the intrinsic amorphous silicon (Intrinsic a-Si: H), characterized in that the passivation layer is formed to a thickness of 0.1 ~ 10nm, the oxidation process is 50 ~ 70 in ultrapure water of 70 ~ 90 ℃ It is characterized in that it is carried out by immersing the silicon substrate for minutes, the oxidation process by immersing the silicon substrate for 10 to 20 minutes in 60 ~ 80% (v / v) HNO ₃ solution at 25 ~ 30 ℃ temperature It is characterized by performing.

In addition, the silicon heterojunction solar cell according to the present invention is characterized in that it is manufactured by the above-described method.

According to the heterojunction silicon solar cell according to the embodiment of the present invention, by forming a passivation layer by an oxidation process using ultrapure water or HNO ₃ solution, the thickness of the passivation layer can be optimized and a uniform passivation layer can be easily formed. Provide the effect.

Therefore, the interface defect between amorphous and crystalline silicon can be reduced, and the P-N diode characteristics can be improved to maximize solar cell filling rate and improve efficiency.

Hereinafter, a high efficiency silicon heterojunction solar cell and a method of manufacturing the same will be described in detail based on the technology of the present invention described above.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only the present embodiments to make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims.

2 is a cross-sectional view showing a heterojunction solar cell according to an embodiment of the present invention.

2, as a heterojunction silicon solar cell according to an embodiment of the present invention, a first type silicon substrate 100, a passivation layer 120, a second type silicon layer 130, a transparent conductive film 150, An upper electrode 170, a field forming layer (BSF) 140, and a lower electrode 160 are included.

However, in the above description, the first type and the second type mean p or n type, and may not be the same type. Hereinafter, for convenience of description, the first type and the second type are referred to as the n type and the second type. Explain it locally.

The first type silicon substrate 100 is a crystalline n-type silicon substrate, and may be either single crystal or polycrystal.

The second type silicon layer 130 is formed of an amorphous p-type silicon layer, which may also be a p-type of a material other than amorphous silicon.

In this case, the passivation layer 120 reduces interface defects occurring at the interface between the second type silicon layer 130 and the first type silicon substrate 100 to minimize recombination of electrons and holes. Finally, the efficiency of the solar cell manufactured can be improved, indicating stable efficiency.

That is, in the case of amorphous / crystalline silicon heterojunction, the defect density at the amorphous / crystalline interface is the biggest factor that determines the characteristics of the solar cell, and the plasma damage and dopant, which are the causes of the defect density, are caused. By minimizing defect formation at the interface between amorphous and crystalline to minimize damage, the passivation of the crystalline can lower the density of interfacial defects and thereby lower the recombination rate of carriers at the interface. It is.

Such a passivation layer 120 should be able to move the electron (e-), which is a minority carrier (minority carrier) of the silicon substrate 100, to the p-type silicon layer 130, and the minority of the p-type silicon layer 130 Since the hole, which is a carrier, should be able to be moved to the p-type silicon substrate 100, it should be connected to a predetermined gap.

As described above, the passivation layer 120 is formed of a material capable of minimizing PN interface defects to serve as a buffer layer layer to minimize PN interface defects, and at the same time, the passivation layer 120 is formed therein. By forming a plurality of holes (through hole) through the upper surface and the lower surface (through hole) is a layer that serves to free the movement of the minority carrier described above.

However, when the passivation layer 120 is provided, the first type crystalline silicon substrate 100 and the second type silicon layer 130 may be connected to each other only through the pores, and thus the minority carriers may be connected. Although the collecting capacity and the moving force of may drop, the collecting capacity due to the diffusion of minority carriers in the bulk region by passivation of the surface may increase.

Accordingly, the passivation layer 130 is formed of a material capable of minimizing defects in the PN interface as described above. Specifically, the passivation layer 130 is selected from SiO ₂ , SiC, SiNx, and intrinsic amorphous silicon (Intrinsic a-Si: H). It is preferable to form one or more.

In the passivation layer 120 described above, the proportion of the voids based on the plan view surface area is preferably in the range of 50% or less of the total surface area based on the plan view, and the distance d between the centers of the neighboring pores is several nm. It can be freely determined in the range of several micrometers, specifically 1 nm-9 micrometers. And the shape of the voids can be freely designed in the form of squares, triangles, circles, ovals, and other polygons when viewed from the top view.

As described above, specific details of the voids formed in the passivation layer 120 have been described, but in order to smoothly perform the function of the passivation layer 120 described above, that is, due to the internal field effect through PN diode formation. In order to enable the collection of electrons and holes, the size of the pores and the spacing between neighboring pores need to be properly adjusted.

To this end, the thickness of the passivation layer 120 is preferably several nm to several tens nm, but should be freely determined in the range of 0.1 to 10 nm as a condition for minimizing the reflectance. If the thickness of the passivation layer is less than 0.1 nm, it may not function as a passivation layer, and thus the meaning of formation may be lost. If the thickness of the passivation layer exceeds 10 nm, as described above, the general amorphous / crystalline PN heterojunction silicon There is a problem that can show a lower efficiency than the solar cell.

Therefore, while the thickness control is essential, in the related art, since the passivation layer is formed by using a device such as PE-CVD or HW-CVD, the thickness control as described above was not easy. Therefore, in the present invention, the method of forming the passivation layer 120 is introduced by an oxidation process using ultrapure water or HNO ₃ solution, thereby enabling fine thickness control. In addition, in the prior art, it was difficult to uniformly form a thin passivation layer, but it was possible with the method according to the present invention, so that a dense passivation layer could be formed.

Next, the transparent conductive film layer 150 is formed on the second type silicon layer 130, and the upper electrode 170 in which the solar cell is connected to the external conductor is incident on the top of the transparent conductive film layer 150. It is formed to maintain a constant interval for the incident light.

Next, the lower electrode 160 of the solar cell according to the present invention is formed on the lower surface of the first type silicon substrate 100, and the upper electrode 170 and the lower electrode 160 described above are both electric It is formed using one or more of metals having good conductivity, such as Al, Pt, Au, Cu, and Ag.

In addition, as shown in FIG. 2, a structure in which an electric field forming layer (BSF) 140 is applied may be used at an interface between the first type silicon substrate 100 and the lower electrode 160. The back surface field formation layer 140 is formed by applying a metal layer as a lower electrode and then heat-treating at a high temperature. The back surface field formation layer 140 acts as an impurity on the back surface of the crystalline silicon substrate by n + The n + layer reduces the back recombination of electrons generated by light, increasing the efficiency of the solar cell.

Although not shown, a surface of a texturing structure may be formed at an interface between the above-described layers by an etching process. Such a texturing structure may lower reflectance and improve light collection. Make sure

As described above, the silicon heterojunction solar cell according to the present invention includes a passivation layer, and in order to maximize the effect of the passivation layer, an oxide process using ultrapure water or HNO ₃ solution is formed to a thickness of 0.1 to 10 nm. do.

2 illustrates that a passivation layer is formed at an interface between the silicon substrate 100 and the amorphous silicon layer 130, and FIG. 3 illustrates an amorphous silicon layer 220 and a transparent conductive film ( It is shown that the passivation layer is formed at the interface between 250).

3 is a cross-sectional view showing a heterojunction solar cell according to another embodiment of the present invention.

Referring to FIG. 3, a first type silicon substrate 200, a second type silicon layer 220, a passivation layer 230, a transparent conductive film 250, an upper electrode 270, and a field forming layer (BSF, 240) And both the function and shape of the lower electrode 260 is the same as the structure of FIG.

Here, the passivation layer 230 is formed by an oxidation process using ultrapure water or HNO ₃ solution (Oxidation), so that it is possible to control the fine thickness in the range of 0.1 ~ 10nm, thereby improving the interface properties.

Hereinafter, a method of forming a passivation layer and forming conditions thereof applied to the above-described two embodiments will be described in more detail.

4A to 4C are cross-sectional views illustrating a heterojunction solar cell manufacturing method for forming the passivation layer of the FIG. 2 structure.

First, referring to FIGS. 4A and 4B, passivation layers 310 and 315 are formed on both surfaces of a first type crystalline silicon substrate 300 in order to manufacture a silicon heterojunction solar cell.

In this case, the passivation layers 310 and 315 are formed by oxidation using ultrapure water or HNO ₃ solution.

In the case of using ultrapure water, the silicon substrate 300 is immersed in ultrapure water of 70 to 90 ° C. for 50 to 70 minutes, and 60 to 80% of the temperature of 25 to 30 ° C. (v / v) when using HNO ₃ solution. ) Is preferably performed by immersing the silicon substrate 300 in a HNO ₃ solution for 10-20 minutes.

Here, an apparatus for maintaining the temperature of ultrapure water or HNO ₃ solution and immersing the silicon substrate 300 is schematically shown in FIG. 6. If the temperature of the ultrapure water is less than 70 ℃ may be a problem that the immersion time exceeds 70 minutes, if the temperature of the ultrapure water exceeds 90 ℃ may cause a problem that the thickness of the passivation layer is not easy to control due to the rapid oxidation rate. have.

In addition, when using HNO ₃ solution having a concentration of less than 60% (v / v), the oxidation process may be excessively delayed, and the oxidation rate when using HNO ₃ solution having a concentration exceeding 80% (v / v). This may cause a problem that the thickness of the passivation layer is not easy to be increased.

In addition, if the temperature of the HNO ₃ solution is less than 25 ℃, and the time to immerse less than 10 minutes, the oxidation process is insufficient to perform the passivation layer is not normally formed, the temperature of the HNO ₃ solution exceeds 30 ℃, If the immersion time exceeds 20 minutes, the oxidation process is excessively performed, which may cause a problem in that the thickness of the passivation layer is not easily adjusted.

Referring to FIG. 4C, after performing the oxidation process as described above, a process of removing the passivation layer 315 formed on the bottom surface of the silicon substrate 300 is performed. At this time, the process of removing the passivation layer is a first step of immersing in a mixed solution of Hydrofluoric Acid (HF) and Buffered Oxide Etch (BOE) for 30 seconds to 2 minutes, and immersed in DI water twice in succession It is preferable to proceed to the second step of washing. The solution immersion step of removing the back passivation layer 315 as described above is shown in Figure 7 below.

Next, a second type amorphous silicon layer is formed on the passivation layer 310, and then zinc oxide (ZnO), indium tin oxide (ITO), and AZO (Aluminum-) are formed on the second type silicon layer 310. A transparent conductive film is formed using a material such as doped zinc oxide, and an upper metal electrode is formed on the transparent conductive film.

Finally, when the lower electrode is formed under the first type silicon base substrate 300, the heterojunction silicon solar cell according to the present invention is completed.

5A to 5C are cross-sectional views illustrating a heterojunction solar cell manufacturing method for forming a passivation layer of the FIG. 3 structure.

5A to 5C, a second type amorphous silicon layer 410 is formed on the first type crystalline silicon substrate 400 to manufacture a silicon heterojunction solar cell, and a passivation layer is formed on both surfaces of the structure. 410 and 415.

In this case, the passivation layers 410 and 415 are formed by oxidation using ultrapure water or HNO ₃ solution according to the conditions described above.

Next, a process of removing the passivation layer 415 formed on the lower surface, forming a transparent conductive film, and forming an upper metal electrode on the transparent conductive film are also performed by the same process as that of FIGS. 4A to 4C. do.

In addition, the oxidation process using the ultrapure water or HNO ₃ solution (Oxidation) is shown in Figure 6, the method of removing the back passivation layer is shown in Figure 7.

As described above, in the case of the silicon heterojunction solar cell according to the embodiments of the present invention, a stable passivation layer may be formed. In particular, a thin passivation layer of 10 nm or less can be uniformly formed, and as a more compact structure can be formed, the stability and reproducibility of solar cell efficiency can be very excellent.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be modified in various forms, and having ordinary skill in the art to which the present invention pertains. It will be appreciated that one can implement other specific forms without changing the technical spirit or essential features of the present invention. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 is a cross-sectional view showing a laminated structure of a heterojunction solar cell according to the prior art.

Figure 2 is a cross-sectional view showing a heterojunction solar cell according to an embodiment of the present invention.

Figure 3 is a cross-sectional view showing a heterojunction solar cell according to another embodiment of the present invention.

4A to 4C are cross-sectional views illustrating a heterojunction solar cell manufacturing method for forming a passivation layer of the FIG. 2 structure.

5A to 5C are cross-sectional views illustrating a heterojunction solar cell manufacturing method for forming a passivation layer of the FIG. 3 structure.

6 is a photo schematically showing a method of performing an oxidation process using ultrapure water or HNO ₃ solution.

7 is a photo schematically showing how to remove the back passivation layer.

Claims (7)

In the manufacturing method of a silicon heterojunction solar cell, (a) preparing a first type crystalline silicon substrate; (b) forming a passivation layer on the first type crystalline silicon substrate using an oxidation process; (c) forming a second type amorphous silicon layer on the passivation layer; (d) forming a transparent conductive film and an upper electrode on the second type amorphous silicon layer; And (e) forming a lower electrode on a lower surface of the first type crystalline silicon substrate; Method for producing a silicon heterojunction solar cell comprising a. The method of claim 1, After the step (c), further comprising the step of forming a passivation layer on the second type of amorphous silicon layer using an oxidation process. The method of claim 1, The passivation layer is a method of manufacturing a silicon heterojunction solar cell, characterized in that selected from SiO ₂ , SiC, SiNx, intrinsic amorphous silicon (Intrinsic a-Si: H). The method of claim 1, The passivation layer is a silicon heterojunction solar cell manufacturing method characterized in that formed to a thickness of 0.1 ~ 10nm. The method of claim 1, The oxidation process is a method of manufacturing a silicon heterojunction solar cell, characterized in that performed by immersing the silicon substrate in ultrapure water of 70 ~ 90 ℃ for 50 ~ 70 minutes. The method of claim 1, The oxidation process is a silicon heterojunction solar cell manufacturing method, characterized in that performed by immersing the silicon substrate in 60 ~ 80% (v / v) HNO ₃ solution at 25 ~ 30 ℃ temperature for 10 to 20 minutes. A silicon heterojunction solar cell prepared by the method of any one of claims 1 to 6.

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