KR100847741B1 - Point-contacted heterojunction silicon solar cell having passivation layer between the interface of p-n junction and method for fabricating the same - Google Patents

Abstract

A point-contact heterojunction silicon solar cell having a passivation layer on a p-n junction interface is provided to reduce an interfacial defect by minimizing a contact area between amorphous silicon and crystalline silicon. A passivation layer(305) is formed on an interface between a crystalline silicon wafer(300) of a first type and an amorphous silicon layer(310) of a second type wherein a plurality of voids penetrating the front and back surfaces of the passivation layer are formed in the passivation layer. The crystalline silicon wafer of the first type comes in contact with the amorphous silicon layer of the second type only by the voids. The passivation layer can be selected from SiO2, SiC, SiNx and intrinsic amorphous silicon.

Description

POINT-CONTACTED HETEROJUNCTION SILICON SOLAR CELL HAVING PASSIVATION LAYER BETWEEN THE INTERFACE OF p-n JUNCTION AND METHOD FOR FABRICATING THE SAME}

1 is a view for explaining the principle of electricity generation for solar cells using sunlight.

2A to 2C are cross-sectional views schematically showing a conventional silicon heterojunction solar cell.

3 is a cross-sectional view showing a heterojunction silicon solar cell according to an embodiment of the present invention.

4 shows a top view of the passivation layer 305 of FIG. 3.

5A to 5F are process cross-sectional views illustrating a method of manufacturing a heterojunction silicon solar cell according to the present invention.

6 is a scanning electron microscope (SEM) and transmission electron microscope (TEM) photograph showing a plan view (left) of the surface of a patterned passivation layer prepared according to the above embodiment, and a cross-sectional shape (right) of a solar cell made using the same. to be.

7 is a graph illustrating changes in spectral response characteristics according to wavelengths of light in a silicon solar cell manufactured according to an embodiment and a solar cell manufactured according to a comparative example.

<Explanation of symbols for the main parts of the drawings>

300: first type crystalline silicon base substrate

305: passivation layer

310: type 2 amorphous silicon layer

311: photoresist pattern

315: void

320: transparent conductive oxide film

330: upper electrode

340: lower electrode

The present invention relates to a heterojunction silicon solar cell and a method of manufacturing the same, and more particularly, to prevent a decrease in efficiency of a solar cell due to recombination of electrons and holes due to defects present at an interface between pn junction layers of a silicon solar cell. The present invention relates to a heterojunction silicon solar cell in which the interfacial structure of a pn heterojunction layer is changed, and a manufacturing method thereof.

Renewable energy using solar energy can be divided into solar power generation system using solar heat and solar cells using solar light.

Dual solar cells have the opposite principle to LEDs or laser diodes that convert electrical energy into light energy, and are mostly composed of large area p-n junction diodes.

1 is a view for explaining the principle of electricity generation for solar cells using sunlight.

As shown in FIG. 1, the solar cell includes an n-type region 110 and a p-type region 120, where the n-type region 110 has a large electron density and a small hole. It has a hole density, and the p-type region 120 is the opposite of that.

In such a structure, in the thermal equilibrium, in the diode composed of a junction of a p-type semiconductor and an n-type semiconductor, an unbalance of charge occurs due to diffusion due to a concentration gradient of carriers. (electric field) is formed so that carrier diffusion no longer occurs.

When these diodes are subjected to light above the band gap energy, which is the difference in energy between the conduction band and valence band of the material, they receive this light energy and the electrons are excited from the valence band to the conduction band. (excited)

At this time, the electrons excited by the conduction band can move freely, and holes are generated in the valence band where electrons escape. This is called an excess carrier, and these excess carriers diffuse by concentration differences in the conduction band or the valence band.

At this time, the electrons excited in the p-type region 120 and the holes made in the n-type region 110 are called minority carriers, and carriers in the p-type or n-type semiconductor before the conventional junction The p-type holes and the n-type electrons are called major carriers.

At this time, the main carriers are interrupted by the energy barrier caused by the electric field, but the electrons, which are the minority carriers of the p-type, move toward the n-type region 110, and the holes, which are the minority carriers of the n-type, form the p-type region. You can move towards each other.

Due to the diffusion of a small number of carriers, the electric neutrality inside the material is broken, resulting in a potential drop. When the electromotive force generated at the anode terminal of the pn junction diode is connected to an external circuit, it acts as a solar cell. do.

The solar cell using the solar light can be divided into homojunction and heterojunction according to the properties of the p region and the n region used for pn junction. When combined with other materials.

2A to 2C are cross-sectional views schematically showing a conventional silicon heterojunction solar cell.

First, referring to FIG. 2A, a conventional silicon heterojunction solar cell deposits amorphous silicon (a-Si) (emitter) 210 on a crystalline silicon wafer (base) 200 using a plasma chemical vapor deposition apparatus (PECVD). Thereby forming an amorphous / crystalline pn structure, and forming a metal line 230 spaced apart from the transparent conduction oxide (TCO) 220 at a predetermined interval on the front surface where light enters, and the rear surface of the wafer 200. The basic structure is made by forming the rear electrode 240.

Amorphous / crystalline silicon heterojunction solar cell as shown in Figure 2a has been attracting a lot of attention because it can be produced in a low temperature, simple process compared to the conventional diffusion-type crystalline silicon solar cell. The biggest factor influencing the characteristics of such heterojunction solar cells is known to be the defect density caused by dangling bonds or the like at the amorphous / crystalline interface.

In other words, when the defect density at the interface is large, it is known that the recombination rate of electrons and holes generated by light increases to decrease the efficiency of the solar cell.

In addition to the surface defects of the base silicon wafer 200, such defects may be caused by damage caused by plasma exposure and dopants of amorphous silicon 210. Various surface treatment methods may be used to reduce such interface defects. Growth methods have been studied.

FIG. 2B is a HIT (Heterojunction with Intrinsic Thinfilm) cell solar cell sold by Sanyo, Japan, in which a structure for solving the above problem is presented. The n-type silicon base 200 and the amorphous p-type silicon emitter ( Intrinsic amorphous silicon 205 is sandwiched between 210 and several nm in thickness to dramatically improve efficiency characteristics.

In addition, FIG. 2C illustrates a structure in which a texturing and a backside field forming layer are applied to the backside of the wafer 200 in the structure shown in FIG. 2B.

However, compared with the current p (amorphous) / n (crystalline) heterojunction silicon solar cell characteristics using the n-type wafer silicon described above, the n (amorphous) / p (crystalline) structure using p-type wafer silicon shows high efficiency. I can't give it.

The technical problem to be achieved by the present invention is to protect the crystalline interface with a material having a high passivation effect in the amorphous / crystalline silicon heterojunction solar cell by forming a point contact pn diode between the crystalline / amorphous region The present invention provides a heterojunction silicon solar cell having high efficiency stability and reproducibility by reducing the recombination rate due to defects at the pn interface.

Another object of the present invention is to provide a method for manufacturing the heterojunction silicon solar cell.

The technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In the heterojunction silicon solar cell according to the embodiment of the present invention for solving the above technical problem, a second type amorphous silicon layer is formed on a first type crystalline silicon wafer, and a transparent conductive film is formed on the second type amorphous silicon layer. In the heterojunction silicon solar cell having the upper electrode and the lower electrode formed on the lower surface of the first type crystalline silicon wafer, the interface between the first type crystalline silicon wafer and the second type amorphous silicon layer has its own structure. A plurality of voids penetrating the front and rear surfaces are formed, and the passivation layer is inserted to allow the first type crystalline silicon wafer and the second type silicon layer to contact only through the voids.

According to another aspect of the present invention, there is provided a method of manufacturing a heterojunction silicon solar cell, including: (a) forming a passivation layer on a first type crystalline silicon substrate; (b) forming a photoresist pattern by applying a photoresist film on the passivation layer and removing a portion of the photoresist film to expose a portion of the passivation layer through an exposure and development process; (c) removing the passivation layer exposing the photoresist pattern with an etch mask to form a plurality of voids to expose the surface of the first type silicon substrate under the passivation layer; And (d) depositing a second type of amorphous silicon on the passivation layer in which the voids are formed.

Specific details of other embodiments are included in the detailed description and the accompanying drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only the present embodiments to make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

In addition, in the drawings, the size and thickness of layers and films or regions are exaggerated for clarity of description, and when any film or layer is described as being formed "on" of another film or layer, It may be directly on top of the other film or layer, and a third other film or layer may be interposed therebetween.

3A is a cross-sectional view illustrating a heterojunction silicon solar cell according to an embodiment of the present invention, and FIG. 4 is a plan view of the passivation layer 305 of FIG. 3.

As shown in FIG. 3A, the heterojunction silicon solar cell 30 according to the exemplary embodiment of the present invention may include a first type silicon base substrate 300, a passivation layer 305, a second type silicon layer 310, and transparent conduction. The film 320, the upper electrode 330, and the lower electrode 340 are included.

However, in the above description, the first type and the second type mean p or n type, and may not be the same type. Hereinafter, for convenience of description, the first type and the second type are n type. Explain only to.

The first type silicon base substrate 300 is a crystalline p-type silicon substrate, and may be single crystal or polycrystalline.

The second type silicon layer 310 has a constant surface area in contact with the first type silicon base substrate 300 and is made of an amorphous n-type silicon layer. This may also be an n-type of a material other than amorphous silicon.

3A and 4, the passivation layer 305 reduces the interface defects occurring at the interface between the second type silicon layer 310 and the first type silicon base substrate 300 to recombine electrons and holes. This layer is introduced to minimize recombination, improve efficiency of the finally manufactured solar cell, and exhibit stable efficiency.

That is, in the case of amorphous / crystalline silicon heterojunction, the defect density at the amorphous / crystalline interface is the biggest factor that determines the characteristics of the solar cell, and the plasma damage and dopant, which are the causes of the defect density, are caused. In order to minimize damages, the amorphous / crystalline contact area is minimized and most areas are passivated with crystalline materials that can minimize defect formation, thereby reducing the density of interfacial defects and thereby recombining carriers at the interface. Can lower the rate.

Such a passivation layer 305 should be able to move the electron (e-), the minority carrier (minority carrier) of the base layer 300 to the n-type silicon layer 310, the minority of the n-type silicon layer 310 Since the hole, which is a carrier, should be able to move to the p-type base layer 300, it should not cover the entire pn interface, and a certain through hole 315 should be formed.

That is, the passivation layer 305 is formed of a material capable of minimizing pn interface defects to serve as a buffer layer layer that minimizes pn interface defects, and at the same time the top and bottom surfaces of the passivation layer 305 therein. By forming a plurality of through holes (315) through the through is a layer that serves to free the movement of the minority carriers described above.

However, when the passivation layer 305 is provided, the first type crystalline silicon base substrate 300 and the second type silicon layer 310 are in point contact with each other, not through the pn junction. Alternatively, since the collecting ability or the moving force of the minority carriers may be decreased because the contacting of the minority carriers is performed, the collecting capability due to the diffusion of the minority carriers in the bulk region due to passivation of the surface may increase.

As described above, the passivation layer 305 is formed of a material capable of minimizing defects in the pn interface. Specifically, the passivation layer 305 is formed of one selected from SiO ₂ , SiC, SiNx, and intrinsic amorphous silicon. desirable.

In the passivation layer 305, the ratio of the voids 315 to the basis of the plan view surface area is preferably in the range of more than 0% and less than 50% of the total surface area based on the plan view, and the distance between the centers of the neighboring pores ( d) can be freely determined in the range of several nm to several μm, specifically 1 nm to 9 μm.

Although the shape of the void 315 is a quadrangular shape in FIG. 4 when viewed from the top view, it may be freely designed in the form of a triangle, a circle, an ellipse, or another polygon.

Although the details of the gap 315 formed in the passivation layer 305 have been described above, in order to perform the function of the passivation layer 305 described above and to perform the function of the gap 315, that is, forming a pn diode In order to enable the collection of electrons and holes by the internal field effect through the gap, the size of the gaps 315 and the distance between neighboring pores need to be properly adjusted.

Although the thickness of the passivation layer 305 is preferably several nm, the thickness of the passivation layer 305 may be freely determined in the range of several tens nm, specifically, about 1 to 90 nm.

Referring again to FIG. 3A, a transparent conductive film layer 320 is formed on the second type silicon layer 310, and an upper electrode 330 having a solar cell connected to an external conductor on the transparent conductive film layer 320. It is formed while maintaining a constant interval for the incident of light incident from the outside.

The lower electrode 340 of the solar cell of the present invention is formed on the lower surface of the first type silicon base substrate 300, and the upper electrode 330 and the lower electrode 340 described above are both metal having excellent electrical conductivity, For example, it forms using Al, Pt, Au, Cu, etc.

3B is a cross-sectional view of a heterojunction silicon solar cell according to another embodiment of the present invention.

In FIG. 3B, the same reference numerals as used in FIG. 3A denote the same members. Therefore, in FIG. 3B, the same reference numerals as in FIG. 3A will be interpreted with reference to FIG. 3A, and only the points distinguishing from FIG. 3A will be described below.

Referring to FIG. 3B, the second type silicon layer 310 is not formed on the gap 315 and the passivation layer 305, but is formed only inside the gap 315.

That is, since the second type silicon layer 310 only needs to form a pn junction with the lower base substrate 300, it is not necessary to form a thick layer, and even if the second type silicon layer 310 is formed only at the portion of the gap 315 that can form the pn junction. The effect expected in the present invention will be obtained.

5A to 5F are process cross-sectional views illustrating a method of manufacturing a heterojunction silicon solar cell according to the present invention.

5A to 5B, the same reference numerals as used in FIG. 3 denote the same members.

Therefore, in interpreting FIGS. 5A to 5F, reference numerals similar to those of FIG. 3 will be referred to FIG. 3.

To fabricate the heterojunction silicon solar cell according to the present invention as shown in FIG. 5A, first, a passivation layer 305 is formed on the first type crystalline silicon base substrate 300.

Next, as shown in FIG. 5B, a photoresist film is coated on the passivation layer 305, and the photoresist pattern 311 is exposed to expose the passivation layer 305 to be etched through exposure and development. To form.

At this time, the photoresist film to be used may be a positive type or a negative type, but a positive type photoresist is preferably used for ease of processing.

Positive photoresist means that the portion to which light is irradiated during the exposure process is softened and then removed in the developing process.

Next, the exposed passivation layer 305 is etched using the photoresist pattern 311 as an etching mask.

At this time, the etching may be dry etching or wet etching, but although the etching surface is not smooth due to isotropy etching, the wet etching with excellent selectivity is excellent. It is preferable to use.

The etching process is performed until all of the exposed passivation layer 305 is etched to expose the lower first type silicon base substrate 300.

Therefore, if the wet etching process is used in the above process, the etchant used in the etching process may be a solution having high selectivity to the passivation layer 305 and low selectivity to the crystalline silicon substrate.

Next, as shown in FIG. 5D, when the photoresist pattern 311 is removed, the passivation layer 305 having the void 315 exposing the lower first type silicon base substrate 300 is left. do.

As the method for forming the pores, the etching process may be performed using a photoresist, and various patterning methods using a nanoimprint process and a self-aligned organic material may be applied.

Next, as shown in FIG. 5E, the second type amorphous silicon is deposited on the passivation layer 305 to form the second type amorphous silicon layer 310.

In this case, the second type amorphous silicon material is deposited on the first type silicon base substrate 300 layer exposed by the gap 315 and the upper portion of the passivation layer 305, and if the deposition time is maintained, the voids 315 are all filled with a second type amorphous silicon material, and have a structure as shown in FIG. 5E.

However, if the order of the process of 5d and 5e is changed, that is, when the second type of amorphous silicon material is deposited in the state where the photoresist pattern 311 is present, the photoresist pattern is removed, FIG. As described above, a structure in which the second type silicon material is not formed on the upper portion of the passivation layer 305 while forming a pn junction only in the cavity 315 is obtained.

Next, as shown in FIG. 5F, the transparent conductive film 320 is formed on the second type silicon layer 310 by using a material such as indium tin oxide (ITO) or aluminum-doped zinc oxide (AZO). The upper metal electrode 330 is formed on the transparent conductive film 320 while maintaining a constant interval by using a shadow mask or screen printing. Finally, the lower electrode 340 is disposed below the first type silicon base substrate 300. ), The heterojunction silicon solar cell according to the present invention is completed.

Hereinafter will be described with reference to specific experimental examples that the stability and reproducibility of the efficiency is very excellent when the heterojunction silicon solar cell according to the embodiments of the present invention. Details not described herein are omitted because they can be sufficiently inferred by those skilled in the art.

<Example>

After the p-type silicon substrate (1 ~ 2Ωcm) was surface treated by RCA method, the natural oxide film was removed with dilute hydrofluoric acid and wet annealed at about 850 ° C in the furnace to have a thickness of 30 nm on the front and back. An SiO ₂ film was formed as the passivation film.

Thereafter, a positive photoresist was applied on the SiO ₂ film on the entire surface of the silicon substrate to a thickness of about 1 μm, and only a predetermined portion was exposed using a photomask and then developed.

The photoresist pattern formed through this process was used as an etching mask, and the SiO ₂ film was etched by wet etching using an etching solution, and then the photoresist was removed.

Subsequently, the patterned silicon substrate was etched in HF: H ₂ O (1: 100) solution for about 30 seconds to remove the exposed SiO _2, and then placed in a plasma chemical vapor deposition apparatus (PECVD), followed by H ₂ , SiH ₄ , and PH _3. N-type amorphous silicon was deposited by about 10 nm using a mixed gas.

Thereafter, ZnO, a transparent conductive oxide film, was deposited on the amorphous silicon by about 80 nm using a spattering method.

Ag was deposited on the transparent conductive oxide film by using a shadow mask at a constant interval of 1 μm by thermal evaporation, and finally, Al was 500 nm on the back electrode.

Areas outside the 1 cm x 1 cm area were wet-etched to remove ZnO and wet-etched amorphous silicon (a-Si) using Reactive Ion Etching (RIE).

Comparative Example

After the RCA surface treatment using the same silicon p-type wafer as in Example, the exposed SiO ₂ was etched in HF: H ₂ O (1: 100) solution for about 30 seconds, and then placed in a plasma chemical vapor deposition apparatus (PECVD). N-type amorphous silicon was deposited by about 10 nm using H ₂ , SiH ₄ , PH ₃ mixed gas.

After that, ZnO, a transparent conductive oxide film, was deposited on the amorphous silicon by about 80 nm by using a spattering method, and Ag was used as a thermal evaporation method with a front electrode that maintains a constant interval using a shadow mask thereon. After evaporation, Al was finally raised to about 500 nm with the back electrode.

Areas outside the 1 cm x 1 cm area were removed by dry etching with ZnO by wet etching and a-Si using RIE for accurate area definition.

In order to reduce all errors, the samples of Examples and Comparative Examples were simultaneously made from amorphous silicon deposition through a plasma chemical vapor deposition apparatus.

6 is a scanning electron microscope (SEM) and transmission electron microscope (TEM) photograph showing a plan view (left) of the surface of a patterned passivation layer prepared according to the above embodiment, and a cross-sectional shape (right) of a solar cell made using the same. to be.

Referring to FIG. 6, the plane of the patterned silicon wafer spaced at regular intervals for p / n formation is shown well, and in the cross-section, the region of the silicon passivated by SiO ₂ and the region of amorphous silicon, which is formed by amorphous / crystalline contact, amorphous silicon And the interface of the transparent conductive oxide film.

  Table 1 shows the results of the conversion efficiency of the solar cell produced by the above Examples and Comparative Examples.

Referring to Table 1, in the case of the solar cell of the embodiment, despite the reduction of the open circuit voltage (Voc) and the short-circuit current density (Jsc), compared to the comparative example, a slightly better efficiency due to the increase of the fill factor (FF) It can be seen that the characteristics of.

In addition, as a result of fabricating and comparing several samples, the solar cell manufactured according to the example showed stability of stability and reproducibility.

7 is a graph illustrating changes in spectral response characteristics according to wavelengths of light in a silicon solar cell manufactured according to an embodiment and a solar cell manufactured according to a comparative example.

Referring to FIG. 7, it can be seen that the embodiment shows a slightly lower response in the short wavelength region due to the decrease in the depletion layer region due to the decrease in the p / n contact region, but shows a higher spectral response characteristic in the long wavelength region. .

This shows that in the bulk region, the embodiment contributes to the short circuit current density due to the increase in the spectral response characteristic.

This characteristic can be attributed to the increase of the injected energy with the decrease of reflectivity and the reduction of the re-defect rate due to surface passivation.

Referring to this, it can be seen that the effect of passivation of the crystalline surface contributes to the improvement of efficiency with the reduction of surface defects, the improvement of pn diode characteristics, and the increase of FF.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings and tables, the present invention is not limited to the above embodiments, but may be manufactured in various forms, and common knowledge in the art to which the present invention pertains. Those skilled in the art can understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the heterojunction silicon solar cell according to the embodiment of the present invention, by minimizing the contact area between amorphous and crystalline silicon, interface defects can be reduced, and the solar cell can be improved through pn diode characteristics through minimum point contact or partial surface contact. Increased filling rate and improved efficiency.

Claims (17)

A second type amorphous silicon layer is formed on the first type crystalline silicon wafer, a transparent conductive film and an upper electrode are formed on the second type amorphous silicon layer, and a lower electrode is formed on the bottom surface of the first type crystalline silicon wafer. In the heterojunction silicon solar cell having a structure, At the interface between the first type crystalline silicon wafer and the second type amorphous silicon layer, a plurality of pores penetrating the front and rear surfaces thereof are formed, so that the first type crystalline silicon wafer and the second type are only through the pores. A heterojunction silicon solar cell, characterized in that a passivation layer is inserted to allow the type silicon layer to contact. The method of claim 1, Wherein said first type is p-type and said second type is n-type. The method of claim 1, The first type is n-type, the second type is a heterojunction silicon solar cell, characterized in that. The method of claim 1, The passivation layer is a heterojunction silicon solar cell, characterized in that selected from SiO ₂ , SiC, SiN _x , intrinsic amorphous silicon. The method of claim 1, The portion of the passivation layer occupied by the voids is a heterojunction silicon solar cell, characterized in that more than 0% to 50% or less of the total surface area. The method of claim 1, Heterojunction silicon solar cells, characterized in that the distance between the center of the adjacent gaps of the passivation layer is 1nm ~ 9㎛. The method of claim 1, The shape of the void is a heterojunction silicon solar cell, characterized in that triangular, square, circular, oval, polygonal. The method of claim 1, The passivation layer is a heterojunction silicon solar cell, characterized in that the thickness of 1 ~ 90nm. (a) forming a passivation layer on the first type crystalline silicon substrate; (b) forming a photoresist pattern by applying a photoresist film on the passivation layer and then removing a portion of the photoresist film to expose a portion of the passivation layer through an exposure and development process; (c) removing the passivation layer exposing the photoresist pattern with an etch mask to form a plurality of pores to expose the surface of the first type silicon substrate under the passivation layer; And (d) depositing a second type of amorphous silicon on the passivation layer in which the voids are formed. The method of claim 9, Wherein said first type is p-type and said second type is n-type. The method of claim 9, The first type is n-type, the second type is a method of manufacturing a heterojunction silicon solar cell, characterized in that the p-type. The method of claim 9, The passivation layer is a method of manufacturing a heterojunction silicon solar cell, characterized in that selected from SiO ₂ , SiC, SiN _x , intrinsic amorphous silicon. The method of claim 9, The voids occupy the passivation layer in a method of manufacturing a heterojunction silicon solar cell, characterized in that more than 0% to 50% or less of the total surface area. The method of claim 9, The method of manufacturing a heterojunction silicon solar cell, characterized in that the distance between the centers of the mutually adjacent pores of the passivation layer is 1nm ~ 9㎛. The method of claim 9, The voids are triangular, rectangular, circular, oval, polygonal manufacturing method of a heterojunction silicon solar cell, characterized in that. The method of claim 9, The passivation layer is a thickness of 1 ~ 90nm manufacturing method of a heterojunction silicon solar cell, characterized in that. The method of claim 9, Forming the voids is a method of manufacturing a heterojunction silicon solar cell, characterized in that performed using any one selected from a method using a photoresist, nano-imprint and nano-patterning method using a self-arranged polymer.

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