JP3872428B2 - Manufacturing method of solar cell - Google Patents

Abstract

A solar cell includes a semiconductor substrate (1) with irregularities on its principal surface covered with an insulating layer (3) such that it covers some of the projections of the irregularities, that is, uncovered areas (5) are formed on the principal surface. An output electrode (7) is connected directly, or through a conducting layer, with tops (25) of projections (15) in the exposed semiconductor areas (5). The exposed semiconductor areas (5) is formed by applying insulating film (3) to cover projections (15) on the principal surface of the semiconductor substrate (1), applying etch resist (4) to cover the insulating film (3) in the areas except the peaks (25) of the projections (15), and etching the insulating film (3) to expose the peaks (25) of the projections (15).

Description

実施例品１及び実施例品２では、半導体表層部２であるエミッタ層のシート抵抗を２００Ω／□に設定できた。他方、ファイヤースルー方式を用いた比較例品では、該シート抵抗は４０〜５０Ω／□であった。そして、表１に示すように、比較例品に比べて実施例品１及び実施例品２では、フィルファクタが減少していないことがわかる。これは、実施例品１及び実施例品２において透明導電層のシート抵抗が低く、コンタクト抵抗の増加が抑制されたためであると考えられる。
また、比較例品と比べた場合、実施例品１及び実施例品２では開放電圧が大幅に向上している。これは、エミッタ層のドーパント濃度が低減され、表面再結合速度が低減されたたことと、半導体層露出領域５に基づくコンタクトホールの面積を制限できたための結果であると考えられる。なお、実施例品１及び実施例品２に使用した基板１は、走査型電子顕微鏡（ＳＥＭ）による表面観察から、半導体層露出領域５の第一主表面における合計面積率は、おおよそ１％となっていることを確認した。
比較例品と比べた場合、実施例品１及び実施例品２では短絡電流も増加している。これは、シャドーイングロスの低減と短波長感度の増加によるものと考えられる。比較例品では電流はエミッタ層内を横方向に流れるが、本実施例では代わりに透明導電層６内を流れる。透明導電層６のシート抵抗は約１０Ω／□であり、比較例品と比べて、電極ピッチを例えば２倍にしても同程度の抵抗ロスで済む。よって、シャドーイングロスを半分にでき、これが短絡電流の増加に大きく寄与したものと考えられる。また、図１５に示すように、実施例品１及び実施例品２は短波長感度も増大していることがわかる。これは上記説明したように、エミッタ層のドーパント濃度が低くなり、表面再結合速度が低減されたことによる。
そして、実施例品１及び実施例品２では、開放電圧、短絡電流及びフィルファクタが各々増加したことにより、２０％前後の変換効率を得ることができた。特に、裏面側にＢＳＦ層を導入した実施例品２では変換効率が２０％を越える太陽電池が得られた。
なお、本実施例における太陽電池では、裏面全面に電極を形成しているが、裏面側にも表面同様、透明導電膜と櫛形電極を形成し、裏面側からも光が入射する構造にしても構わない。また、２００Ω／□のｎ型拡散層を形成したが、１００Ω／□より高い値にできれば、短波長感度が増大し、太陽電池特性が向上する。さらに、作製プロセスにおいて、本実施例では絶縁膜として酸化膜（二酸化珪素膜）を利用したが、窒化珪素膜でも構わない。また、拡散層の形成には熱拡散法を用いたが、イオン打ち込み法やスピンオン法など、本発明の構造が形成可能であれば、いかなる手段を用いることも可能である。
（実験例２）
図５に示す構造の太陽電池１０３を以下のようにして作製した。まず、ＣＺ法にて作製したｐ型単結晶シリコン基板１（厚さ２５０μｍ、抵抗率０．５Ω・ｃｍのガリウムドープ品）を用意し、実験例１と同様にダメージ層をエッチングした後、両面にランダムテクスチャ面を形成した。テクスチャ形成後、Ｐ_２Ｏ_５を含有する塗布剤を塗布し、８５０℃で熱拡散を行い、表面にシート抵抗が約１００Ω／□のｎ型拡散層２を形成した。
その後、８００℃でパイロジェニック酸化を行い、さらに、実験例１と同様の方法で半導体層露出領域５を形成した。この後、実験例１と同様の出力取出用電極７，８を第一及び第二主表面にそれぞれ形成した。続いて、反射防止膜を兼ねた補助絶縁膜１０として窒化珪素膜をプラズマＣＶＤによって形成し、太陽電池１０３を完成させた（実施例品３）。この際、基板温度は４００℃に設定し、膜堆積後に、実験例１と同様の水素アニール処理を行った。該実施例品３について、実験例１と同様に性能評価試験を行なった。結果を表２に示す

これによると、実施例品３では、前述の実施例品１及び２と比較して短絡電流が減少し、一方で、開放電圧が増加していることがわかる。短絡電流が減少した原因は電極幅、電極ピッチが従来方式のものと変わらないためであると考えられる。つまり、表１に示した実施例品１及び２と比較してシャドーイング面積が増加したことによる。一方、開放電圧が増加した理由は、基板抵抗率を２．０Ω・ｃｍから０．５Ω・ｃｍに下げたことによるものと考えられる。一般的に基板抵抗率を下げると逆飽和電流密度が減少し、開放電圧は増加する。しかし、ｐ型基板において抵抗率が２．０Ω・ｃｍ程度の場合、光劣化の問題を検討しておく必要がある。光劣化とは、太陽電池セルに強い光を照射すると太陽電池基板のライフタイムの低下が起こり、十分な変換効率を得ることができなくなる現象である。
この光劣化の有無を調べるために、上記ガリウムドープＣＺシリコン単結晶基板を用いて作製した太陽電池と、通常のボロンドープＣＺシリコン単結晶基板（抵抗率０．５Ω・ｃｍ）を用いた以外は全く同様の方法にて作製した太陽電池とを、２５℃にて、上記ソーラーシミュレータの下で疑似太陽光を照射し続け、電流電圧特性の光照射時間依存性を調べた。その結果、ボロンドープ基板から作製された太陽電池は擬似太陽光下で１０時間照射すると、１割程度の変換効率の劣化がみられた。それに対し、ガリウムドープ基盤を用いた太陽電池は、若干の変換効率の変動が見られたが、劣化に相当する特性の変化は見られなかった。このように、ガリウムドープ基板を利用することで光劣化の問題は回避でき、開放電圧と変換効率を改善することができた。なお、本実施例ではＣＺ法によるガリウムドープのｐ型基板を利用したが、格子間酸素濃度を数ｐｐｍ以下としたＭＣＺ基板、ＦＺ基板でも光劣化問題は回避可能である。また、ｎ型基板を用い、ボロン等を用いてｐ型のエミッタ層を形成しても光劣化問題は回避可能である。
（実験例３）
図６に示す太陽電池１０４を以下のようにして作製した（なお、図６では煩雑となることを避けるため、凹凸部及び反射防止膜を描かずに、表面近傍の部分のみを示した）。まず、ＣＺ法にて作製したｐ型単結晶シリコン基板１（厚さ２５０μｍ、抵抗率２Ω・ｃｍのボロンドープ品）を用意し、ダイサを用いて、第一主表面に断面が三角形をしたリブ状の凸部４５，４５を２ｍｍ間隔で形成した（凸部４５，４５の間の領域は凹部とみなすことができる）。この際、基板１の第一主表面から各凸部４５，４５の頂上までの高さを約３０μｍとした。
次に、ダメージ層を化学エッチングした後、両主表面に凹凸部として、高さ５μｍ程度のランダムテクスチャ構造を形成した。その後、実験例２と同様に熱拡散を行い、表面にシート抵抗が約１００Ω／□のｎ型拡散層２を形成し、続いて、熱酸化を行うことにより絶縁膜３としての酸化膜を形成した。そして、第二主表面側に実験例１と同様の方法によりエッチング保護膜を形成する一方、第一主表面にはエッチング保護膜として、ゴム系樹脂からなる耐フッ酸仕様の印刷レジストを、厚さ２０μｍとなるようにスクリーン印刷を用いて塗布した。こうすることにより、最初にダイサで形成した凸部４５，４５の頂上部２５が稜線方向に周期的に印刷レジスト表面から突き出ることになる。
レジストを乾燥後、１０質量％フッ酸水溶液に基板１を浸漬し、凸部４５，４５の頂上部２５に半導体層露出部５を形成した。次いで、溶媒を用いてレジストを洗い流した後、スクリーン印刷法により、第一主表面には銀ペーストを用いて図６に示す出力取出用電極７のパターンを、第二主表面にはアルミニウムペーストを用いて全面に出力取出用電極８のパターンを形成した。この時、第一主表面側の出力取出用電極７は、凸部４５，４５の頂上の半導体層露出部５に重なる形で印刷されるよう、位置合わせする必要があるが、コンタクト幅に対して電極７の幅が半導体層露出部５の幅の１０倍程度あるため、比較的ラフに位置合わせが可能である。続いて、反射防止膜としてＴｉＯ_２膜（図示せず）を常圧ＣＶＤによって６０ｎｍの厚さに形成し、太陽電池１０４を完成させた（実施例品４）。
該実施例品４の性能評価を実験例１と同様に行なったところ、開放電圧０．６６７Ｖ、短絡電流密度３６．９ｍＡ／ｃｍ^２、フィルファクタ０．７７０、変換効率１９．０％が得られ、従来のスクリーン印刷／ファイヤースルー方式より特性が向上した。
【図面の簡単な説明】
図１Ａは、本発明に係る太陽電池の第一例の断面構造を示す模式図。
図１Ｂは、本発明に係る太陽電池の第二例の断面構造を示す模式図。
図２Ａは、半導体基板に形成する凹凸部の形態の第一例を示す斜視図。
図２Ｂは、同じく第二例を示す斜視図。
図２Ｃは、同じく第三例を示す斜視図。
図３は、実験例における太陽電池の製造工程を示すフローチャートである。
図４Ａは、本発明における半導体層露出領域の形成方法を示す工程説明図。
図４Ｂは、図４Ａに続く工程説明図。
図４Ｃは、図４Ｂに続く工程説明図。
図４Ｄは、図４Ｃに続く工程説明図。
図５は、実験例２で用いた太陽電池の断面構造を示す模式図。
図６は、実験例３で用いた太陽電池の要部を拡大して示す斜視図。
図７Ａは、本発明の太陽電池の、要部断面構造の第一例を示す模式図。
図７Ｂは、同じく第二例を示す模式図。
図７Ｃは、同じく第三例を示す模式図。
図７Ｄは、同じく第四例を示す模式図。
図７Ｅは、同じく第五例を示す模式図。
図７Ｆは、同じく第六例を示す模式図。
図７Ｇは、同じく第七例を示す模式図。
図８Ａは、塗布液を用いてエッチング保護膜を段階的に厚く形成する例を示す工程説明図。
図８Ｂは、図８Ａに続く工程説明図。
図８Ｃは、図８Ｂに続く工程説明図。
図８Ｄは、図８Ｃに続く工程説明図。
図９Ａは、塗布液の粘度とエッチング保護膜の形成状態との関係を説明する図。
図９Ｂは、図９Ａに続く説明図。
図９Ｃは、図９Ｂに続く説明図。
図９Ｄは、図９Ｃに続く説明図。
図１０Ａは、エッチング保護膜の形成形態と、半導体層露出部の形成態様との関係を例示して示す断面模式図。
図１０Ｂは、同じく別例を示す断面模式図。
図１１Ａは、透明導電層を組み込んだ本発明の太陽電池の、製造工程の第一例を示す断面模式図。
図１１Ｂは、同じく第二例を示す断面模式図。
図１１Ｃは、同じく第三例を示す断面模式図。
図１２は、透明導電層を組み込んだ本発明の太陽電池における、出力取出用電極の形成態様の変形例を示す断面模式図。
図１３Ａは、透明導電層の有無による、表層部を流れる電流経路の違いを説明する図。
図１３Ｂは、図１３Ａに続く説明図。
図１４は、実験例１における各太陽電池の電流電圧特性を示すグラフ。
図１５は、同じく内部量子効率と波長との関係を示すグラフ。
図１６は、ｐ−ｎ接合を利用した太陽電池の原理説明図。
図１７は、受光面側における出力取出用電極の形成形態の一例を模式的に示す斜視図。
図１８は、太陽電池の電流電圧曲線の説明図。
図１９Ａは、本発明と従来方法との半導体層露出部の形成形態の違いを対比して説明する模式図。
図１９Ｂは、図１９Ａに続く説明図。Technical field
The present invention relates to a solar cell that has relatively high photoelectric conversion efficiency and can be manufactured at low cost, and a method for manufacturing the solar cell.
Background art
A solar cell is a semiconductor element that converts light energy into electric power, and includes a pn junction type, a pin type, and a Schottky type, and the pn junction type is most widely used. When solar cells are classified based on their substrate materials, there are roughly three types: silicon crystal solar cells, amorphous (amorphous) silicon solar cells, and compound semiconductor solar cells. Silicon crystal solar cells are further classified into single crystal solar cells and polycrystalline solar cells. Among these, the compound semiconductor solar cell has the highest energy conversion efficiency, but it is very difficult to make a compound semiconductor as a material of the compound semiconductor solar cell, and the manufacturing cost of the solar cell substrate is low. In general, there is a problem in widespread use, and its use is limited. On the other hand, as a solar cell having the next highest conversion efficiency after a compound semiconductor solar cell, a silicon single crystal solar cell follows, and a silicon single crystal substrate for a solar cell can also be manufactured relatively easily. It has become the mainstay of batteries.
The output characteristics of a solar cell are generally evaluated by measuring an output current voltage curve as shown in FIG. 18 using a solar simulator. On this curve, the point Pm at which the product Ip · Vp of the output current Ip and the output voltage Vp is maximum is called the maximum output Pm, and the total light energy (S × I: S is the element) incident on the solar cell. Area, I is the value divided by the intensity of the irradiated light):
η≡ {Pm / (S × I)} × 100 (%) (1)
Is defined as the conversion efficiency η of the solar cell. As is apparent from FIG. 18, in order to increase the conversion efficiency η, the short-circuit current Isc (output current value when V = 0 on the current-voltage curve) or the open circuit voltage Voc (also output voltage when I = 0). It is important to increase the value) and to make the output current voltage curve as close to a square as possible. Note that the degree of squareness of the output current voltage curve is generally
FF≡Ipm × Vpm / (Isc × Voc) (2)
It means that the output current-voltage curve approaches an ideal square shape and the conversion efficiency η increases as the value of the FF is closer to 1.
For example, in a silicon crystal solar cell, in order to prevent the recombination of electrons and holes in the direct contact portion between the metal electrode for output extraction and the silicon layer and increase the open-circuit voltage Voc, the surface of the silicon layer is made of SiO. ₂ A structure for forming an insulating film such as MIS contact or contact passivation is employed. However, if the entire surface of the silicon layer is covered with the insulating film as described above, the generated photocurrent must pass through the insulating film by the tunnel effect, and the photocurrent collection rate is sufficiently lowered. Improvement in conversion efficiency cannot be expected.
In order to prevent this, a small contact hole is provided in a part of the insulating film, and by forming a metal electrode here, the direct contact portion between the metal electrode that acts as a recombination site and the silicon layer is limited to a minute region. In order to improve the photocurrent collection rate, it has been carried out. In this case, how to form a contact hole in the insulating film becomes a problem. For example, in a laboratory, a method of forming a contact hole by using a photoresist or the like and etching an insulating film can be considered. However, this method requires too much man-hours and costs for using the photolithography technique, and is not practical from the viewpoint of mass production of solar cells.
In view of this, Japanese Patent Application Laid-Open No. 8-335711 proposes a method for forming a contact hole without using a photolithography technique. Specifically, the pattern of the metal electrode for output extraction is formed on the insulating film by screen printing of a conductive paste, and further fired. As a result, the metal and glass frit contained in the paste are melted by heat, and the contact hole is formed by breaking through the insulating film and reaching the emitter layer. This method is generally referred to as fire-through, and can be easily formed as a contact hole. Therefore, this method is widely used in the production of single crystal or polycrystalline solar cells.
By the way, in the solar cell manufacturing method by a fire through system, it is necessary to set the dopant concentration of the emitter layer which is a surface n-type layer high. This is because when the dopant concentration of the emitter layer is low, the contact resistance of the direct contact portion between the metal and silicon formed by fire-through is not sufficiently lowered, and the contact resistance loss is increased and the power that can be extracted is reduced. Because. However, when the dopant concentration in the emitter layer is increased by diffusion, a compound of semiconductor silicon and a dopant is precipitated, many defect levels are formed on the surface, and the surface recombination rate is increased. If it becomes such a state, the short wavelength sensitivity of a solar cell will become low, and the malfunction which the electric current which can be taken out becomes small will arise.
On the other hand, in order to increase the conversion efficiency η of the solar cell, it is also important to reduce the shadowing loss by reducing the formation width of the output extraction metal electrode as much as possible. However, since the electrodes are formed by screen printing in the fire-through method, it is theoretically difficult to make the electrode width extremely small. As a result, in order to reduce the shadowing loss, the arrangement interval of the plurality of electrodes to be formed is reduced. It must be wide. If the electrode arrangement interval is increased in this way, the lateral conduction distance in the thin emitter layer becomes longer at the time of current extraction, so that the emitter resistance loss increases and the conversion efficiency η has to be reduced. For these reasons, it is considered difficult to produce a solar cell having a good conversion efficiency η, for example, a solar cell having η exceeding 20% by adopting the fire-through method.
An object of the present invention is to provide a solar cell that can be manufactured at a low cost with high conversion efficiency, and a manufacturing method thereof.
Disclosure of the invention
In order to solve the above problems, the first configuration of the solar cell of the present invention is a solar cell in which an uneven portion is formed on the main surface of a semiconductor substrate, and the main surface is covered with an insulating film. A semiconductor layer exposed region that is not covered with an insulating film is formed on the main surface so as to include the top of at least a part of the convex portion forming the convex portion, and the convex portion is formed in the semiconductor layer exposed region. The tip height position of the top is higher than the maximum height position of the insulating film at the outer peripheral edge of the semiconductor layer exposed region, and is directly or other conductive on the top of the convex portion in the semiconductor layer exposed region. The output extraction electrode is formed so as to be indirectly contacted through the layer.
In the present specification, the main surface of the semiconductor substrate means at least one of both surfaces (front surface and back surface) in the thickness direction of the semiconductor substrate. Therefore, the uneven portion may be formed only on one main surface of the substrate, or may be formed on both surfaces. Further, in this specification, the semiconductor layer exposed region includes not only the case where the insulating film is completely removed but also the case where the insulating film having a thickness (about 3 nm or less) through which a tunnel current flows remains.
In the solar cell having the first configuration, the uneven portion is formed on the main surface of the semiconductor substrate. Such concavo-convex portion formation has been employed in conventional silicon single crystal solar cells mainly for the purpose of preventing reflection loss. However, in the present invention, the uneven portion is used not only for the purpose of preventing reflection loss but also for its unique form to form a semiconductor layer exposed region that should function as a contact hole between the output extraction electrode and the semiconductor layer. There is a feature. Specifically, as illustrated in FIG. 19A, the semiconductor layer exposed region 5 is formed so as to include the top portion 25 of the convex portion 15, and the tip height position of the convex portion 15 is the semiconductor layer. It is set higher than the maximum height position of the insulating film 3 at the outer peripheral edge of the exposed region 5. Then, the output extraction electrode 7 is formed so as to be in direct contact (or indirectly through another conductive layer) with the top 25 of the convex portion 15 in the semiconductor layer exposed region 5.
For example, in a contact hole formed by photolithography or fire-through in a conventional solar cell, as shown in FIG. 19B, the semiconductor layer exposed region 5 forms a bottom surface of the contact hole, and the semiconductor in the exposed region 5 The layer 2 can never protrude beyond the upper edge of the surrounding insulating film 3. In this respect, the structure of the solar cell according to the first aspect of the present invention is decisively different from the structure of these conventional solar cells. By adopting such a structure, there is an advantage that the semiconductor layer exposed region 5 can be very easily formed by the method for manufacturing a solar cell of the present invention described below.
That is, the method includes a step of forming an uneven portion on the main surface of the semiconductor substrate;
Covering the main surface of the semiconductor substrate with an insulating film in a form including irregularities;
A step of covering the insulating film with an etching protective film in a region other than the top of the convex portion forming the concave and convex portions;
Thereafter, the insulating film on the top of the convex portion is removed by etching, thereby forming a semiconductor layer exposed castle that is not covered with the insulating film so as to include the top of at least a part of the convex portion. When,
Forming an output extraction electrode so as to contact the top of the convex portion in the semiconductor layer exposed region directly or indirectly through another conductive layer;
It is characterized by including.
In addition, the second configuration of the solar cell according to the present invention captures the characteristics of the solar cell of the present invention from the viewpoint of the above-described manufacturing method. The main surface of the semiconductor substrate is formed with uneven portions, and the main surface is insulated. A semiconductor layer exposed region that is covered with a film and that is not covered with an insulating film is formed on the main surface so as to include the tops of at least some of the convex portions that form the concave and convex portions, and the semiconductor layer In the solar cell in which the electrode for output extraction is formed so as to contact the top of the convex portion in the exposed region directly or indirectly through another conductive layer,
The semiconductor layer exposed region is formed by covering the main surface of the semiconductor substrate with an insulating film so as to include a concavo-convex portion, and further covering the insulating film with an etching protective film in a region other than the top portion of the convex portion, and then projecting the convex portion by etching. It is characterized by being formed by removing the insulating film at the top.
In other words, according to the above method, the main surface of the semiconductor substrate 1 shown in FIG. 4A is covered so that the region excluding the top 25 of the convex portion 15 formed on the main surface is covered as shown in FIG. 4B. For example, the etching protection film 4 is formed so that the convex portion 15 is buried partway in the height direction and only the top portion protrudes. Then, as shown in FIG. 4C, by performing etching thereafter, only the insulating film 3 on the top portion 25 of the convex portion 15 protruding from the etching protection film 4 is selectively removed. As a result, the semiconductor layer exposed region 5 described above is formed so as to include the top 25 of the convex portion 15. As shown in FIG. 4D, the tip height position of the protrusion 15 is higher than the maximum height position 11 of the insulating film 3 at the outer peripheral edge of the semiconductor layer exposed region 5.
The etching protection film 4 can use a general-purpose polymer resist having no photosensitivity, and in order to form the above-described covering state, it is only necessary to set the formation thickness of the etching protection film 4 appropriately. Once such a covering state is formed, the semiconductor layer exposed region 5 can be easily formed simply by immersing the substrate in an appropriate etching solution, for example. Therefore, a troublesome and labor-intensive photolithography technique is not required at all, and, of course, no fire-through is required. Therefore, a good ohmic contact can be obtained without increasing the dopant concentration on the substrate surface. This can increase the fill factor of the solar cell. Moreover, since the dopant concentration on the surface can be lowered, the short wavelength sensitivity of the solar cell is increased, and the short-circuit current can be improved. In this way, a high-performance solar cell with high conversion efficiency can be realized.
Next, in a third configuration of the solar cell according to the present invention, in the solar cell in which the main surface of the semiconductor substrate is covered with an insulating film, a semiconductor layer exposed region that is not covered with the insulating film is formed on the main surface. Thus, a transparent conductive layer that collectively covers the semiconductor layer exposed region and the insulating film is formed, and an output extraction electrode is formed on the transparent conductive layer.
In this configuration, a semiconductor layer exposed region functioning as a contact hole is formed in the insulating film, and a transparent conductive layer is formed to collectively cover the semiconductor layer exposed region and the insulating film. Then, an output extraction electrode is formed on the transparent conductive layer. When such a transparent conductive layer is not provided, as illustrated in FIG. 13A, the current generated on the semiconductor substrate 1 side flows in the lateral direction through the substrate surface layer portion (for example, the emitter layer) 2 having a relatively high resistivity. Thereafter, the output is taken out from the output extraction electrode 7, so that the series resistance is increased and loss is easily generated. However, according to the solar cell according to the third configuration of the present invention, as illustrated in FIG. 13B, the current from the semiconductor layer exposed region 5 has a relatively high conductivity (that is, a relatively low resistivity). After flowing through the transparent conductive layer 6 in the lateral direction, it can be taken out from the output extraction electrode 7. Therefore, it is possible to greatly reduce the resistance loss when the current flows in the lateral direction. For example, in FIG. 13A, all of the distance LP1 to the output extraction electrode 7 must be a lateral conduction path in the substrate surface layer portion 2, but in FIG. 13B, the presence of the output extraction electrode 7 exists. Regardless of the presence or absence, it is sufficient that a current flows from the nearest semiconductor layer exposed region 5 to the transparent conductive layer 6, so that the lateral conduction length LP2 is significantly shorter than the lateral conduction length LP1 of FIG. 13A. It is clear that As another effect, since the transparent conductive layer is formed, shadowing loss due to the transparent conductive layer itself hardly occurs. Thus, the short circuit current and conversion efficiency of the solar cell can be improved.
In particular, when the output extraction electrode is formed by general-purpose screen printing, the width of the output extraction electrode 7 is increased. Therefore, it is necessary to widen the formation interval in order to reduce shadowing loss. As shown in FIG. 13A, in the case where a transparent conductive layer is not provided, an increase in series resistance due to a lateral current becomes a problem, but in the third configuration of the solar cell according to the present invention, as shown in FIG. Since the transparent conductive layer 6 functions as a lateral conduction path, the influence of the problem can be drastically reduced. In addition, when the series resistance increases, there is a certain limit to increase the formation interval of the output extraction electrodes. On the other hand, the solar cell according to the third configuration of the present invention is provided on the transparent conductive layer 6. Even if the formation interval of the output extraction electrodes 7 and 7 is considerably large, the series resistance is not so high, and as a result, the shadowing loss can be further reduced.
Further, in the present invention, since it is not necessary to flow a current laterally in the substrate surface layer portion (for example, the emitter layer), even when the sheet resistance is increased, for example, when an n-type emitter layer is formed, the sheet resistance is set to 100Ω. There is no problem even if it is much higher than / □. That is, it is possible to further reduce the dopant concentration in the surface layer portion of the substrate. As a result, the surface recombination rate can be further reduced, and the conversion efficiency can be increased.
The third configuration of the solar cell according to the present invention can be combined with the first configuration or the second configuration described above. In this case, as shown in FIG. 13B, the output extraction electrodes 7 and 7 can be formed at positions corresponding to the convex portions 15 scattered in various places on the main surface of the substrate. On the other hand, the third configuration can be implemented independently of the first or second configuration. In FIG. 7E, the convex portion 15 is not formed on the main surface of the substrate 1, and the semiconductor layer exposed portion 35 is formed on the insulating layer 3 by photolithography or the like.
Next, a fourth configuration of the solar cell according to the present invention is a solar cell in which the main surface of the semiconductor substrate is covered with an insulating film, and a plurality of semiconductor layer exposed regions not covered with the insulating film are provided on the main surface. In some of the exposed regions of the semiconductor layer, the output extraction electrode is formed in direct contact with the semiconductor layer, while the remaining semiconductor layer exposed region where the output extraction electrode is not formed is transparent. It is characterized by being covered with an insulating layer.
In the configuration of the solar cell in which the output extraction electrode is formed in direct contact with the semiconductor layer in the exposed region of the semiconductor layer, for example, as described above, the semiconductor surface is accidentally exposed by using the uneven surface profile of the main surface of the semiconductor substrate. When the output extraction electrode is formed, not all of the semiconductor exposed region is used as a contact hole with the output extraction electrode, and the position is outside the formation region of the output extraction electrode. In some cases, the exposed semiconductor region may remain. In the fourth configuration, the semiconductor layer exposed region can be passivated by covering the remaining semiconductor layer exposed region that is not used as a contact hole with a transparent auxiliary insulating layer, and the semiconductor layer is contaminated from the semiconductor layer exposed region. It is possible to effectively prevent an undesired leakage current due to adhesion or the like. In addition, since the auxiliary insulating layer is transparent, shadowing loss due to the formation of the auxiliary insulating layer hardly occurs. Such an auxiliary insulating layer can be easily formed if the remaining semiconductor layer exposed region, the insulating film, and the output extraction electrode are covered together, and the manufacturing cost can be reduced.
The fourth configuration of the solar cell according to the present invention can be combined with the first configuration or the second configuration described above. For example, in FIG. 7F, the semiconductor layer exposed region 5 is formed on the top 25 of the convex portion 15, and the output extraction electrode 7 is in direct contact with the semiconductor layer 2 at the semiconductor layer exposed region 5. On the other hand, the fourth configuration can be implemented regardless of the first configuration or the second configuration. In the example shown in FIG. 7G, the convex portion 15 is not formed on the main surface of the substrate 1, and the semiconductor layer exposed portion 35 is formed on the insulating layer 3 by photolithography or the like. In any configuration, the auxiliary insulating layer 10 covers the remaining semiconductor layer exposed region 5 ′, the insulating film 3, and the output extraction electrode 7 together.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, several embodiments according to the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
FIG. 1A is a cross-sectional view schematically showing one embodiment of the solar cell of the present invention. The solar cell 100 includes an impurity diffusion layer 2 (in this embodiment, n-type) on the first main surface side of a silicon single crystal substrate 1 (hereinafter simply referred to as the substrate 1; in this embodiment, p-type). Is formed, forming a pn junction. In the present invention, a layer newly formed near the surface of the semiconductor substrate, such as the diffusion layer 2, is collectively referred to as the semiconductor layer 2. On the surface of the semiconductor layer 2, an insulating film (passivation film) 3, a transparent conductive layer 6, and an output extraction electrode 7 are formed in this order.
Here, an uneven portion is formed on the first main surface of the substrate 1, and the insulating film 3 is formed so as to cover the uneven portion. Then, the semiconductor layer exposed region 5 that is not covered with the insulating film 3 is formed so as to include the top portions 25 of some of the convex portions 15 that form the concave and convex portions. As shown in an enlarged view in FIG. 19A, the tip height position of the top 25 of the convex portion 15 in the semiconductor layer exposed region 5 is the maximum height position of the insulating film 3 on the outer peripheral edge of the semiconductor layer exposed region 5. That is, it is higher than (the maximum height position of the inner peripheral edge 11 of the insulating film 3). The transparent conductive layer 6 is in direct contact with the semiconductor layer 2 at the top 25 of the convex portion 15 in the semiconductor layer exposed region 5, and the output extraction electrode 7 formed thereon is a transparent conductive layer. In other words, the semiconductor layer 2 is indirectly contacted via 6.
The semiconductor layer exposed region 5 is preferably formed so that the total area ratio is 1% or less on the main surface (here, the first main surface) of the substrate 1 on which the semiconductor layer exposed region 5 is formed. The semiconductor layer exposed region 5 functions as a contact hole with the transparent conductive layer 6, and the surface recombination speed becomes very high at this position. Therefore, by reducing the total area ratio to 1% or less, effective surface recombination is achieved. It is possible to reduce the binding speed. Thereby, an open circuit voltage and conversion efficiency can be improved. On the other hand, if the formation area ratio is not secured at least about 0.001%, the resistance increases due to current concentration in the vicinity of the contact, and sufficient conversion efficiency cannot be expected.
Since single crystal silicon which is a constituent material of the substrate 1 has a large refractive index of 6.00 to 3.50 in a wavelength range of 400 to 1100 nm, reflection loss when sunlight enters is a problem. The uneven portion is formed mainly for preventing reflection of the first main surface that serves as a light receiving surface of the solar cell. As shown in FIG. 2A, a large number of pyramidal protrusions 55 whose outer surface is a (111) surface. A random texture structure consisting of Such a texture structure can be formed by anisotropically etching the (100) plane of a silicon single crystal using an etching solution such as an aqueous hydrazine solution or sodium hydroxide. The semiconductor layer exposed region 5 can be formed so as to include the tip of the pyramidal protrusion 55.
In addition, as shown in FIG. 2B, a configuration in which V grooves are arranged at regular intervals (the inner surface of the grooves is, for example, (111) surfaces of silicon single crystals intersecting each other) may be adopted. it can. Such a V-groove can be formed by photolithography, for example, by anisotropic etching using a diluted NaOH aqueous solution. In this form, the triangular roof-shaped rib-like part 56 sandwiched between adjacent V-grooves is a convex part, and its ridge line part is the top. The semiconductor layer exposed region 5 can be formed so as to include only a part of the ridgeline, for example. In this embodiment, by aligning the grooves, the output extraction electrode can be formed in a regular shape, and the series loss can be reduced more effectively. If photolithography is used, as shown in FIG. 2C, a lattice-like rib 57 having a shape in which the rib-like portions 56 of FIG. 2B are crossed in a lattice shape can be obtained. In other words, this is to form a so-called inverted pyramid uneven portion in a form in which pyramidal concave portions are arranged in a lattice pattern. According to this, surface reflection can be more effectively suppressed.
In consideration of the ease of carrying out the step of covering the surface with the etching protective film 4 with a sufficient antireflection effect and exposing only the top, the top from the bottom of the valley of the convex portion 15 to be formed. It is desirable that the maximum height to the portion is 0.1 μm or more and 30 μm or less.
Next, the insulating film 3 can be an oxide type or nitride type. Here, the substrate 1 is a silicon single crystal substrate, and the insulating film 3 is configured as a silicon oxide film or nitride film (which can be formed by, for example, a CVD method) formed by heat treatment in a predetermined atmosphere. . Thereby, the insulating film 3 functions as a passivation film having a low surface recombination speed.
The method of forming the semiconductor layer exposed region 5 on the insulating film 3 is as already described with reference to FIG. For example, a coating material is prepared using a polymer material having sufficient resistance to etching such as hydrofluoric acid, for example, a novolac resin as a resist material. The viscosity of the coating solution can be adjusted using an appropriate solvent. As shown in FIG. 8A, this coating solution is applied by a known coating method such as spin coating or spraying. As a result, the coating liquid accumulates in the concave portion 16 formed between the adjacent convex portions 15 and 15 to form the coating layer 24. Next, when the solvent is evaporated and dried, as shown in FIG. 8B, the coating layer 24 becomes a resist layer 4 ′, and the bottom portion of the recess 16 is partially filled.
Then, as shown in FIGS. 8C and 8D, the resist layer 4 ′ gradually increases in thickness by repeating the formation and drying of the coating layer 24 as described above. Then, when the top 25 of the protrusion 15 is exposed to a necessary and sufficient height, the resist layer 4 ′ is not formed any further, and this is used as a final etching protective film as shown in FIG. 4C. Used as 4. In this state, if the first main surface side of the substrate is immersed in an etching solution containing hydrofluoric acid or the like, and an insulating film (for example, a silicon oxide film) covering the protruding top portion 25 of the convex portion 15 is dissolved and removed. Then, the semiconductor layer exposed region 5 is formed. When the etching is completed, as shown in FIG. 4D, the etching protective film 4 is removed using an organic solvent such as acetone or MEK (methyl ethyl ketone).
The coating liquid used when forming the etching protective film 4 is a liquid whose viscosity is adjusted moderately (for example, 0.04 to 0.1 N · s / m ² ) Must be used. If the viscosity of the coating liquid is excessively large, as shown in FIG. 9A, the liquid remains around the top 25 of the convex portion 15 to be exposed from the liquid surface of the coating layer 24 due to surface tension. After drying, as shown in FIG. 9B, an excessive etching protective film 4a remains on the top 25 of the convex portion 15 and hinders etching. On the other hand, when a coating liquid whose viscosity is adjusted moderately is used, as shown in FIG. 9C, the top 25 of the convex portion 15 can be exposed from the liquid level without excess or deficiency. In this case, even if some etching protective film 4a remains on the top 25 after drying, as shown in FIG. 9D, the residual film becomes thin or porous, or becomes an island shape, and the insulating film It is possible to reliably form a state in which 3 is at least partially exposed. In this case, since the etching solution permeates from the exposed portion, the portion of the insulating film 3 where the etching protection film 4a remains can be removed. Then, by reducing the residual amount of the etching protective film 4a at the peak of the convex portion 15 in this way, as shown in FIG. 7C, the semiconductor layer exposed region 5 corresponds to the film surface position of the etching protective film 4a. The upper surface 11 of the inner peripheral edge of the insulating film 3 that forms the outer peripheral edge of the insulating film 3 can be formed flat. As a result, it is possible to form the semiconductor layer exposed region 5 in which the remaining insulating film 3 is small and variation in the formation area is suppressed to be low.
If the etching protection film 4 can completely cover the periphery of a certain convex portion 15, the base end side outer peripheral surface of the convex portion 15 is covered with the insulating film 3 as illustrated in FIG. 7B or FIG. 7C. The semiconductor layer exposed region 5 can be formed in such a manner that the tip portion of the convex portion 15 is covered and protrudes from the upper edge 11 of the insulating film 3. However, the heights of all the convex portions 15 are not ideally aligned. For example, as shown in FIG. 10A, a convex portion 15 ′ having a height smaller than the convex portions 15 existing around is formed. If so, it may be completely buried in the etching protective film 4. In this case, the insulating film 3 on the top portion 25 of the convex portions 15 ′ is not naturally removed. FIG. 7D also shows an example in which a convex portion 15 ′ from which the insulating film 3 is not removed is formed. These convex portions 15 ′ may be formed to some extent as long as they do not hinder contact with the output extraction electrode 7.
On the other hand, it is ideal that the etching protective film 4 is uniformly filled in all the recesses. However, in the case of adopting a random texture structure, for example, the recesses opened to the outside are shown in FIG. 10B. In addition, there may be a recess 16 'in which the coating liquid is difficult to accumulate. In this case, since the etching protection film 4 is not sufficiently formed in the concave portion 16 ′ and the convex portion 35 adjacent thereto, the convex portion 35 in which the insulating film 3 is entirely removed in the semiconductor layer exposed region 5. May exist.
As shown in FIG. 11A, in order to uniformly form the semiconductor layer exposed region 5 having a small variation in formation area, the height of the film surface of the etching protection film 4 is made substantially constant as shown in FIG. 8D. It is desirable to align.
Next, the transparent conductive layer 6 is made of, for example, tin oxide (SnO ₂ ) Or indium oxide (In ₂ O ₃ ) Or the like. Specifically, a tin oxide film doped with antimony (Sb) (so-called Nesa film) or an indium oxide film doped with tin (Sn) (so-called ITO film) has a high conductivity and can be suitably used in the present invention. . Among these, the nesa film has a high conductivity and contributes particularly to the reduction of the series resistance of the solar cell. On the other hand, the ITO film is slightly inferior in conductivity to the nesa film but is cheaper. In addition to the Nesa film and the ITO film, for example, Cd ₂ SnO ₄ , Zn ₂ SnO ₄ ZnSnO ₃ MgIn ₂ O ₄ CdSb doped with yttrium (Y) ₂ O ₆ Sn doped GaInO ₃ Etc. can be used as the material of the transparent conductive layer 6.
These conductive oxide films can be formed by a vapor deposition method, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD) such as sputtering or vacuum deposition. However, other methods such as a sol-gel method may be used. As shown in FIG. 11B, the transparent conductive layer 6 is formed so as to cover the semiconductor layer exposed region 5 and the insulating film 3 together. As shown in FIG. 7D or FIG. 11C, the transparent conductive layer 6 is formed on the transparent conductive layer 6. An output extraction electrode 7 is formed. In these figures, the output extraction electrodes 7 are all formed in a positional relationship overlapping the semiconductor layer exposed region 5, but since the conductivity of the transparent conductive layer 6 is high, as shown in FIG. The formation position of the extraction electrode 7 may be slightly deviated from the position of the semiconductor layer exposed region 5.
From the viewpoint of reducing the series resistance of the solar cell 100, the transparent conductive layer 6 has an electrical resistivity of 5 × 10. ^-5 ~ 3x10 ^-4 It is desirable to adjust to about Ω · cm. For example, an ITO film produced by sputtering has an electrical resistivity value of, for example, 1 × 10 ^-4 ~ 2.8x10 ^-4 It can be set to Ω · cm. On the other hand, the Nesa film is formed by CVD, for example, 1 × 10. ^-4 A film having a low resistivity of Ω · cm or less can be obtained.
The transparent conductive layer 6 can also function as an antireflection film by adopting a material having a refractive index different from that of the silicon single crystal constituting the substrate 1. When functioning as an antireflection film, the refractive index of the constituent material of the transparent conductive layer 6 is preferably 1.5 to 2.5. For example, in the case of a nesa film, the refractive index is about 2.0, and when the thickness is about 40 to 70 nm, a remarkable antireflection effect can be obtained. An antireflection film may be separately formed together with the transparent conductive layer 6 or instead of the transparent conductive layer 6. For example, MgF on the transparent conductive layer 6 ₂ If a film having a refractive index lower than that of the transparent electrode layer 6 such as a film is formed, the reflectance can be further reduced and the generated current density can be further increased.
The output extraction electrode 7 is obtained by printing and baking a desired electrode pattern on the transparent conductive layer 6 by a known thick film printing method such as screen printing using a paste containing metal powder such as silver powder. Can be formed. Further, the output extraction electrode 7 can be formed at a lower temperature by using a thermosetting paste. As shown in FIG. 17, since the first main surface side of the substrate 1 is a light receiving surface of the solar cell, the output extraction electrode 7 is provided, for example, in order to increase the incident efficiency of light to the pn junction 48. A thick bus bar electrode formed at an appropriate interval for reducing internal resistance and a finger electrode branched from the bus bar electrode into a comb shape at a predetermined interval can be used. However, when the conductivity of the transparent conductive layer 6 is sufficiently high, it is possible to omit the finger electrodes or to widen the formation interval even when they are formed.
When screen printing as described above is used, the formation width of the output extraction electrode 7 (bus bar electrode or finger electrode) is increased to some extent. In this case, as shown in FIG. 1A or 7D, the output extraction electrode 7 is formed so as to straddle the semiconductor layer exposed region 5 and the surrounding insulating layer 3. Since the output extraction electrode 7 formed in such a specific form by screen printing is wide, it is necessary to widen the arrangement interval of a plurality of electrodes to be formed in order to reduce shadowing loss. However, unlike the solar cell manufactured by the conventional fire-through method, the transparent conductive layer 6 is formed in this configuration, so that the resistance loss is small and the conversion efficiency η can be increased.
Returning to FIG. 1A, an uneven portion for preventing back surface reflection is formed on the second main surface of the substrate 1, and an insulating film 3 is formed so as to cover the uneven portion. Further, the semiconductor layer exposed portion 5 is formed at the peak portion of the convex portion 15. However, since the second main surface side does not become a light receiving surface, the entire surface is covered with the output extraction electrode 8. When reducing the thickness of the substrate 1 to reduce the weight of the solar battery cell, as shown in FIG. 1B, in order to prevent recombination / annihilation of minority carriers at the electrode 8 on the second main surface side. A high-concentration diffusion layer 9 having the same conductivity type as that of the substrate 1 and having a higher concentration can be formed on the second main surface side (a so-called BSF (back surface field) layer).
Hereinafter, the operation of the solar cell 100 of FIG. 1 will be described. As shown in FIG. 16, when the solar cell 100 absorbs photons having energy larger than the forbidden band width by light irradiation, electrons and holes are generated as minority carriers by photoexcitation in the p-type region and the n-type region. Each diffuses toward the joint. An internal electric field (so-called “built-in electric field”) is generated at the junction due to the formation of the electric double layer, and electrons and holes diffused as minority carriers are caused by this internal electric field. Electrons are drawn into the n-type region, and holes are drawn into the p-type region and separated into major carriers. As a result, the p-type region and the n-type region are charged positively and negatively, respectively, and an electromotive force ΔE of the solar cell is generated between the electrodes (FIG. 1: 7, 8) provided in each part.
Here, in the case where the substrate surface is passivated with an insulating film, if the contact hole is formed by the fire-through method, the dopant concentration of the emitter layer which is the semiconductor layer 2, here the surface n-type layer, is 3 × 10. ²⁰ cm ^-3 (Sheet resistance conversion: 40Ω / □) Unless set to about the following, the resistance of the electrode contact portion formed by fire-through is a sufficient value, for example, 0.01Ωcm ² It cannot be lowered to the extent. That is, in the fire-through method, the dopant concentration of the semiconductor layer 2 must be increased in order to reduce the contact resistance loss. Further, even if the width of the output extraction electrode 7 formed by screen printing is narrow, it is necessary to ensure 100 μm or more, and in order to make the shadowing loss around 5%, for example, the pitch between the electrodes is 2 to 3 mm. It was necessary to be.
However, according to the configuration of the solar cell 100 in FIG. 1, the semiconductor layer exposed region 5 serving as a contact hole can be easily formed by simple etching without using the fire-through method. Therefore, naturally the dopant concentration of the semiconductor layer 2 is also 3 × 10. ²⁰ cm ^-3 It becomes possible to set a value smaller than (sheet resistance conversion: 40Ω / □). Further, as shown in FIG. 13B, since the transparent conductive layer 6 is used, it is necessary to flow a current in the lateral direction in the semiconductor layer 2 for a longer distance than in the case of FIG. 13A where the transparent electrode layer 6 is not used. Disappear. For example, when a nesa film or an ITO film is used as the transparent conductive layer 6, the sheet resistance can be lowered to about 10 to 25Ω / □ if there is a thickness (40 to 70 nm) used as an antireflection film. As a result, the output extraction electrode 7 provided on the transparent conductive layer 6 has a series resistance that does not increase so much even if it is doubled, for example, compared with the conventional one (2 to 3 mm), so that shadowing loss can be greatly reduced. Can do.
In the above embodiment, the uneven portion is formed by etching, but the uneven portion can also be formed by mechanical processing. For example, the groove shape illustrated in FIG. 2B can be easily formed by cutting. For example, a plurality of rows of grooves are collectively formed by rotating a plurality of rotating blades arranged in the axial direction so as to bite from the surface of the substrate to a predetermined depth while relatively moving the substrate and the rotating blade in the groove forming direction. be able to.
In the present invention, when there is no concern that the series resistance increases so much, as shown in FIGS. 7A to 7C or 5, the transparent conductive layer 6 is omitted and the semiconductor layer exposed region 5 is used for output extraction. The electrode 7 can be in direct contact with the semiconductor layer 2. In this case, as shown in FIG. 7F, the remaining semiconductor layer exposed region 5 ′ where the output extraction electrode 7 is not formed can be covered with the auxiliary insulating layer 10. In the example of this figure, after forming the output extraction electrode 7, the auxiliary insulating layer 10 is formed so as to cover the remaining semiconductor layer exposed region 5 ', the insulating film 3, and the output extraction electrode 7 collectively. Has been. As a material of the auxiliary insulating layer 10, an inorganic insulating film such as silicon nitride or silicon oxide can be employed. In this case, by appropriately adjusting the formation thickness of the auxiliary insulating layer 10, it can function as an antireflection film.
(Experimental example)
Hereinafter, experimental results performed to confirm the effects of the present invention will be described.
(Experimental example 1)
The solar cell shown in FIG. 1A was produced by the process shown in the flowchart of FIG. First, an as-sliced p-type crystalline silicon substrate 1 cut out from a silicon single crystal ingot (resistivity 2 Ω · cm (dopant concentration 7.2 × 10 ¹⁵ cm ^-3 ) Boron doped product) was prepared. The thickness of the substrate 1 is 300 μm. The substrate 1 is chemically etched with a sodium hydroxide aqueous solution (concentration: 40% by mass) to remove a damaged layer due to slicing, and then added with isopropyl alcohol (sodium hydroxide aqueous solution: 3% by mass). The concavo-convex portions having the random texture form shown in FIG. 2A were formed on both main surfaces of the substrate 1 by dipping in the substrate and performing wet etching.
After cleaning the substrate 1 with the unevenness formed, an n-type diffusion layer 2 (phosphorus diffusion layer) having a sheet resistance of 200Ω / □ was formed on the first main surface by thermally diffusing phosphorus. Next, the phosphorus glass produced on the substrate surface was removed by etching, and then oxidation was performed to form a silicon dioxide film having a thickness of about 5 nm as an insulating film 3 on both main surfaces. Then, an etching protective film 4 mainly composed of a novolac resin is formed so that some of the top portions 25 of the convex portions 15 are projected as shown in FIG. Formed. Subsequently, it was immersed in an aqueous hydrofluoric acid solution having a concentration of 10% by mass, and only the insulating film 3 at the top 25 was etched to form the exposed portion 5 of the semiconductor layer. Next, the substrate was immersed in acetone to dissolve and remove the etching protective film 4.
Next, a tin dioxide film doped with antimony as the transparent conductive layer 6 was deposited on the first main surface of the substrate 1 by atmospheric pressure CVD. The thickness of the transparent conductive layer 6 was set to 60 nm because it also serves as an antireflection film. Next, the pattern of the output extraction electrode 7 having the form shown in FIG. 17 is formed on the surface of the first main surface of the substrate 1 by a screen printing method using silver paste, and the aluminum paste is applied to the entire surface of the second main surface. The pattern of the electrode 8 for output extraction was each formed. Thereafter, hydrogen annealing was performed at a temperature of 400 ° C. to complete the solar cell 100 (Example product 1).
It should be noted that a high-concentration p-type diffusion layer 9 (BSF layer) is formed on the back surface as shown in FIG. 1B using the same process as described above except that phosphorus is simultaneously diffused on the front surface and boron is simultaneously diffused on the back surface. A sample of the solar cell 101 provided with a) was also produced (Example product 2). On the other hand, the solar cell produced using the same board | substrate 1 as the above using the conventional fire through technique was also produced (comparative example goods). In addition, the transparent electrode 6 is not formed in the comparative example product. Each solar cell was subjected to a performance evaluation test as follows. That is, a solar cell unit having a light receiving area of 10 cm square is assembled into a solar simulator (light intensity: 1 kW / m ² , Spectrum: AM1.5 global), and current-voltage characteristics at a temperature of 25 ° C. were measured. The result is shown in FIG. Table 1 shows the characteristics of these solar cells. Further, FIG. 15 shows the internal quantum efficiency of these solar cells.

In Example Product 1 and Example Product 2, the sheet resistance of the emitter layer which is the semiconductor surface layer portion 2 could be set to 200Ω / □. On the other hand, in the comparative example product using the fire-through method, the sheet resistance was 40 to 50Ω / □. As shown in Table 1, it can be seen that the fill factor is not decreased in the example product 1 and the example product 2 as compared with the comparative product. This is considered to be because in Example Product 1 and Example Product 2, the sheet resistance of the transparent conductive layer was low, and the increase in contact resistance was suppressed.
Moreover, when compared with the comparative product, the open circuit voltage is significantly improved in the practical product 1 and the practical product 2. This is considered to be a result of the fact that the dopant concentration in the emitter layer was reduced, the surface recombination rate was reduced, and the area of the contact hole based on the semiconductor layer exposed region 5 could be limited. The substrate 1 used in Example Product 1 and Example Product 2 has a total area ratio of about 1% on the first main surface of the semiconductor layer exposed region 5 based on surface observation by a scanning electron microscope (SEM). It was confirmed that
When compared with the comparative example product, the short-circuit current also increases in the example product 1 and the example product 2. This is thought to be due to a reduction in shadowing loss and an increase in short wavelength sensitivity. In the comparative product, the current flows laterally in the emitter layer, but in this embodiment, it flows in the transparent conductive layer 6 instead. The sheet resistance of the transparent conductive layer 6 is about 10 Ω / □, and comparable resistance loss can be achieved even if the electrode pitch is doubled, for example, compared to the comparative product. Therefore, the shadowing loss can be halved, which is considered to have greatly contributed to the increase in the short-circuit current. Further, as shown in FIG. 15, it is understood that the short wavelength sensitivity of the example product 1 and the example product 2 is also increased. As described above, this is because the dopant concentration in the emitter layer is lowered and the surface recombination rate is reduced.
In Example Product 1 and Example Product 2, conversion efficiency of about 20% could be obtained by increasing the open circuit voltage, the short circuit current, and the fill factor. Particularly, in Example Product 2 in which the BSF layer was introduced on the back side, a solar cell having a conversion efficiency exceeding 20% was obtained.
In the solar cell in this example, the electrodes are formed on the entire back surface, but the transparent conductive film and the comb-like electrode are formed on the back surface as well as the surface so that light can enter from the back surface. I do not care. Moreover, although the 200-ohm / square n-type diffused layer was formed, if it can be made a value higher than 100 ohm / square, a short wavelength sensitivity will increase and a solar cell characteristic will improve. Further, in this embodiment, an oxide film (silicon dioxide film) is used as an insulating film in this embodiment, but a silicon nitride film may be used. In addition, although the thermal diffusion method is used for forming the diffusion layer, any means such as an ion implantation method or a spin-on method can be used as long as the structure of the present invention can be formed.
(Experimental example 2)
The solar cell 103 having the structure shown in FIG. 5 was produced as follows. First, a p-type single crystal silicon substrate 1 (250 μm thick, gallium-doped product having a resistivity of 0.5 Ω · cm) prepared by the CZ method was prepared, and after etching the damaged layer in the same manner as in Experimental Example 1, A random textured surface was formed. After texture formation, P ₂ O ₅ A coating agent containing was applied, thermal diffusion was performed at 850 ° C., and an n-type diffusion layer 2 having a sheet resistance of about 100Ω / □ was formed on the surface.
Thereafter, pyrogenic oxidation was performed at 800 ° C., and the semiconductor layer exposed region 5 was formed by the same method as in Experimental Example 1. Thereafter, output extraction electrodes 7 and 8 similar to those in Experimental Example 1 were formed on the first and second main surfaces, respectively. Subsequently, a silicon nitride film was formed by plasma CVD as the auxiliary insulating film 10 also serving as an antireflection film, and the solar cell 103 was completed (Example product 3). At this time, the substrate temperature was set to 400 ° C., and after the film deposition, the same hydrogen annealing treatment as in Experimental Example 1 was performed. With respect to Example Product 3, a performance evaluation test was conducted in the same manner as in Experimental Example 1. The results are shown in Table 2.

According to this, it can be seen that in the example product 3, the short-circuit current is reduced as compared with the above-described example products 1 and 2, while the open circuit voltage is increased. The reason why the short-circuit current is reduced is considered to be because the electrode width and the electrode pitch are not different from those of the conventional system. That is, the shadowing area is increased as compared with the example products 1 and 2 shown in Table 1. On the other hand, the reason why the open circuit voltage increased is thought to be that the substrate resistivity was lowered from 2.0 Ω · cm to 0.5 Ω · cm. Generally, when the substrate resistivity is lowered, the reverse saturation current density is decreased and the open circuit voltage is increased. However, when the resistivity is about 2.0 Ω · cm in the p-type substrate, it is necessary to consider the problem of light degradation. Photodegradation is a phenomenon in which when a solar cell is irradiated with strong light, the lifetime of the solar cell substrate is reduced and sufficient conversion efficiency cannot be obtained.
In order to investigate the presence or absence of this photodegradation, a solar cell produced using the gallium-doped CZ silicon single crystal substrate and a normal boron-doped CZ silicon single crystal substrate (resistivity 0.5 Ω · cm) were used. The solar cell produced by the same method was continuously irradiated with simulated sunlight under the solar simulator at 25 ° C., and the light irradiation time dependency of the current-voltage characteristics was examined. As a result, when the solar cell produced from the boron-doped substrate was irradiated for 10 hours under simulated sunlight, the conversion efficiency was reduced by about 10%. On the other hand, solar cells using a gallium-doped substrate showed some change in conversion efficiency, but no change in characteristics corresponding to deterioration was observed. Thus, by using the gallium doped substrate, the problem of photodegradation could be avoided, and the open circuit voltage and the conversion efficiency could be improved. In this embodiment, a gallium-doped p-type substrate by the CZ method is used, but the photodegradation problem can be avoided even with an MCZ substrate or FZ substrate having an interstitial oxygen concentration of several ppm or less. Further, even if an n-type substrate is used and a p-type emitter layer is formed using boron or the like, the light deterioration problem can be avoided.
(Experimental example 3)
The solar cell 104 shown in FIG. 6 was manufactured as follows (in FIG. 6, only the portion in the vicinity of the surface is shown without drawing the uneven portion and the antireflection film in order to avoid complication). First, a p-type single crystal silicon substrate 1 (a boron-doped product having a thickness of 250 μm and a resistivity of 2 Ω · cm) prepared by the CZ method is prepared, and using a dicer, a rib shape having a triangular cross section on the first main surface The convex portions 45, 45 were formed at intervals of 2 mm (the region between the convex portions 45, 45 can be regarded as a concave portion). At this time, the height from the first main surface of the substrate 1 to the top of each convex portion 45, 45 was set to about 30 μm.
Next, after chemically etching the damaged layer, a random texture structure having a height of about 5 μm was formed as an uneven portion on both main surfaces. Thereafter, thermal diffusion is performed in the same manner as in Experimental Example 2 to form an n-type diffusion layer 2 having a sheet resistance of about 100Ω / □ on the surface, and subsequently, thermal oxidation is performed to form an oxide film as the insulating film 3. did. Then, an etching protective film is formed on the second main surface side by the same method as in Experiment Example 1, while a hydrofluoric acid resistant printing resist made of a rubber-based resin is formed on the first main surface as an etching protective film. The film was applied by screen printing so as to have a thickness of 20 μm. By doing so, the top portions 25 of the convex portions 45, 45 formed first by the dicer protrude periodically from the surface of the printing resist in the ridge line direction.
After drying the resist, the substrate 1 was immersed in a 10% by mass hydrofluoric acid aqueous solution, and the semiconductor layer exposed portion 5 was formed on the top portions 25 of the convex portions 45 and 45. Next, the resist is washed away using a solvent, and then the pattern of the output extraction electrode 7 shown in FIG. 6 is used on the first main surface using silver paste, and the aluminum paste is used on the second main surface by screen printing. The pattern of the output extraction electrode 8 was formed on the entire surface. At this time, the output lead-out electrode 7 on the first main surface side needs to be aligned so as to be printed so as to overlap the semiconductor layer exposed portion 5 on the top of the convex portions 45, 45, Since the width of the electrode 7 is about 10 times the width of the exposed portion 5 of the semiconductor layer, the alignment can be performed relatively roughly. Subsequently, TiO as an antireflection film ₂ A film (not shown) was formed to a thickness of 60 nm by atmospheric pressure CVD to complete the solar cell 104 (Example product 4).
When the performance evaluation of Example Product 4 was performed in the same manner as in Experimental Example 1, the open circuit voltage was 0.667 V and the short-circuit current density was 36.9 mA / cm. ² A fill factor of 0.770 and a conversion efficiency of 19.0% were obtained, and the characteristics were improved as compared with the conventional screen printing / fire-through method.
[Brief description of the drawings]
FIG. 1A is a schematic diagram showing a cross-sectional structure of a first example of a solar cell according to the present invention.
FIG. 1B is a schematic diagram showing a cross-sectional structure of a second example of the solar cell according to the present invention.
FIG. 2A is a perspective view showing a first example of the shape of a concavo-convex portion formed on a semiconductor substrate.
FIG. 2B is a perspective view showing a second example.
FIG. 2C is a perspective view showing a third example.
FIG. 3 is a flowchart showing a manufacturing process of the solar cell in the experimental example.
FIG. 4A is a process explanatory view showing a method for forming a semiconductor layer exposed region in the present invention.
FIG. 4B is a process explanatory diagram following FIG. 4A.
FIG. 4C is a process explanatory diagram following FIG. 4B.
FIG. 4D is a process explanatory diagram following FIG. 4C.
FIG. 5 is a schematic diagram showing a cross-sectional structure of the solar cell used in Experimental Example 2.
FIG. 6 is an enlarged perspective view showing a main part of the solar cell used in Experimental Example 3.
FIG. 7A is a schematic diagram showing a first example of a cross-sectional structure of a main part of the solar cell of the present invention.
FIG. 7B is a schematic diagram showing a second example.
FIG. 7C is a schematic diagram showing a third example.
FIG. 7D is a schematic diagram showing a fourth example.
FIG. 7E is a schematic diagram showing a fifth example.
FIG. 7F is a schematic diagram showing a sixth example.
FIG. 7G is a schematic diagram showing a seventh example.
FIG. 8A is a process explanatory view showing an example in which an etching protective film is formed thicker in steps using a coating solution.
FIG. 8B is a process explanatory diagram following FIG. 8A.
FIG. 8C is a process explanatory diagram following FIG. 8B.
FIG. 8D is a process explanatory diagram following FIG. 8C.
FIG. 9A is a diagram for explaining the relationship between the viscosity of the coating liquid and the formation state of the etching protective film.
FIG. 9B is an explanatory diagram following FIG. 9A.
FIG. 9C is an explanatory diagram following FIG. 9B.
FIG. 9D is an explanatory diagram following FIG. 9C.
FIG. 10A is a schematic cross-sectional view illustrating the relationship between the formation form of the etching protective film and the formation form of the exposed portion of the semiconductor layer.
FIG. 10B is a schematic cross-sectional view showing another example.
FIG. 11A is a schematic cross-sectional view showing a first example of the manufacturing process of the solar cell of the present invention incorporating a transparent conductive layer.
FIG. 11B is a schematic cross-sectional view showing a second example.
FIG. 11C is a schematic cross-sectional view showing a third example.
FIG. 12 is a schematic cross-sectional view showing a modification of the mode of forming the output extraction electrode in the solar cell of the present invention incorporating the transparent conductive layer.
FIG. 13A is a diagram for explaining a difference in a current path flowing through a surface layer portion depending on the presence or absence of a transparent conductive layer.
FIG. 13B is an explanatory diagram following FIG. 13A.
FIG. 14 is a graph showing current-voltage characteristics of each solar cell in Experimental Example 1.
FIG. 15 is a graph showing the relationship between internal quantum efficiency and wavelength.
FIG. 16 is a diagram illustrating the principle of a solar cell using a pn junction.
FIG. 17 is a perspective view schematically showing an example of a form of forming an output extraction electrode on the light receiving surface side.
FIG. 18 is an explanatory diagram of a current-voltage curve of a solar cell.
FIG. 19A is a schematic diagram illustrating the difference in the formation form of the exposed portion of the semiconductor layer between the present invention and the conventional method.
FIG. 19B is an explanatory diagram following FIG. 19A.

Claims (6)

A solar cell in which a concavo-convex portion is formed on a main surface of a semiconductor substrate, and the main surface is covered with an insulating film, and includes a top portion of at least a part of the convex portion forming the concavo-convex portion A semiconductor layer exposed region that is not covered with the insulating film is formed on the main surface, and the tip height position of the top of the convex portion in the semiconductor layer exposed region is the height of the semiconductor layer exposed region. It is higher than the maximum height position of the insulating film at the outer peripheral edge, and so as to contact the top of the convex portion in the semiconductor layer exposed region directly or indirectly through another conductive layer, In the method of manufacturing a solar cell in which an output extraction electrode is formed,
  Forming a concavo-convex portion on the main surface of the semiconductor substrate;
  Covering the main surface of the semiconductor substrate with the insulating film in a form including the uneven portion;
  A step of covering the insulating film with an etching protective film in a region other than the top of the convex part forming the concavo-convex part so that the top protrudes from the etching protective film;
  Thereafter, the insulating film on the top of the convex portion is removed by etching, thereby exposing an exposed region of the semiconductor layer not covered with the insulating film so as to include the top of at least a part of the convex portion. Forming, and
  Forming an output extraction electrode so as to contact the top of the convex portion in the semiconductor layer exposed region directly or indirectly through another conductive layer;
including,
  A method for manufacturing a solar cell. An uneven portion is formed on the main surface of the semiconductor substrate, the main surface is covered with an insulating film, and the insulating film covers the top of at least a part of the protruding portion forming the uneven portion. An output is formed such that an unexposed semiconductor layer exposed region is formed on the main surface and is in direct contact with the top of the convex portion in the semiconductor layer exposed region directly or through another conductive layer. In the solar cell in which an extraction electrode is formed, the semiconductor layer exposed region covers the main surface of the semiconductor substrate with the insulating film in a form including the concave and convex portions, and further the top of the convex portion The insulating film is formed with an etching protective film in a region other than the portion so that the top portion protrudes from the etching protective film, and then the insulating film on the top portion of the convex portion is removed by etching. For solar cell manufacturing methods Te,
  Forming a concavo-convex portion on the main surface of the semiconductor substrate;
  Covering the main surface of the semiconductor substrate with the insulating film in a form including the uneven portion;
  A step of covering the insulating film with an etching protective film in a region other than the top of the convex part forming the concavo-convex part so that the top protrudes from the etching protective film;
  Thereafter, the insulating film on the top of the convex portion is removed by etching, thereby exposing an exposed region of the semiconductor layer not covered with the insulating film so as to include the top of at least a part of the convex portion. Forming, and
  Forming an output extraction electrode so as to contact the top of the convex portion in the semiconductor layer exposed region directly or indirectly through another conductive layer;
including,
  A method for manufacturing a solar cell. The manufacturing method of the solar cell of Claim 1 or Claim 2 including the process of forming the said uneven | corrugated | grooved part by an etching. The manufacturing method of the solar cell of any one of Claim 1 thru | or 3 including the process of forming the said uneven | corrugated | grooved part by mechanical processing. A step of forming a plurality of the semiconductor layer exposed regions on the main surface, a step of forming the output extraction electrode in direct contact with the semiconductor layer in a part of the semiconductor layer exposed region, and the output extraction The method for manufacturing a solar cell according to any one of claims 1 to 4, further comprising a step of covering a remaining exposed region of the semiconductor layer where an electrode is not formed with an auxiliary insulating layer. 6. The method for manufacturing a solar cell according to claim 5, wherein the auxiliary insulating layer is formed so as to cover the remaining semiconductor layer exposed region, the insulating film, and the output extraction electrode in a lump. .

Images