WO2002031892A1

WO2002031892A1 - Solar cell and method of manufacture thereof

Info

Publication number: WO2002031892A1
Application number: PCT/JP2000/008486
Authority: WO
Inventors: Hiroyuki Ohtsuka
Original assignee: Shin-Etsu Handotai Co., Ltd.; Shin-Etsu Chemical Co., Ltd.
Priority date: 2000-10-06
Filing date: 2000-11-30
Publication date: 2002-04-18
Also published as: TW480737B; KR100790956B1; JP3872428B2; KR20030036893A; CN1284248C; CN1454395A; JPWO2002031892A1

Abstract

A solar cell includes a semiconductor substrate (1) with irregularities on its principal surface covered with an insulating layer (3) such that it covers some of the projections of the irregularities, that is, uncovered areas (5) are formed on the principal surface. An output electrode (7) is connected directly, or through a conducting layer, with tops (25) of projections (15) in the exposed semiconductor areas (5). The exposed semiconductor areas (5) is formed by applying insulating film (3) to cover projections (15) on the principal surface of the semiconductor substrate (1), applying etch resist (4) to cover the insulating film (3) in the areas except the peaks (25) of the projections (15), and etching the insulating film (3) to expose the peaks (25) of the projections (15).

Description

Solar cell and method for manufacturing the same

The present invention relates to a solar cell which has relatively high photoelectric conversion efficiency and can be manufactured at low cost, and a method for manufacturing the same. Light

Rice field

Background art

A solar cell is a semiconductor element that converts light energy into electric power, and includes a pn junction type, a pin type, and a Schottky type. The pn junction type is most widely used. When solar cells are classified based on their substrate materials, they can be broadly classified into three types: silicon crystalline solar cells, amorphous silicon solar cells, and compound semiconductor solar cells. Silicon crystalline solar cells are further classified into single crystalline solar cells and polycrystalline solar cells. Of these, the compound with the highest energy conversion efficiency is a compound semiconductor solar cell, but it is extremely difficult to make a compound semiconductor as a material for the compound semiconductor solar cell, and the cost of manufacturing solar cell substrates is low. There are problems with its widespread use, and its use is limited. On the other hand, as a solar cell with the highest conversion efficiency next to a compound semiconductor solar cell, a silicon single crystal solar cell follows, and a silicon single crystal substrate for solar cells can be manufactured relatively easily. It is the mainstay of solar cells.

The output characteristics of a solar cell are generally evaluated by measuring an output current-voltage curve as shown in Fig. 18 using a solar simulator. On this curve, the point Pm at which the product Ip · Vp of the output current I and the output voltage Vp is maximum is called the maximum output Pm, and the total light energy incident on the solar cell (Pm) SXI: S is the element area, I is the irradiation light Intensity) divided by:

η≡ {Pm / (S X I)} X 100 (%)

Is defined as the conversion efficiency of the solar cell. As is clear from Fig. 18, in order to increase the conversion efficiency 77, the short-circuit current Isc (the output current value when V = 0 on the current-voltage curve) or the open-circuit voltage Voc (I = 0 It is important to increase the output voltage value at the time of (1) and to make the output current-voltage curve a shape close to a square shape. Note that the squareness of the output current-voltage curve is generally

F F≡ I pmXVp m / (IscXVoc) (2)

It can be evaluated by the fill factor (fill factor) defined by. The closer the value of F F is to 1, the closer the output current-voltage curve becomes to an ideal square shape, and the higher the conversion efficiency η is.

For example, in a silicon crystal-based solar cell, the surface of the silicon layer must be covered with S to prevent the recombination of electrons and holes at the direct contact between the metal electrode for output extraction and the silicon layer and to increase the open-circuit voltage V oc. i 0 structure forming an insulating film such as ₂ is employed (-called MIS contact or contact passivating Chillon). However, if the entire surface of the silicon layer is covered with the insulating film as described above, the generated photocurrent must pass through the insulating film by a tunnel effect, and the photocurrent collection rate is reduced. As a result, the conversion efficiency cannot be sufficiently improved.

To prevent this, a small contact hole is provided in a part of the insulating film, and a metal electrode is formed here, so that the direct contact between the metal electrode acting as a recombination site and the silicon layer is reduced to a small area. Limitations have been made to improve the photocurrent collection rate. In this case, how to form a contact hole in the insulating film becomes a problem. For example, in a laboratory, a method of forming a contact hole by etching a dielectric film using a photoresist or the like can be considered. However, this method requires too much man-hour and cost to use one photolithography technology, and from the viewpoint of mass production of solar cells. Is not realistic.

In view of this, Japanese Patent Application Laid-Open No. Hei 8-333571 proposes a method for forming a contact hole without using photolithography technology. Specifically, a pattern of a metal electrode for taking out output is formed on the insulating film by screen printing of a conductive paste, and then baked. As a result, the metal and the glass frit contained in the paste are melted by heat, break through the insulating film and reach the emitter layer, thereby forming a contact hole. This method is generally referred to as fire-through, and is widely used when fabricating single-crystal or polycrystalline solar cells because of its ability to form a contact horn easily.

By the way, in the solar cell manufacturing method using the fire-through method, it is necessary to set the dopant concentration of the emitter layer, which is the surface n-type layer, to be high. This is because when the dopant concentration of the emitter layer is low, the contact resistance at the direct contact between the metal and silicon formed by the fire-through does not drop sufficiently, and the power that can be extracted is reduced due to the large contact resistance loss Because it leads to things. However, if the dopant concentration in the emitter layer is increased by diffusion, a compound of the semiconductor silicon and the dopant precipitates, and many defect levels are formed on the surface, thereby increasing the surface recombination rate. In such a state, the short-wavelength sensitivity of the solar cell is reduced, and a drawback occurs in that the current that can be extracted is reduced.

On the other hand, in order to increase the conversion efficiency 77 of the solar cell, it is also important to reduce the formation width of the metal electrode for taking out the output as much as possible to reduce the shadow loss. However, in the fire-through method, since electrodes are formed by screen printing, it is theoretically difficult to make the electrode width extremely small.As a result, in order to reduce shadowing loss, an array of a plurality of electrodes is formed. The interval has to be widened. When the electrode arrangement interval is widened in this way, the current conduction becomes longer in the thin emitter layer in the horizontal direction during current extraction, so that the emitter loss is increased and the conversion efficiency 77 must be reduced. Absent. For these reasons, it is considered difficult to produce a solar cell having a good conversion efficiency of 77, for example, a solar cell with a conversion factor of more than 20% by employing the fire-through method.

An object of the present invention is to provide a solar cell which can be manufactured with high conversion efficiency and low power at low cost, and a method for manufacturing the same. DISCLOSURE OF THE INVENTION ''

In order to solve the above-mentioned problems, a first configuration of a solar cell according to the present invention is a solar cell in which an uneven portion is formed on a main surface of a semiconductor substrate and the main surface is covered with an insulating film. A semiconductor layer exposed region not covered with an insulating film is formed on the main surface so as to cover at least a top of at least a part of the convex portion forming the portion, and the convex portion is formed in the semiconductor layer exposed region. The height of the tip at the top of the semiconductor layer is higher than the maximum height of the insulating film at the outer peripheral edge of the semiconductor layer exposed region, and is directly or at another position on the top of the の portion in the semiconductor layer exposed region. It is characterized in that an output extraction electrode is formed so as to be indirectly contacted via a conductive layer.

In this specification, the main surface of the semiconductor substrate means at least one of both surfaces (front surface, back surface) in the thickness direction of the semiconductor substrate. Therefore, the uneven portions may be formed only on one main surface of the substrate, or may be formed on both surfaces. In addition, in this specification, the semiconductor layer exposed region is conceptually defined not only when the insulating film is completely removed but also when the insulating film is thick enough to allow a tunnel current to flow (about 3 nm or less). Including.

In the solar cell of the first configuration, the unevenness is formed on the main surface of the semiconductor substrate. The formation of such uneven portions has been employed in conventional silicon single crystal solar cells mainly for the purpose of preventing reflection loss. However, in the present invention, not only the above-mentioned uneven portions are prevented from preventing the reflection loss, but also the specific form thereof is used as an output extraction electrode and a semiconductor. It is characterized in that it is used to form an exposed region of a semiconductor layer which is to function as a contact hole with a body layer. Specifically, as illustrated in FIG. 19A, the semiconductor layer exposed region 5 is formed so as to include the top 25 of the convex portion 15 and the height of the tip of the convex portion 15 is increased. The height position is higher than the maximum height position of the insulating film 3 at the outer peripheral edge of the semiconductor layer exposed region 5. Then, the output extraction electrode 7 is formed so as to directly contact (or indirectly via the other conductive layer) the top portion 25 of the convex portion 15 in the semiconductor layer exposed region 5.

For example, in a contact hole formed by photolithography through through in a conventional solar cell, as shown in FIG. 19B, the semiconductor layer exposed region 5 forms a so-called bottom surface of the contact hole. The semiconductor layer 2 in the exposed region 5 can never project beyond the upper edge of the surrounding insulating film 3. In this regard, the structure of the solar cell according to the first aspect of the present invention is crucially different from those of conventional solar cells. By adopting such a structure, there is an advantage that the semiconductor layer exposed region 5 can be formed extremely simply by the method for manufacturing a solar cell of the present invention described below. That is, the method includes the steps of forming an uneven portion on a main surface of a semiconductor substrate;

A step of covering the main surface of the semiconductor substrate with an insulating film including irregularities;

A step of covering the insulating film with an etching protection film in a region other than the top of the convex portion forming the concave / convex portion;

Thereafter, the insulating film on the top of the protrusion is removed by etching to form a semiconductor layer exposed region not covered with the insulating film so as to cover the top of at least a part of the protrusion. Process and

Forming an output extraction electrode so as to directly or indirectly contact the top of the protrusion in the semiconductor layer exposed region via another conductive layer;

It is characterized by including.

Further, the second configuration of the solar cell according to the present invention captures the features of the solar cell of the present invention from the viewpoint of the above-mentioned manufacturing method. Insulation A semiconductor layer exposed region not covered with the insulating film is formed on the main surface so as to cover at least a part of the projections forming the concave and convex portions, the semiconductor layer being covered by the film; In a solar cell in which an output extraction electrode is formed so as to directly or indirectly contact the top of the projection in the exposed area through another conductive layer,

The semiconductor layer exposed region covers the main surface of the semiconductor substrate with an insulating film including irregularities, and further covers the insulating film with an etching protective film in a region other than the top of the convex portion, and then forms a convex portion by etching. It is characterized by being formed by removing the insulating film at the top of the part.

According to the above method, as shown in FIG. 4B, the area other than the tops 25 of the projections 15 formed on the main surface is covered with the main surface of the semiconductor substrate 1 shown in FIG. 4A. In other words, in other words, the etching protection film 4 is formed so that the projection 15 is buried halfway in the height direction and only the top is protruded. Then, as shown in FIG. 4C, by performing etching thereafter, only the insulating film 3 on the top 25 of the convex portion 15 protruding from the etching protective film 4 is selectively removed. As a result, the semiconductor layer exposed region 5 described above is formed so as to include the top portion 25 of the convex portion 15. As shown in FIG. 4D, the height position of the tip of the convex portion 15 is higher than the maximum height position 11 of the insulating film 3 at the outer peripheral edge of the semiconductor layer exposed region 5. As the etching protective film 4, a general-purpose polymer resist having no photosensitivity can be used, and in order to form the above-described coating state, it is only necessary to appropriately set the thickness of the etching protective film 4 to be formed. Once such a covering state is formed, the semiconductor layer exposed region 5 can be easily formed only by immersing the substrate in an appropriate etching solution. Therefore, no cumbersome and labor-intensive photolithography technology is required at all, and, of course, no fire-through is required, so that good ohmic contact can be obtained without increasing the dopant concentration on the substrate surface. . Thereby, the fill factor of the solar cell can be increased. Further, since the dopant concentration on the surface can be reduced, the short-wavelength sensitivity of the solar cell increases, and the short-circuit current can be improved. Thus, high conversion efficiency High-performance solar cells can be realized.

Next, in a third configuration of the solar cell according to the present invention, in a solar cell in which a main surface of a semiconductor substrate is covered with an insulating film, a semiconductor layer exposed region not covered with the insulating film is formed on the main surface. The transparent conductive layer is formed so as to cover the semiconductor layer exposed region and the insulating film in a lump, and an output extraction electrode is formed on the transparent conductive layer.

In this configuration, a semiconductor layer exposed region functioning as a contact hole is formed in an insulating film, and a transparent conductive layer covering the semiconductor layer exposed region and the insulating film is formed. Then, an output extraction electrode is formed on the transparent conductive layer. When such a transparent conductive layer is not provided, as shown in FIG. 13A, the current generated on the side of the semiconductor substrate 1 crosses the substrate surface portion (for example, an emitter layer) 2 having a relatively high resistivity. After flowing in the direction, the electrode is taken out from the output extraction electrode 7, so the series resistance increases and losses easily occur. However, according to the solar cell according to the third configuration of the present invention, as illustrated in FIG. 13B, the current from the semiconductor layer exposed region 5 has a relatively high conductivity (that is, the resistivity). After flowing in the transparent conductive layer 6 in the lateral direction, it can be extracted from the output extraction electrode 7. Therefore, the resistance loss when current flows in the lateral direction can be greatly reduced. For example, in FIG. 13A, the distance LP1 to the output extraction electrode 7 must be all lateral conduction paths in the substrate surface layer 2, but in FIG. Regardless of the presence or absence of the electrode 7, the current only needs to flow from the nearest semiconductor layer exposed region 5 to the transparent conductive layer 6, and the lateral conduction length LP 2 is the lateral conduction length of FIG. 13A. It is clear that the length is much shorter than LP 1. As another effect, since the transparent conductive layer is formed, shadowing loss due to the transparent conductive layer itself hardly occurs. Thus, the short-circuit current and the conversion efficiency of the solar cell can be improved.

In particular, when the output extraction electrode is formed by general-purpose screen printing, the width of the output extraction electrode 7 becomes large. Therefore, it is necessary to widen the formation interval to reduce shadowing loss. As shown in Fig. 13A, when the transparent conductive layer is not provided, Although the increase in series resistance is a problem, in the third configuration of the solar cell according to the present invention, as shown in FIG. 13B, since the transparent conductive layer 6 functions as a lateral conduction path, Can be dramatically reduced. Further, when the series resistance increases, there is a certain limit in increasing the formation interval of the output extraction electrode. On the other hand, according to the solar cell according to the third configuration of the present invention, on the transparent conductive layer 6, Even if the formation intervals of the provided output extraction electrodes 7, 7 are made considerably large, the series resistance does not increase so much, and as a result, the shadowing loss can be further reduced.

Further, in the present invention, since it is not necessary to supply a current in the lateral direction in the surface layer portion of the substrate (for example, the emitter layer), even if the sheet resistance is increased, for example, when the n-type emitter layer is formed, the sheet resistance is reduced to 1 0 0 Ω しても There is no problem even if it is much higher than the mouth. That is, the dopant concentration in the surface layer portion of the substrate can be further reduced. This makes it possible to further reduce the surface recombination rate and increase the conversion efficiency.

The third configuration of the solar cell according to the present invention can be combined with the first configuration or the second configuration described above. In this case, the output extraction electrodes 7, 7 can be formed at positions corresponding to the projections 15 scattered at various points on the main surface of the substrate as shown in FIG. 13B. On the other hand, the third configuration can be implemented independently of the first or second configuration. In FIG. 7E, the convex portion 15 is not formed on the main surface of the substrate 1, and the semiconductor layer exposed portion 35 is formed on the insulating layer 3 by photolithography or the like. Next, in a fourth configuration of the solar cell according to the present invention, in the solar cell in which the main surface of the semiconductor substrate is covered with the insulating film, the semiconductor layer exposed region not covered with the insulating film is formed on the main surface. In a part of the semiconductor layer exposed region, the output extraction electrode is formed directly in contact with the semiconductor layer, while the remaining semiconductor layer exposed region where the output extraction electrode is not formed is transparent. It is characterized by being covered with an auxiliary insulating layer.

In the configuration of the solar cell in which the output extraction electrode is formed in direct contact with the semiconductor layer in the semiconductor layer exposed region, for example, as described above, the protrusion of the main surface of the semiconductor substrate: If a semiconductor exposed area is formed accidentally by using a tool, if the output extraction electrode is formed, not all of the semiconductor exposed area is necessarily used as a contact hole with the output extraction electrode. In some cases, the exposed semiconductor region may be left outside the region where the output electrode is formed. In the fourth configuration, by covering such a remaining semiconductor layer exposed region not used as a contact hole with a transparent auxiliary insulating layer, the semiconductor layer exposed region can be passivated, and the semiconductor layer is contaminated from the semiconductor layer exposed region. It is possible to effectively prevent occurrence of an undesired leak current or the like due to adhesion or the like. Further, the auxiliary insulating layer is made of a transparent material, and the formation of the auxiliary insulating layer hardly causes shadowing loss. It should be noted that such an auxiliary insulating layer can be easily formed if the remaining semiconductor layer exposed area, the insulating film, and the output extraction electrode are collectively covered, and the manufacturing cost can be reduced. .

The fourth configuration of the solar cell according to the present invention can be combined with the first configuration or the second configuration described above. For example, in FIG. 7F, the semiconductor layer exposed region 5 is formed on the top 25 of the convex portion 15, and the output extraction electrode 7 is in direct contact with the semiconductor layer 2 in the semiconductor layer exposed region 5. . On the other hand, the fourth configuration can be implemented independently of the first configuration or the second configuration. In the example shown in FIG. 7G, the convex portion 15 is not formed on the main surface of the substrate 1, and the semiconductor layer exposed portion 35 is formed on the insulating layer 3 by photolithography or the like. In any of the configurations, the auxiliary insulating layer 10 collectively covers the remaining semiconductor layer exposed region 5 ', the insulating film 3, and the output extraction electrode 7. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1A is a schematic diagram showing a cross-sectional structure of a first example of a solar cell according to the present invention.

FIG. 1B is a schematic view showing a cross-sectional structure of a second example of the solar cell according to the present invention.

FIG. 2A is a perspective view showing a first example of a form of an uneven portion formed on a semiconductor substrate.

FIG. 2B is a perspective view showing the same second example. FIG. 2C is a perspective view showing a third example.

FIG. 3 is a flowchart showing a manufacturing process of the solar cell in the experimental example.

FIG. 4A is a process explanatory view showing a method for forming a semiconductor layer exposed region in the present invention.

FIG. 4B is a process explanatory view following FIG. 4A.

FIG. 4C is a process explanatory view following FIG. 4B.

FIG. 4D is a process explanatory view following FIG. 4C.

FIG. 5 is a schematic diagram showing a cross-sectional structure of the solar cell used in Experimental Example 2.

FIG. 6 is an enlarged perspective view showing a main part of the solar cell used in Experimental Example 3.

FIG. 7A is a schematic diagram showing a first example of a cross-sectional structure of a main part of a solar cell of the present invention.

FIG. 7B is a schematic view showing a second example.

FIG. 7C is a schematic view showing the third example.

FIG. 7D is a schematic view showing the fourth example.

FIG. 7E is a schematic view showing a fifth example.

FIG. 7F is a schematic view showing the sixth example.

FIG. 7G is a schematic view showing a seventh example.

FIG. 8A is a process explanatory view showing an example in which an etching protective film is formed gradually thicker using a coating solution.

FIG. 8B is a process explanatory view following FIG. 8A.

FIG. 8C is an explanatory view of the step following FIG. 8B.

FIG. 8D is a process explanatory view following FIG. 8C.

FIG. 9A is a diagram illustrating the relationship between the viscosity of a coating solution and the state of formation of an etching protective film. FIG. 9B is an explanatory view following FIG. 9A.

FIG. 9C is an explanatory view following FIG. 9B.

FIG. 9D is an explanatory view following FIG. 9C.

Fig. 1 OA shows the relationship between the form of etching protection film and the form of exposed semiconductor layer FIG.

FIG. 10B is a schematic cross-sectional view showing another example.

FIG. 11A is a schematic cross-sectional view showing a first example of the manufacturing process of the solar cell of the present invention incorporating a transparent conductive layer.

FIG. 11B is a schematic cross-sectional view showing the second example.

FIG. 11C is a schematic cross-sectional view showing the same third example.

FIG. 12 is a schematic cross-sectional view showing a modified example of the formation mode of the output extraction electrode in the solar cell of the present invention incorporating a transparent conductive layer.

FIG. 13A is a diagram illustrating a difference in a current path flowing through a surface layer portion depending on the presence or absence of a transparent conductive layer.

FIG. 13B is an explanatory view following FIG. 13A.

FIG. 14 is a graph showing the current-voltage characteristics of each solar cell in Experimental Example 1.

Fig. 15 is a graph showing the relationship between internal quantum efficiency and wavelength.

Figure 16 is a diagram illustrating the principle of a solar cell using a pn junction.

FIG. 17 is a perspective view schematically showing an example of a form of forming an output extraction electrode on the light receiving surface side.

Figure 18 is an illustration of the current-voltage curve of a solar cell.

FIG. 19A is a schematic diagram for explaining the difference in the form of forming a semiconductor layer exposed portion between the present invention and the conventional method.

FIG. 19B is an explanatory view following FIG. 19A. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, some embodiments of the present invention will be described with reference to the drawings. In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted. FIG. 1A is a cross-sectional view schematically showing one embodiment of the solar cell of the present invention. The solar cell 100 is provided with an impurity diffusion layer 2 (in the present embodiment, on the first main surface side of a silicon single crystal substrate 1 (hereinafter simply referred to as a substrate 1: a p-type in the present embodiment). is formed, forming a pn junction. A layer newly formed near the surface of the semiconductor substrate like the diffusion layer 2 is generically referred to as a semiconductor layer 2 in the present invention. On the surface of the semiconductor layer 2, an insulating film (passivation film) 3, a transparent conductive layer 6, and an output electrode 7 are formed in this order.

Here, an uneven portion is formed on the first main surface of the substrate 1, and the insulating film 3 is formed so as to cover the uneven portion. Then, the semiconductor layer exposed region 5 not covered with the insulating film 3 is formed so as to include the top portion 25 of a part of the many convex portions 15 forming the concave and convex portions. As shown in FIG. 19A in an enlarged manner, the height of the tip of the top 25 of the convex portion 15 in the semiconductor layer exposed region 5 is the height of the insulating film 3 at the outer peripheral edge of the semiconductor layer exposed region 5. It is higher than the maximum height position (that is, the maximum height position of the inner peripheral edge 11 of the insulating film 3). The transparent conductive layer 6 is in direct contact with the semiconductor layer 2 at the top 25 of the projection 15 in the semiconductor layer exposed region 5, and the output extraction electrode 7 formed thereon is However, the semiconductor layer 2 is indirectly in contact with the semiconductor layer 2 via the transparent conductive layer 6.

The semiconductor layer exposed region 5 is preferably formed such that the total area ratio is 1% or less on the main surface (here, the first main surface) of the substrate 1 on which the semiconductor layer exposed region 5 is formed. ,. The semiconductor layer exposed region 5 functions as a contact hole with the transparent conductive layer 6, and the surface recombination speed becomes extremely high at this position. Therefore, by setting the total area ratio to 1% or less, the effective area can be reduced. It is possible to reduce the rate of surface recombination. Thereby, the open-circuit voltage and the conversion efficiency can be improved. On the other hand, if the formation area ratio is not at least about 0.01%, the resistance is increased due to current concentration near the contact, and a sufficient improvement in conversion efficiency cannot be expected.

Single-crystal silicon, which is a constituent material of the substrate 1, has a wavelength range of 400 to 110 nm. Since it has a large refractive index of 0 to 3.5, reflection loss when sunlight is incident becomes a problem. The above irregularities are formed mainly to prevent reflection of the first main surface serving as the light receiving surface of the solar cell. As shown in FIG. 2A, the outer surface has a large number of pins having a (1 1 1) surface. A random texture structure composed of the ramified protrusions 55 can be provided. Such a texture structure can be formed by anisotropically etching the (100) plane of a silicon single crystal using an etching solution such as a hydrazine aqueous solution or sodium hydroxide. The semiconductor layer exposed region 5 can be formed so as to include the tip of the pyramidal projection 55.

In addition, as shown in FIG. 2B, a structure in which V grooves are arranged at regular intervals (the inner surfaces of the grooves are, for example, (1 1 1) planes of silicon single crystal which intersect each other) is employed. You can do it. Such a V-groove can be formed by photolithography, for example, by anisotropic etching using a diluted NaOH solution. In this embodiment, the rib-like portion 56 having a triangular roof shape sandwiched between the V-shaped grooves in contact with each other is a convex portion, and the ridge line portion is the top. The semiconductor layer exposed region 5 can be formed so as to include, for example, only a part of the ridge line. In the present embodiment, the output electrodes can be formed in a regular shape by aligning the shapes of the grooves, and the series loss can be reduced more effectively. Further, if photolithography is used, as shown in FIG. 2C, a grid-like rib 57 having a form in which the rib-like portion 56 of FIG. 2B is cut into a lattice shape can be obtained. In other words, this is to form a so-called inverted pyramid uneven portion in a form in which viramid-shaped concave portions are arranged in a lattice shape. According to this, surface reflection can be more effectively suppressed.

Considering that the antireflection effect is sufficiently obtained and that the process of covering only the top with the etching protective film 4 is easy to perform, the valley bottom of the projection 15 to be formed is considered. It is desirable that the maximum height from the top to the top be 0.1 μπι or more and 30 μππ or less. Next, an oxide film or a nitride film can be used for the insulating film 3. Here, the substrate 1 is a silicon single crystal substrate, and the insulating film 3 is formed by heat treatment in a predetermined atmosphere. It is configured as a silicon oxide or nitride film (which can be formed by, for example, a CVD method). Thereby, the insulating film 3 functions as a passivation film having a low surface recombination speed.

Then, the method of forming the semiconductor layer exposed region 5 on the insulating film 3 is as described above with reference to FIG. For example, a coating solution is prepared using a polymer material having sufficient resistance to etching such as hydrofluoric acid, for example, a novolak resin as a resist material. The viscosity of the coating solution can be adjusted using an appropriate solvent. As shown in FIG. 8A, this coating liquid is applied by a known coating method, for example, a spin coating method or a spray method. Then, in the concave portion 16 formed between the adjacent convex portions 15, 15, the coating liquid is accumulated and the coating layer 24 is formed. Then, when the solvent is evaporated and dried, as shown in FIG. 8B, the coating layer 24 becomes the resist layer 4 ′, and the shape near the bottom of the concave portion 16 is partially filled.

Then, as shown in FIGS. 8C and 8D, by repeatedly forming and drying the coating layer 24, the thickness of the resist layer 4 'gradually increases. When the tops 25 of the projections 15 are exposed to a necessary and sufficient height, the resist layer 4 ′ is stopped from being further formed, and as shown in FIG. It is used as a simple etching protection film 4. In this state, the first main surface side of the substrate is immersed in an etching solution containing hydrofluoric acid or the like to dissolve the insulating film (for example, silicon oxide film) covering the protruding top portion 25 of the projection 15. · If removed, the semiconductor layer exposed region 5 is formed. When the etching is completed, as shown in FIG. 4D, the etching protection film 4 is removed using an organic solvent such as acetone or MEK (methyl ethyl ketone).

The coating liquid used for forming the etching protection film 4 needs to have a viscosity adjusted appropriately (for example, 0.04 to 0.10 · s / m ² ). If the viscosity of the coating liquid is excessively large, the liquid flows around the top part 25 of the convex part 15 to be exposed from the liquid surface of the coating layer 24 due to surface tension, as shown in FIG. 9A. Residue in shape, after drying In this case, as shown in FIG. 9B, an extra etching protective film 4 a remains on the top 25 of the convex portion 15 and hinders etching. On the other hand, when a coating liquid having an appropriately adjusted viscosity is used, as shown in FIG. 9C, the tops 25 of the projections 15 can be exposed from the liquid surface without excess or shortage. In this case, even if a small amount of the etching protection film 4a remains on the top 25 after drying, the remaining film has a thin or porous force or an island shape as shown in FIG. 9D. As a result, a state where the insulating film 3 is at least partially exposed can be reliably formed. In this case, since the etching solution permeates from the exposed portion, the insulating film 3 where the etching protective film 4a remains can also be removed. By reducing the residual amount of the etching protection film 4a at the top of the projection 15 as described above, as shown in FIG. The upper surface 11 of the inner peripheral edge of the insulating film 3 forming the outer peripheral edge of the layer exposed region 5 can be formed flat. This makes it possible to form the semiconductor layer exposed region 5 in which the remaining insulating film 3 is small and the variation in the formation area is kept low.

If the etching protection film 4 can completely cover the periphery of a certain projection 15, as shown in FIG. 7B or FIG. The semiconductor layer exposed region 5 can be formed so as to be covered with the insulating film 3 and the tip of the convex portion 15 projects beyond the upper edge 11 of the insulating film 3. However, the heights of all the projections 15 are not ideally uniform.For example, as shown in FIG. 1OA, the height of the projections 15 is smaller than that of the surrounding projections 15. If the portion 15 ′ is formed, it may be completely buried in the etching protection film 4. In this case, the insulating film 3 on the top portion 25 of these convex portions 15 ′ is naturally not removed. FIG. 7D also shows an example in which the protrusions 15 of the insulating film 3 that are not removed are formed. These projections 15 ′ may be formed to some extent as long as they do not hinder contact with the output extraction electrode 7.

On the other hand, it is ideal that the etching protection film 4 is uniformly filled in all the recesses. However, for example, when a random texture structure is employed, the etching protection film 4 is opened to the outside. As shown in FIG. 10B, there may be formed a concave portion 16 in which the coating liquid does not easily accumulate. In this case, since the etching protection film 4 is not sufficiently formed in the concave portion 16 'and the convex portion 35 adjacent to the concave portion 16', the convex portion from which the insulating film 3 is entirely removed in the semiconductor layer exposed region 5 is formed. May be present as part 35.

As shown in FIG. 11A, in order to uniformly form the semiconductor layer exposed region 5 where the variation in the formation area is small, as shown in FIG. It is desirable to keep them almost constant.

Next, a transparent conductive layer 6, for example, can be configured as a conductive oxide film such as tin oxide (Sn0 ₂₎ or an acid Ihiinjiumu (I n ₂ 0 _3). Specifically, an antimony (Sb) -doped oxidized tin film (so-called Nesa film) or a tin (Sn) -doped oxidized indium film (so-called ITO Mo) has high conductivity. Yes, it can be suitably used in the present invention. Of these, the Nesa film has a high electrical conductivity and contributes particularly to the reduction of the series resistance of solar cells. On the other hand, the ITO film has a slightly lower conductivity than the Nesa film but is inexpensive. Incidentally, in addition to the above Ne support film Ya I TO film, for example, C d ₂ S N_〇 _{_4,} Zn ₂ Sn0 _4, Zn Sn_〇 _{_{_{3, M gln 2 0 4,}}} C d S doped with yttrium (Y) b ₂ 〇 ₆ and G a I n0 ₃ doped with Sn, it may be used as the material of the transparent conductive layer 6.

These conductive oxide films can be formed by a vapor deposition method, for example, a chemical vapor deposition method (Chemical Vapor deposition: CVD) or a physical vapor deposition method such as sputtering and vacuum deposition (Phisical Vapor deposition: PVD). However, another method such as a sol-gel method may be used. As shown in FIG. 11B, the transparent conductive layer 6 is formed so as to collectively cover the semiconductor layer exposed region 5 and the insulating film 3, and as shown in FIG. 7D or FIG. An output extraction electrode 7 is formed on the transparent conductive layer 6. In these figures, the output extraction electrodes 7 are formed in a positional relationship overlapping the semiconductor layer exposed region 5, and since the conductivity of the transparent conductive layer 6 is high, as shown in FIG. The formation position of the use electrode 7 may be slightly deviated from the position of the semiconductor layer exposed region 5. In view of reducing the series resistance of the solar cell 1 0 0, a transparent conductive layer 6, it is desirable to adjust the specific electric resistance to ^{5 X 1 0- 5 ~3 X 1} 0 about one ⁴ Omega · cm . For example, ITO film produced by sputtering may be the value of the electrical resistivity, for example 1 X 1 0 one ^{4 ~ 2 · 8 X 1 0-} 4 Ω. And cm. On the other hand, for the nesa film, a film having a low resistivity of, for example, 1 × 10 ⁴ Ω · cm or less can be obtained by the CVD method.

The transparent conductive layer 6 can function as an anti-reflection film by adopting a material having a different refractive index from that of the silicon single crystal constituting the substrate 1. When functioning as an antireflection film, the constituent material of the transparent conductive layer 6 preferably has a refractive index of 1.5 to 2.5. For example, in the case of a Nesa film, the refractive index is about 2.0, and when the thickness is about 40 to 70 nm, a remarkable antireflection effect can be obtained. In addition, an anti-reflection film may be separately formed together with or instead of the transparent conductive layer 6. By forming the M g F ₂ film lower layer than the refractive index of the transparent electrode layer 6, etc. on a transparent conductive layer 6, the reflectivity is further reduced, the generation current density can be further increased.

The output extraction electrode 7 is formed by printing a desired electrode pattern on the transparent conductive layer 6 by using a paste containing a metal powder such as silver powder by a known thick film printing method such as screen printing. Can be formed. Also, by using a thermosetting paste, it is possible to form the output extraction electrode 7 at a lower temperature. As shown in FIG. 17, the first main surface side of the substrate 1 serves as the light receiving surface of the solar cell.Therefore, the output extraction electrode 7 is used to improve the efficiency of light incidence on the p_n junction 48. For example, it has a thick busbar electrode formed at an appropriate interval to reduce internal resistance, and a finger electrode that branches into a comb shape at a predetermined interval from the busbar electrode. However, when the electric conductivity of the transparent conductive layer 6 is sufficiently high, it is possible to omit the finger electrode or to set the interval between the finger electrodes wide even when the finger electrode is formed.

In the case of using the screen printing as described above, the width of the output extraction electrode 7 (the bus electrode or the finger electrode) is increased to some extent. In this case, Figure 1A or As shown in FIG. 7D, the output extraction electrode 7 is formed so as to extend over the semiconductor layer exposed region 5 and the surrounding insulating layer 3. Since the output electrode 7 formed in such a specific form by screen printing is wide, it is necessary to increase the arrangement interval of a plurality of formed electrodes in order to reduce shadowing loss. However, unlike the solar cell manufactured by the conventional fire-through method, in this configuration, since the transparent conductive layer 6 is formed, the resistance loss is small, and the conversion efficiency 77 can be increased.

Returning to FIG. 1A, an uneven portion is formed on the second main surface of the substrate 1 for preventing back surface reflection, and an insulating film 3 is formed so as to cover the uneven portion. The semiconductor layer exposed portion 5 is formed on the top of the convex portion 15. However, since the second main surface side is not a light receiving surface, the entire surface is covered with the output extraction electrode 8. When the thickness of the substrate 1 is reduced in order to reduce the weight of the solar cell, the thickness of the substrate 1 is reduced as shown in Fig. 1B to prevent recombination and disappearance of minority carriers at the electrode 8 on the second main surface side. As shown, a high-concentration diffusion layer 9 having the same conductivity type as that of the substrate 1 and a higher concentration can be formed on the second main surface side (so-called BSF (oack surface rield) layer).

Hereinafter, the operation of the solar cell 100 of FIG. 1 will be described. As shown in FIG. 16, when the solar cell 100 absorbs photons having energy equal to or greater than the forbidden band width by light irradiation, electrons and holes are generated by photoexcitation in the P-type region and the n-type region, as shown in FIG. They are generated as minority carriers and diffuse toward the junction. At the junction, an internal electric field (a so-called “build-in” electric field) is generated due to the formation of the electric double layer. The electrons and holes diffused as minority carriers cause the internal electric field to The electrons are in the n-type region and the holes are

Each is drawn into and separated from the P-type region and becomes a majority carrier. As a result, the P-type region and the n-type region are positively and negatively charged, respectively, and an electromotive force ΔE of the solar cell is generated between the electrodes (7, 8 in FIG. 1) provided in each part.

Here, in the case of passivating the substrate surface with an insulating film, if a contact hole is formed by a fire-through method, the semiconductor layer 2, here, an emission layer that is a surface n-type layer is formed. The dopant concentration of the data layer 3 X 1 0 ² ° cm one ³ (sheet resistance in terms: 4 0 Omega / mouth) to be set to extent below the resistance of the electrode contact portion formed at full Iyer through + It cannot be reduced to a reasonable value, for example, about 0.01 Ωcm ² . In other words, in the fire-through method, the dopant concentration of the semiconductor layer 2 was inevitably increased in order to reduce the contact resistance loss. In addition, even if the width of the output electrode 7 formed by screen printing is narrow, it is necessary to secure 100 μππ or more. In order to reduce the shadowing loss to about 5%, for example, the pitch between the electrodes is required. Need to be 2-3mm.

However, according to the configuration of the solar cell 100 of FIG. 1, the semiconductor layer exposed region 5 serving as a contact horn can be easily formed by a simple etching without using a fire-through method. . Therefore, naturally, the dopant concentration of the semiconductor layer 2 can be set to a value smaller than 3 × 10 ² ° cm− ³ (in terms of sheet resistance: 40 Ω / port). Further, as shown in FIG. 13B, since the transparent conductive layer 6 is used, the current is longer in the lateral direction in the semiconductor layer 2 than in the case of FIG. 13A without the transparent electrode layer 6. There is no need to flow away. For example, when using a Nesa film or an IT film as the transparent conductive layer 6, if there is a thickness (40 to 70 nm) to be used as an antireflection film, the sheet resistance is about 10 to 25 Ω square. Can be lowered. As a result, the output resistance electrode 7 provided on the transparent conductive layer 6 has a much smaller series resistance than conventional ones (2 to 3 mm), for example, even if it is doubled, so shadowing loss is greatly reduced. can do.

In the above embodiment, the uneven portions are formed by etching. However, the uneven portions may be formed by mechanical processing. For example, a groove shape as illustrated in FIG. 2B can be easily formed by cutting. For example, by rotating a plurality of rotary blades arranged in the axial direction to a predetermined depth from the substrate surface and rotating the substrate and the rotary blades relative to each other in a groove forming direction, a plurality of rows of groove portions can be collectively formed. Can be formed. In the present invention, when there is no concern that the series resistance increases so much, the transparent conductive layer 6 is omitted as shown in FIGS. 7A to 7C or FIG. In, the output extraction electrode 7 can be brought into direct contact with the semiconductor layer 2. In this case, as shown in FIG. 7F, the remaining semiconductor layer exposed region 5 ′ where the output extraction electrode 7 is not formed can be covered with the auxiliary insulating layer 10. In the example of this figure, the auxiliary insulating layer 10 is assumed to cover the remaining semiconductor layer exposed region 5 ′, the insulating film 3 and the output extracting electrode 7 collectively after forming the output extracting electrode 7. Is formed. As the material of the auxiliary insulating layer 10, an inorganic insulating film such as silicon nitride or silicon oxide can be used. In this case, by appropriately adjusting the formation thickness of the auxiliary insulating layer 10, this can also function as an antireflection film. (Experimental example)

The following is a description of the results of experiments conducted to confirm the effects of the present invention.

(Experimental example 1)

The solar cell shown in FIG. 1A was manufactured by the steps shown in the flowchart of FIG. First, a p-type crystalline silicon substrate 1 (boron-doped product having a resistivity of 2 Ω · cm (dopant concentration 7.2 × ^{10 15} cm— ³ )) cut out of a silicon single crystal ingot in an as-sliced state was prepared. The thickness of the substrate 1 is 300 / zm. The substrate 1 is sodium hydroxide aqueous solution (concentration:. 4 0 mass / ₀₎ by chemically etching, after removal of the dust image layer by slice, hydroxyl Ihinatoriumu solution (hydroxide plus I isopropyl alcohol Ihinatoriumu concentration. 3 weight ⁰ /) soaked by wet etching to form a囬凸of random textures embodiment shown in FIG. 2 a on both main surfaces of the substrate 1. After cleaning the substrate 1 on which the unevenness was formed, phosphorus was thermally diffused to form an n-type diffusion layer 2 (phosphorus diffusion layer) having a sheet resistance of 200 ΩΖ on the first main surface. Next, after removing the phosphorus glass generated on the surface of the substrate by etching, oxidation was performed to form a silicon dioxide film having a thickness of about 5 nm as an insulating film 3 on both main surfaces. Then, the coating liquid is applied to both sides while being sequentially dried by a spin-on method, so that as shown in FIG. An etching protection film 4 mainly composed of novolak resin was formed so that some of 5 would pop out. Subsequently, the substrate was immersed in a 10% by mass aqueous solution of hydrofluoric acid, and only the insulating film 3 on the top 25 was etched to form the exposed portion 5 of the semiconductor layer. Next, the substrate was immersed in acetone to dissolve and remove the etching protection film 4.

Next, an antimony-doped tin dioxide film doped with antimony was deposited as a transparent conductive layer 6 on the first main surface of the substrate 1 at normal pressure CVD. The thickness of the transparent conductive layer 6 was set to 60 nm because it also served as an anti-reflection film. Next, on the first main surface of the substrate 1, a pattern of the output extraction electrode 7 in the form shown in FIG. 17 was formed on the surface by a screen printing method using silver paste, and aluminum was formed on the entire second main surface. The pattern of the output extraction electrode 8 was formed using the paste. Thereafter, hydrogen annealing was performed at a temperature of 400 ° C. to complete the solar cell 100 (Example product 1).

In the above-described phosphorus diffusion step, a high concentration p-type diffusion layer 9 (BSF) was formed on the rear surface as shown in FIG. A sample of the solar cell 101 provided with the layer was also manufactured (Example product 2). On the other hand, a solar cell manufactured using the same fire-through technique using the same substrate 1 as described above was also manufactured (comparative example product). Note that the transparent electrode 6 was not formed in the comparative example product. Each solar cell was subjected to a performance evaluation test as follows. That is, it is assembled into a solar cell unit having a light receiving area of 10 cm square, and is heated at 25 ° C using a solar simulator (light intensity: 1 kW / m ² , spectrum: AM I.5 global). The current-voltage characteristics were measured. Figure 14 shows the results. Table 1 shows the solar cell characteristics of these solar cells. Figure 15 shows the internal quantum efficiency of these solar cells. table 1

In the example product 1 and the example product 2, the sheet resistance of the emitter layer as the semiconductor surface layer 2 could be set to 200 Ω / port. On the other hand, in the comparative example using the fire-through method, the sheet resistance was 40 to 50 Ω / port. And, as shown in Table 1, it can be seen that the fill factor is not reduced in the example product 1 and the example product 2 as compared with the comparative example product. This is considered to be because the sheet resistance of the transparent conductive layer in Example Product 1 and Example Product 2 was low, and the increase in contact resistance was suppressed.

Further, as compared with the comparative example, the open-circuit voltage of the example product 1 and the example product 2 is significantly improved. This is probably because the dopant concentration of the emitter layer was reduced, the surface recombination rate was reduced, and the area of the contact hole based on the semiconductor layer exposed region 5 could be limited. The surface area of the substrate 1 used in Example Product 1 and Example Product 2 was determined by scanning electron microscope (SEM) .As a result, the total area ratio of the semiconductor layer exposed region 5 on the first main surface was approximately 1%. I confirmed that it was.

As compared with the comparative example, the short-circuit current of the comparative example 1 and the comparative example 2 also increased. This is thought to be due to a reduction in shadowing loss and an increase in short wavelength sensitivity. In the comparative example, the current flows laterally in the emitter layer. Flows through Layer 6. The sheet resistance of the transparent conductive layer 6 is approximately 10 Ω / square, and the same resistance loss can be achieved even if the electrode pitch is doubled, for example, as compared with the comparative example. Therefore, the shadowing loss can be halved, which is considered to have contributed greatly to the increase in short-circuit current. In addition, as shown in FIG. 15, it can be seen that Example Product 1 and Example Product 2 also have increased short-wavelength sensitivity. This is because, as described above, the dopant concentration in the emitter layer was lowered, and the surface recombination rate was reduced.

In the example product 1 and the example product 2, the open-circuit voltage, the short-circuit current, and the fill factor were each increased, so that a conversion efficiency of about 20% could be obtained. In particular, in the example product 2 in which the BSF layer was introduced on the back side, a solar cell having a conversion efficiency exceeding 20% was obtained.

In the solar cell according to the present embodiment, the electrodes are formed on the entire back surface. However, similarly to the front surface, a transparent conductive film and a comb-shaped electrode are formed on the back surface side, and a structure in which light enters from the back surface side may be adopted. I do not care. Although an n-type diffusion layer having a thickness of 200 Ω / port was formed, if the value could be set to a value higher than 100 Ω / port, the short-wavelength sensitivity would increase and the solar cell characteristics would improve. Further, in the manufacturing process, an oxide film (silicon dioxide film) was used as an insulating film in this embodiment, but a silicon nitride film may be used. Although the thermal diffusion method is used for forming the diffusion layer, any means such as an ion implantation method and a spin-on method can be used as long as the structure of the present invention can be formed. (Experimental example 2)

A solar cell 103 having the structure shown in FIG. 5 was produced as follows. First, a p-type single crystal silicon substrate 1 (a gallium-doped product having a thickness of 250 μm and a resistivity of 0.5 Ω · cm) prepared by the CZ method was prepared. After etching, random textured surfaces were formed on both surfaces. After texturing, a coating agent containing P ₂ 0 ₅ was coated cloth, 8 5 by thermal diffusion at 0 ° C, the sheet resistance on the surface of about 1 0 0 Omega / mouth of the n-type diffusion layer 2 Was formed.

Thereafter, pyrogenic acid was performed at 800 ° C., and a semiconductor layer exposed region 5 was formed in the same manner as in Experimental Example 1. Thereafter, the same output extraction electrodes 7 and 8 as in Experimental Example 1 were formed on the first and second main surfaces, respectively. Subsequently, a silicon nitride film was formed by plasma CVD as an auxiliary insulating film 10 also serving as an anti-reflection film, thereby completing a solar cell 103 (Example product 3). At this time, the substrate temperature was set to 400 ° C., and after the film was deposited, the same hydrogen annealing treatment as in Experimental Example 1 was performed. A performance evaluation test was performed on Example product 3 in the same manner as in Experimental example 1. Table 2 shows the results

Table 2

According to this, it can be seen that the short circuit current is reduced in the example product 3 as compared with the example products 1 and 2 described above, while the open circuit voltage is increased. It is considered that the reason why the short-circuit current decreased was that the electrode width and electrode pitch were not different from those of the conventional method. That is, the shadowing area was increased as compared with the products of Examples 1 and 2 shown in Table 1. On the other hand, the reason why the open-circuit voltage increased was thought to be that the substrate resistivity was reduced from 2.0 Ω · 111 to 0.5 Ω · cm. In general, lowering the substrate resistivity decreases the reverse saturation current density and increases the open-circuit voltage. However, if the resistivity of a p-type substrate is about 2.0 Ω · cm, it is necessary to consider the problem of light degradation. Photodegradation is a phenomenon in which when solar cells are irradiated with strong light, the lifetime of the solar cell substrate is reduced and sufficient conversion efficiency cannot be obtained. In order to examine the presence or absence of this photodegradation, a solar cell fabricated using the above-mentioned gallium-doped CZ silicon single crystal substrate and a normal boron-doped CZ silicon single crystal substrate (resistivity 0.5 Ω · cm) were used. We continued irradiating the solar cell fabricated by exactly the same method with the simulated sunlight at 25 ° C under the above-mentioned solar simulator, and examined the light irradiation time dependency of the current-voltage characteristics. As a result, the conversion efficiency of the solar cell fabricated from the boron-doped substrate was reduced by about 10% when irradiated under simulated solar light for 10 hours. On the other hand, the solar cell using the gallium-doped substrate showed a slight change in conversion efficiency, but no change in characteristics corresponding to deterioration. Thus, by using a gallium-doped substrate, the problem of light degradation could be avoided, and the open-circuit voltage and conversion efficiency could be improved. In this example, a gallium-doped p-type substrate by the CZ method was used, but the photodegradation problem can be avoided even with an MCZ substrate or an FZ substrate having an interstitial oxygen concentration of several ppm or less. Also, even if an n-type substrate is used and a p-type emitter layer is formed using boron or the like, the problem of light degradation can be avoided. (Experimental example 3)

The solar cell 104 shown in FIG. 6 was manufactured as follows (note that in FIG. 6, in order to avoid complication, only the portion near the surface is shown without drawing the uneven portions and the antireflection film). T). First, a p-type single-crystal silicon substrate 1 (boron-doped product having a thickness of 250 m and a resistivity of 2 Ω · cm) prepared by the CZ method was prepared. Square rib-shaped protrusions 45, 45 were formed at intervals of 2 mm (the area between the protrusions 45, 45 can be regarded as a recess). At this time, the height from the first main surface of the substrate 1 to the top of each of the projections 45, 45 was set to about 30 μπι.

Next, after the damaged layer was chemically etched, a random texture structure with a height of about 5 μππ was formed on both main surfaces as irregularities. After that, thermal diffusion is performed in the same manner as in Experimental Example 2, an η-type diffusion layer 2 having a sheet resistance of about 100 Ω / port is formed on the surface, and then thermal oxidation is performed. As a result, an oxygen film as the insulating film 3 was formed. Then, an etching protection film is formed on the second main surface side in the same manner as in Experimental Example 1, while a hydrofluoric acid resistant printing resist made of rubber resin is formed on the first main surface as an etching protection film. It was applied using screen printing so as to have a thickness of 20 / m. By doing so, the tops 25 of the projections 45, 45 first formed by the dicer periodically protrude from the print resist surface in the ridge direction.

After the resist was dried, the substrate 1 was immersed in a 10% by mass aqueous hydrofluoric acid solution to form a semiconductor layer exposed portion 5 on the tops 25 of the projections 45, 45. Then, after the resist was washed away using a solvent, the pattern of the output electrode 7 shown in FIG. 6 was formed on the first main surface using silver paste by screen printing, and the aluminum was printed on the second main surface. The pattern of the output electrode 8 was formed on the entire surface using the paste. At this time, it is necessary to align the output extraction electrode 7 on the first main surface side so as to be printed so as to overlap the semiconductor layer exposed portion 5 on the tops of the projections 45, 45. Since the width of the electrode 7 is about 10 times the width of the semiconductor layer exposed portion 5 with respect to the width, the positioning can be performed relatively roughly. Subsequently, as the anti-reflection film T I_〇 ₂ film was formed to a thickness of a (not shown) 6 0 nm by normal pressure CVD, thereby completing the solar cell 1 0 4 (Example Product 4) .

The performance of Example product 4 was evaluated in the same manner as in Experimental example 1. Open circuit voltage 0.667 V, short-circuit current density 36.9 mA / cm ² , fill factor 0.770, conversion efficiency 19.0% was obtained, and the characteristics were improved compared to the conventional screen printing fire-through method.

Claims

The scope of the claims

1. In a solar cell in which an uneven portion is formed on a main surface of a semiconductor substrate and the main surface is covered with an insulating film, a shape including at least a part of a top of the convex portion forming the uneven portion. A semiconductor layer exposed region not covered with the insulating film is formed on the main surface, and a tip height position force of a top of the convex portion in the semiconductor layer exposed region. It is higher than the maximum height position of the insulating film at the outer peripheral edge, and is in direct contact with the top of the protrusion in the semiconductor layer exposed region or indirectly via another conductive layer. A solar cell, wherein an output extraction electrode is formed.

2. The solar cell according to claim 1, wherein a base end side outer peripheral surface of the convex portion is covered with the insulating film, and a distal end portion of the convex portion protrudes from an upper edge of the insulating film. battery.

3. The solar cell according to claim 1, wherein an upper surface of an inner peripheral portion of the insulating film that forms an outer peripheral edge of the semiconductor layer exposed region is formed flat.

4. The other conductive layer is a transparent conductive layer that covers the semiconductor layer exposed region and the insulating film collectively, and the output extraction electrode is formed on the transparent conductive layer. A solar cell according to any one of Items 1 to 3.

5. In a solar cell in which a main surface of a semiconductor substrate is covered with an insulating film, a semiconductor layer exposed region that is not covered with the insulating film is formed on the main surface, and the semiconductor layer exposed region and the insulating layer are not covered with the insulating film. A solar cell, wherein a transparent conductive layer covering the film and the film is formed, and an output extraction electrode is formed on the transparent conductive layer.

6. The plurality of semiconductor layer exposed regions are formed on the main surface, and in some of the semiconductor layer exposed regions, the output extraction electrode is formed directly in contact with the semiconductor layer, while the output extraction electrode is formed. The solar cell according to any one of claims 1 to 3, wherein a remaining semiconductor layer exposed region where no electrode is formed is covered with a transparent auxiliary insulating layer.

7. In a solar cell in which the main surface of a semiconductor substrate is covered with an insulating film, a plurality of semiconductor layer exposed regions not covered with the insulating film are formed on the main surface, and the semiconductor layer exposed region is In some, the output extraction electrode is formed in direct contact with the semiconductor layer, while the remaining semiconductor layer exposed region where the output extraction electrode is not formed is covered with a transparent auxiliary insulating layer. A solar cell.

8. The solar cell according to claim 6, wherein the auxiliary insulating layer collectively covers the remaining semiconductor layer exposed region, the insulating film, and the output extraction electrode.

9. The semiconductor layer exposed region covers the main surface of the semiconductor substrate with the insulating film so as to include the HQ convex portion, and further covers the insulating film in a region other than the top of the convex portion. 9. The solar cell according to any one of claims 1 to 8, wherein the solar cell is formed by covering with an etching protective film, and thereafter removing the insulating film on the top of the projection by etching.

10. An uneven portion is formed on a main surface of the semiconductor substrate, the main surface is covered with an insulating film, and the insulating film is formed so as to include a top of at least a part of the convex portion forming the uneven portion. A semiconductor layer exposed region not covered by the semiconductor layer is formed on the main surface, and directly or indirectly contacts the top of the projection in the semiconductor layer exposed region via another conductive layer. Thus, in the solar cell in which the output extraction electrode is formed,

The semiconductor layer exposed region covers the main surface of the semiconductor substrate with the insulating film so as to include the irregularities, and further etches the insulating film in a region other than the top of the convex portion. A solar cell formed by covering with a film and then removing the insulating film on the top of the convex portion by etching.

11. The solar cell according to any one of claims 1 to 10, wherein the uneven portion comprises at least one of a texture, a V-groove, and an inverted viramid.

12. The semiconductor layer exposure region according to claim 1, wherein the semiconductor layer exposure region is formed such that a total area ratio is 1% or less on a main surface on which the semiconductor layer exposure region is formed. A solar cell according to any one of the above items.

13. The solar cell according to any one of claims 1 to 12, wherein the output extraction electrode is formed so as to extend over the semiconductor layer exposed region and a surrounding insulating layer.

14. A step of forming an HQ projection on the main surface of the semiconductor substrate;

A step of covering the main surface of the semiconductor substrate with the insulating film so as to include the irregularities; and covering the insulating film with an etching protection film in a region other than the top of the convexes forming the irregularities. Process and

Thereafter, the insulating film on the top of the projection is removed by etching to expose a semiconductor layer exposed region not covered with the insulating film so as to include the top of at least a part of the projection. Forming a;

A method for manufacturing a solar cell, comprising:

15. The method of manufacturing a solar cell according to claim 14, further comprising a step of forming the round protrusion by etching.

16. The method of manufacturing a solar cell according to claim 14 or 15, further comprising a step of forming the uneven portion by mechanical processing.

17. A step of forming a plurality of the semiconductor layer exposed regions on the main surface, and a step of forming the output extraction electrode in direct contact with the semiconductor layer in a part of the semiconductor layer exposed regions; 17. The method for manufacturing a solar cell according to claim 14, further comprising: covering the remaining semiconductor layer exposed region where the output extraction electrode is not formed with an auxiliary insulating layer.

18. The method for manufacturing a solar cell according to claim 17, wherein the auxiliary insulating layer is formed so as to collectively cover the remaining semiconductor layer exposed region, the insulating film, and the output extraction electrode. .