CN102244079B - Power transistor chip structure of mesa technology and implementation method - Google Patents
Power transistor chip structure of mesa technology and implementation method Download PDFInfo
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- CN102244079B CN102244079B CN 201110213277 CN201110213277A CN102244079B CN 102244079 B CN102244079 B CN 102244079B CN 201110213277 CN201110213277 CN 201110213277 CN 201110213277 A CN201110213277 A CN 201110213277A CN 102244079 B CN102244079 B CN 102244079B
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- 238000000034 method Methods 0.000 title claims description 45
- 238000005516 engineering process Methods 0.000 title abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 86
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 86
- 239000010703 silicon Substances 0.000 claims abstract description 86
- 238000009792 diffusion process Methods 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000011521 glass Substances 0.000 claims abstract description 35
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 32
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000013078 crystal Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000004411 aluminium Substances 0.000 claims description 27
- 238000005498 polishing Methods 0.000 claims description 21
- 238000005245 sintering Methods 0.000 claims description 20
- 230000007797 corrosion Effects 0.000 claims description 19
- 238000005260 corrosion Methods 0.000 claims description 19
- 238000001259 photo etching Methods 0.000 claims description 16
- 238000011049 filling Methods 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 11
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
- 239000011574 phosphorus Substances 0.000 claims description 11
- 238000012545 processing Methods 0.000 claims description 11
- 239000000126 substance Substances 0.000 claims description 8
- 238000000637 aluminium metallisation Methods 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 claims description 5
- 238000012856 packing Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 5
- 230000009477 glass transition Effects 0.000 claims description 3
- 230000008961 swelling Effects 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 8
- 239000000377 silicon dioxide Substances 0.000 abstract description 8
- 238000002161 passivation Methods 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 230000001681 protective effect Effects 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 32
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 30
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 18
- 229910052757 nitrogen Inorganic materials 0.000 description 18
- 229910052760 oxygen Inorganic materials 0.000 description 18
- 239000001301 oxygen Substances 0.000 description 18
- 239000008367 deionised water Substances 0.000 description 12
- 229910021641 deionized water Inorganic materials 0.000 description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 12
- 229910052796 boron Inorganic materials 0.000 description 9
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- 238000001035 drying Methods 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000001459 lithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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Abstract
The invention relates to a power transistor chip structure of a mesa technology. The structure comprises an N+ emitter region, an emitting electrode aluminum electrode, a base pole aluminum electrode, a SiO2 protective film, glass passivation films, an N+ substrate diffusion layer, a P-type base region diffusion layer and a silicon single crystal chip; the front side of the silicon single crystal chip is provided with the P-type base region diffusion layer; the back side of the silicon single crystal chip is provided with the N+ substrate diffusion layer; the surface of the P-type base region diffusion layer is provided with the SiO2 protective film, the base pole aluminum electrode, the N+ emitter region and the emitting electrode aluminum electrode; front surface grooves are arranged on the silicon single crystal chip and the P-type base region diffusion layer; and the base parts and the side walls of the front surface grooves are provided with the glass passivation films. The structure is characterized in that the periphery of the back side of the N+ substrate diffusion layer is provided with a back side stress balance groove; the top part and the side wall of the back side stress balance groove are provided with glass films; and a plurality of layers of metal electrodes are arranged on the N+ substrate diffusion layer and the surfaces of the glass films. The structure provided by the invention has the advantages of mature structure and technology, simple manufacturing process, good breakdown voltage property of the manufactured chip, and high reliability of products.
Description
Technical field
The present invention relates to a kind of chip structure for power transistor produced with mesa process, also relate to a kind of mesa technique power transistor chip implementation method, belong to power semiconductor device manufacturing technology field.
Background technology
Power transistor is in the manufacture of middle high-pressure electric power semiconductor device chip, so far still extensively adopt the mesa technique manufacturing technology, as Figure 1-4, the thick passivation glass film of one deck 30～50um of having grown in the groove in silicon wafer front, due to the coefficient of expansion of this glass-film, than silicon, much larger (coefficient of expansion of general passivation glass is 4.4 ± 0.4 * 10
-6/ ℃, and the coefficient of expansion of silicon is 2.6 * 10
-6/ ℃); after glass sintering completes; glass-film in the groove of front has produced a very large shrinkage stress; pull silicon wafer to be bent upwards, because the bending of silicon wafer makes silicon chip central area and lithography mask version not to be adjacent to, produce gap, cause waste product to produce; often can fall sheet; the silicon wafer percentage of damage is very high, and this method is only suitable in the processing procedure of 4 inches silicon wafers of 2 inches～Φ of Φ, is difficult to the silicon wafer processing procedure for 4 inches of 5 inches～Φ of Φ by above technology.
Summary of the invention
The purpose of this invention is to provide a kind of chip structure for power transistor produced with mesa process, a kind of mesa technique power transistor chip implementation method also is provided simultaneously.
The technical solution used in the present invention is: comprise N
+emitter region, emitter aluminium electrode, base stage aluminium electrode, SiO
2diaphragm, glassivation film, N
+substrate diffusion layer, P type base diffusion layer and silicon single crystal flake, described silicon single crystal flake front is provided with P type base diffusion layer, and the described silicon single crystal flake back side is provided with N
+the substrate diffusion layer, described P type is provided with N in base
+emitter region, diffusion layer surface, described P type base and N
+the surface, emitter region is provided with SiO
2diaphragm, base stage aluminium electrode and emitter aluminium electrode, described silicon single crystal flake and P type base diffusion layer are provided with the front groove, and described front channel bottom and sidewall are provided with the glassivation film, it is characterized in that: described N
+substrate diffusion layer back periphery is provided with back side stress equilibrium groove, and stress equilibrium groove top, the described back side and sidewall are provided with glass-film, described N
+substrate diffusion layer surface and glass-film surface are provided with multilayer metallic electrode.
Described back side stress equilibrium groove depth is 50-110um, and described back side stress equilibrium well width is 100-240um.。
Mesa technique power transistor chip implementation method, comprise N
+the step of substrate diffusing step, front polishing attenuate, front side of silicon wafer is carried out to the step of chemical corrosion or chemico-mechanical polishing, positive P type base spread and grow oxide layer step, the positive emitter window step of photoetching, N
+emitter region phosphorus spread and grow oxide layer step, photoengraving groove step, in groove filling glass carry out sintering step and subsequent processing steps, described N
+the substrate diffusing step is N
+the substrate diffusion, form the high concentration substrate layer, the step of described front polishing attenuate is for removing the N of front side of silicon wafer by the method for mechanical lapping
+substrate layer, the corrosion window that described photoengraving groove step is the photoetching front, and go out the ring-shaped groove of certain depth at front etch, described in groove filling glass carry out sintering step for filling glass carry out sintering in groove, the glass-film after burning till is as the terminal passivating film of P-N knot, described subsequent processing steps is growth LTO passivating film, glass-film is protected, fairlead in positive photoetching base and emitter region, at positive AM aluminum metallization film, anti-carve positive aluminium electrode, alloy, remove back side oxide layer, back side evaporation metal electrode, chip testing and sorting, scribing, carry out the chip separation, check, packing, described photoengraving groove step be photoetching just, the corrosion window at the back side, and just, the back side erodes away groove simultaneously, gash depth is 50-110um, groove width is 100-240um, filling glass carry out sintering in the groove of front and back, burn till the passivating film of the glass-film of rear front groove as the P-N knot, the glass-film that burns till rear backside trench as the convergent force in balance front for flattening silicon chip, 3-6h anneals under glass transition point-(10～20) ℃, realize reducing the glass swelling coefficient.
Advantage of the present invention is: structure and technical maturity, manufacture process is simple, the chip breakdown voltage characteristics of manufacturing is good, qualification rate is higher, and product reliability is higher, chip passive region at silicon chip back side has dug out a groove that adjacent chips is shared, we are referred to as to call the stress equilibrium groove, glass sintering have been filled in this stress equilibrium groove, formed one deck glass-film at its top and sidewall, make silicon chip smooth, processing procedure after glassivation is accessible, reduce the percentage of damage of silicon wafer in processing procedure, the method that has adopted two sides simultaneously to process, in the temperature-fall period of glass sintering, having increased at " glass transition point-(10～20) ℃ " lower annealing process further reduces the glass swelling coefficient.
The accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the chip structure for power transistor produced with mesa process schematic diagram that background technology is mentioned.
Fig. 2 is the mesa technique power transistor chip manufacture process schematic diagram that background technology is mentioned.
Fig. 3 is the silicon chip flexibility schematic diagram of background technology after for the major diameter silicon wafer.
The glass sintering temperature curve that Fig. 4 is background technology.
Fig. 5 is chip structure for power transistor produced with mesa process schematic diagram of the present invention.
Fig. 6 is mesa technique power transistor chip manufacture process schematic diagram of the present invention, wherein a, N
+the substrate diffusion, b, front attenuate, c, positive mirror polish, d, the diffusion of positive P type base, e, positive base window, f, the N of sending out of photoetching
+send out the base diffusion, g, dual surface lithography corrosion window etching tank, filling glass sintering in h, groove, i, photoetching front fairlead, j, positive AM aluminum metallization film, k, anti-carve front side aluminum electrode, l, back metal electrode.
Fig. 7 is the silicon chip flexibility schematic diagram of the technology of the present invention after for the major diameter silicon wafer.
The glass sintering temperature curve that Fig. 8 is the technology of the present invention.
Wherein: 1, N
+emitter region, 2, emitter aluminium electrode, 3, base stage aluminium electrode, 4, SiO
2diaphragm, 5, the glassivation film, 6, N
+the substrate diffusion layer, 7, P type base diffusion layer, 8, silicon single crystal flake, 9, the front groove, 10, metal electrode, 11, back side stress equilibrium groove, 12, glass-film.
Embodiment
As shown in Fig. 5, Fig. 6, Fig. 8, chip structure for power transistor produced with mesa process, comprise N
+emitter region 1, emitter aluminium electrode 2, base stage aluminium electrode 3, SiO
2diaphragm 4, glassivation film 5, N
+substrate diffusion layer 6, P type base diffusion layer 7 and silicon single crystal flake 8, silicon single crystal flake 8 fronts are provided with P type base diffusion layer 7, and silicon single crystal flake 8 back sides are provided with N
+substrate diffusion layer 6, be provided with N in P type base diffusion layer 7
+emitter region 1, P type base diffusion layer 7 and N
+the surface of emitter region 1 is provided with SiO
2diaphragm 4, base stage aluminium electrode 3 and emitter aluminium electrode 2, silicon single crystal flake 8 and P type base diffusion layer 7 are provided with front groove 9, and front groove 9 bottoms and sidewall are provided with glassivation film 5, N
+substrate diffusion layer 6 back peripheries are provided with back side stress equilibrium groove 11, and back side stress equilibrium groove 11 degree of depth are 50um, and back side stress equilibrium groove 11 width are 100um, and stress equilibrium groove 11 tops, the back side and sidewall are provided with glass-film 12, N
+substrate diffusion layer 6 and glass-film 12 surfaces are provided with multilayer metallic electrode 10.
As shown in Fig. 6, Fig. 7 and Fig. 8, mesa technique power transistor chip implementation method comprises:
N
+substrate diffusing step: a, use HF:H
3pO
4: HNO
3=1:2:5 corrodes 30 Sec to silicon single crystal flake, removes the damage layer on silicon single crystal flake surface, uses deionized water rinsing 10 times; B, RCA clean, and use deionized water rinsing 15 times; C, drying; D, high concentration phosphorus give deposition, under 1195 ℃, pass into and carry POCL
3nitrogen and oxygen, spread 3.9 h, form N
+sedimentary deposit, require R
□=0.27 Ω/; E, knot, under 1270 ℃, nitrogen and oxygen atmosphere, spread 156 h, forms the dark N of 170um
+substrate layer.
The step of front polishing attenuate: with wafer lapping machine, the front of silicon chip is ground, remove positive N
+substrate layer, after attenuate, silicon wafer thickness is 285 um;
Front side of silicon wafer is carried out to the step of chemical corrosion or chemico-mechanical polishing: the front side of silicon wafer by the method for chemical corrosion or chemico-mechanical polishing after to attenuate carries out polishing, and the silicon wafer thickness after polishing is 265um;
Positive P type base spread and grows oxide layer step: a, silicon chip is carried out to the RCA cleaning, use deionized water rinsing 15 times; B, drying; C, front side of silicon wafer are coated with the boron source; D, boron give deposition, under 945 ℃, nitrogen and oxygen atmosphere, spread 0.9 h, form P type sedimentary deposit, require R
□=29 Ω/; E, knot, under 1230 ℃, nitrogen and oxygen atmosphere, spread 12 h, forms the dark p type diffused layer of 22um;
The positive emitter window step of photoetching: utilize sol evenning machine that photoresist is coated in to front side of silicon wafer, through the front baking of 95 ℃/20min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, remove cull, clean, dry;
N
+emitter region phosphorus spread and grow oxide layer step: a, silicon chip is carried out to the RCA cleaning, with deionized water rinsing 15 times; B, drying; C, phosphorus give deposition, under 920 ℃, pass into and carry POCL
3nitrogen and oxygen, spread 1 h, form N
+sedimentary deposit, require R
□=4 Ω/; D, knot, under 1170 ℃, nitrogen and oxygen atmosphere, diffusion 2.5h, form emitter region, controls h
fEmeet the requirements;
Photoengraving groove step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 95 ℃/20min, utilize mask aligner, mask plate to carry out double-sided exposure, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, cleans, dry, utilize HF:HN0
3 : CH
3 cOOH=3:1:1 erodes away the groove of front and back simultaneously, removes cull, cleans, and dries;
Filling glass carry out sintering step in groove: prepare glass and stick with paste, glass is stuck with paste and scraped silicon chip surface, wipe the outer glass of groove and stick with paste, according to the temperature curve shown in Fig. 8, carry out sintering;
Subsequent processing steps: a, growth LTO passivating film are for the protection of glass-film; B, at the fairlead of positive photoetching base and emitter region; C, at positive AM aluminum metallization film; D, anti-carve positive aluminium electrode; E, alloy; F, removal back side oxide layer; G, back side evaporation metal electrode; H, chip testing and sorting; I, scribing, carry out the chip separation; J, check; K, packing.
As shown in Fig. 5, Fig. 6, Fig. 8, chip structure for power transistor produced with mesa process, comprise N
+emitter region 1, emitter aluminium electrode 2, base stage aluminium electrode 3, SiO
2diaphragm 4, glassivation film 5, N
+substrate diffusion layer 6, P type base diffusion layer 7 and silicon single crystal flake 8, silicon single crystal flake 8 fronts are provided with P type base diffusion layer 7, and silicon single crystal flake 8 back sides are provided with N
+substrate diffusion layer 6, be provided with N in P type base diffusion layer 7
+emitter region 1, P type base diffusion layer 7 and N
+the surface of emitter region 1 is provided with SiO
2diaphragm 4, base stage aluminium electrode 3 and emitter aluminium electrode 2, silicon single crystal flake 8 and P type base diffusion layer 7 are provided with front groove 9, and front groove 9 bottoms and sidewall are provided with glassivation film 5, N
+substrate diffusion layer 6 back peripheries are provided with back side stress equilibrium groove 11, and back side stress equilibrium groove 11 degree of depth are 80um, and back side stress equilibrium groove 11 width are 170um, and stress equilibrium groove 11 tops, the back side and sidewall are provided with glass-film 12, N
+substrate diffusion layer 6 and glass-film 12 surfaces are provided with multilayer metallic electrode 10.
As shown in Fig. 6, Fig. 7 and Fig. 8, mesa technique power transistor chip implementation method comprises:
N
+substrate diffusing step: a, use HF:H
3pO
4: HNO
3=1:2:5 corrodes 40 Sec to silicon single crystal flake, removes the damage layer on silicon single crystal flake surface, uses deionized water rinsing 10 times; B, RCA clean, and use deionized water rinsing 15 times; C, drying; D, high concentration phosphorus give deposition, under 1200 ℃, pass into and carry POCL
3nitrogen and oxygen, spread 4.2 h, form N
+sedimentary deposit, require R
□=0.30 Ω/; E, knot, under 1275 ℃, nitrogen and oxygen atmosphere, diffusion 168h, form the dark N of 175um
+substrate layer.
The step of front polishing attenuate: with wafer lapping machine, the front of silicon chip is ground, remove positive N
+substrate layer, after attenuate, silicon wafer thickness is 290um;
Front side of silicon wafer is carried out to the step of chemical corrosion or chemico-mechanical polishing: the front side of silicon wafer by the method for chemical corrosion or chemico-mechanical polishing after to attenuate carries out polishing, and the silicon wafer thickness after polishing is 270um;
Positive P type base spread and grows oxide layer step: a, silicon chip is carried out to the RCA cleaning, use deionized water rinsing 15 times; B, drying; C, front side of silicon wafer are coated with the boron source; D, boron give deposition, and under 950 ℃, nitrogen and oxygen atmosphere, diffusion 1h, form P type sedimentary deposit, requires R
□=30 Ω/; E, knot, under 1235 ℃, nitrogen and oxygen atmosphere, diffusion 14h, form the dark p type diffused layer of 25um;
The positive emitter window step of photoetching: utilize sol evenning machine that photoresist is coated in to front side of silicon wafer, through the front baking of 100 ℃/25min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, remove cull, clean, dry;
N
+emitter region phosphorus spread and grow oxide layer step: a, silicon chip is carried out to the RCA cleaning, with deionized water rinsing 15 times; B, drying; C, phosphorus give deposition, under 930 ℃, pass into and carry POCL
3nitrogen and oxygen, diffusion 1.2h, form N
+sedimentary deposit, require R
□=4.5 Ω/; D, knot, under 1180 ℃, nitrogen and oxygen atmosphere, diffusion 3h, form emitter region, controls h
fEmeet the requirements;
Photoengraving groove step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 100 ℃/25min, utilize mask aligner, mask plate to carry out double-sided exposure, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, cleans, dry, utilize HF:HN0
3 : CH
3 cOOH=4:1:1 erodes away the groove of front and back simultaneously, removes cull, cleans, and dries;
Filling glass carry out sintering step in groove: prepare glass and stick with paste, glass is stuck with paste and scraped silicon chip surface, wipe the outer glass of groove and stick with paste, according to the temperature curve shown in Fig. 8, carry out sintering;
Subsequent processing steps: a, growth LTO passivating film are for the protection of glass-film; B, at the fairlead of positive photoetching base and emitter region; C, at positive AM aluminum metallization film; D, anti-carve positive aluminium electrode; E, alloy; F, removal back side oxide layer; G, back side evaporation metal electrode; H, chip testing and sorting; I, scribing, carry out the chip separation; J, check; K, packing.
As shown in Fig. 5, Fig. 6, Fig. 8, chip structure for power transistor produced with mesa process, comprise N
+emitter region 1, emitter aluminium electrode 2, base stage aluminium electrode 3, SiO
2diaphragm 4, glassivation film 5, N
+substrate diffusion layer 6, P type base diffusion layer 7 and silicon single crystal flake 8, silicon single crystal flake 8 fronts are provided with P type base diffusion layer 7, and silicon single crystal flake 8 back sides are provided with N
+substrate diffusion layer 6, be provided with N in P type base diffusion layer 7
+emitter region 1, P type base diffusion layer 7 and N
+the surface of emitter region 1 is provided with SiO
2diaphragm 4, base stage aluminium electrode 3 and emitter aluminium electrode 2, silicon single crystal flake 8 and P type base diffusion layer 7 are provided with front groove 9, and front groove 9 bottoms and sidewall are provided with glassivation film 5, N
+substrate diffusion layer 6 back peripheries are provided with back side stress equilibrium groove 11, and back side stress equilibrium groove 11 degree of depth are 110um, and back side stress equilibrium groove 11 width are 240um, and stress equilibrium groove 11 tops, the back side and sidewall are provided with glass-film 12, N
+substrate diffusion layer 6 and glass-film 12 surfaces are provided with multilayer metallic electrode 10.
As shown in Fig. 6, Fig. 7 and Fig. 8, mesa technique power transistor chip implementation method comprises:
N
+substrate diffusing step: a, use HF:H
3pO
4: HNO
3=1:2:5 corrodes 45 Sec to silicon single crystal flake, removes the damage layer on silicon single crystal flake surface, uses deionized water rinsing 10 times; B, RCA clean, and use deionized water rinsing 15 times; C, drying; D, high concentration phosphorus give deposition, under 1205 ℃, pass into and carry POCL
3nitrogen and oxygen, diffusion 4.5h, form N
+sedimentary deposit, require R
□=0.33 Ω/; E, knot, under 1280 ℃, nitrogen and oxygen atmosphere, diffusion 180h, form the dark N of 180um
+substrate layer.
The step of front polishing attenuate: with wafer lapping machine, the front of silicon chip is ground, remove positive N
+substrate layer, after attenuate, silicon wafer thickness is 295um;
Front side of silicon wafer is carried out to the step of chemical corrosion or chemico-mechanical polishing: the front side of silicon wafer by the method for chemical corrosion or chemico-mechanical polishing after to attenuate carries out polishing, and the silicon wafer thickness after polishing is 275um;
Positive P type base spread and grows oxide layer step: a, silicon chip is carried out to the RCA cleaning, use deionized water rinsing 15 times; B, drying; C, front side of silicon wafer are coated with the boron source; D, boron give deposition, under 955 ℃, nitrogen and oxygen atmosphere, spread 1.1 h, form P type sedimentary deposit, require R
□=31 Ω/; E, knot, under 1240 ℃, nitrogen and oxygen atmosphere, spread 16 h, forms the dark p type diffused layer of 28um;
The positive emitter window step of photoetching: utilize sol evenning machine that photoresist is coated in to front side of silicon wafer, through the front baking of 105 ℃/30min, utilize mask aligner, mask plate to be exposed, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, remove cull, clean, dry;
N
+emitter region phosphorus spread and grow oxide layer step: a, silicon chip is carried out to the RCA cleaning, with deionized water rinsing 15 times; B, drying; C, phosphorus give deposition, under 940 ℃, pass into and carry POCL
3nitrogen and oxygen, diffusion 1.4h, form N
+sedimentary deposit, require R
□=5 Ω/; D, knot, under 1190 ℃, nitrogen and oxygen atmosphere, spread 3. 5 h, forms emitter region, controls h
fEmeet the requirements;
Photoengraving groove step: utilize sol evenning machine photoresist to be coated in to the positive and negative two sides of silicon chip, front baking through 105 ℃/30min, utilize mask aligner, mask plate to carry out double-sided exposure, develop, post bake, utilize the buffered hydrofluoride acid corrosion to remove the silicon dioxide film of window, cleans, dry, utilize HF:HN0
3 : CH
3 cOOH=4:1:1 erodes away the groove of front and back simultaneously, removes cull, cleans, and dries;
Filling glass carry out sintering step in groove: prepare glass and stick with paste, glass is stuck with paste and scraped silicon chip surface, wipe the outer glass of groove and stick with paste, according to the temperature curve shown in Fig. 8, carry out sintering;
Subsequent processing steps: a, growth LTO passivating film are for the protection of glass-film; B, at the fairlead of positive photoetching base and emitter region; C, at positive AM aluminum metallization film; D, anti-carve positive aluminium electrode; E, alloy; F, removal back side oxide layer; G, back side evaporation metal electrode; H, chip testing and sorting; I, scribing, carry out the chip separation; J, check; K, packing.
Claims (3)
1. chip structure for power transistor produced with mesa process, comprise N
+emitter region, emitter aluminium electrode, base stage aluminium electrode, SiO
2diaphragm, glassivation film, N
+substrate diffusion layer, P type base diffusion layer and silicon single crystal flake, described silicon single crystal flake front is provided with P type base diffusion layer, and the described silicon single crystal flake back side is provided with N
+the substrate diffusion layer, described P type is provided with N in base
+emitter region, diffusion layer surface, described P type base and N
+the surface, emitter region is provided with SiO
2diaphragm, base stage aluminium electrode and emitter aluminium electrode, described silicon single crystal flake and P type base diffusion layer are provided with the front groove, and described front channel bottom and sidewall are provided with the glassivation film, it is characterized in that: described N
+substrate diffusion layer back periphery is provided with back side stress equilibrium groove, and stress equilibrium groove top, the described back side and sidewall are provided with glass-film, described N
+substrate diffusion layer surface and glass-film surface are provided with multilayer metallic electrode.
2. chip structure for power transistor produced with mesa process according to claim 1, it is characterized in that: described back side stress equilibrium groove depth is 50-110um, described back side stress equilibrium well width is 100-240um.
3. mesa technique power transistor chip implementation method, comprise N
+the step of substrate diffusing step, front polishing attenuate, front side of silicon wafer is carried out to the step of chemical corrosion or chemico-mechanical polishing, positive P type base spread and grow oxide layer step, the positive emitter window step of photoetching, N
+emitter region phosphorus spread and grow oxide layer step, photoengraving groove step, in groove filling glass carry out sintering step and subsequent processing steps, described N
+the substrate diffusing step is N
+the substrate diffusion, form the high concentration substrate layer, the step of described front polishing attenuate is for removing the N of front side of silicon wafer by the method for mechanical lapping
+substrate layer, the corrosion window that described photoengraving groove step is the photoetching front, and go out the ring-shaped groove of certain depth at front etch, described in groove filling glass carry out sintering step for filling glass carry out sintering in groove, the glass-film after burning till is as the terminal passivating film of P-N knot, described subsequent processing steps is growth LTO passivating film, glass-film is protected, fairlead in positive photoetching base and emitter region, at positive AM aluminum metallization film, anti-carve positive aluminium electrode, alloy, remove back side oxide layer, back side evaporation metal electrode, chip testing and sorting, scribing, carry out the chip separation, check, packing, it is characterized in that: described photoengraving groove step be photoetching just, the corrosion window at the back side, and just, the back side erodes away groove simultaneously, gash depth is 50-110um, groove width is 100-240um, front channel bottom and sidewall are provided with the glassivation film, stress equilibrium groove top, the back side and sidewall are provided with glass-film, filling glass carry out sintering in the groove of front and back, burn till the passivating film of the glass-film of rear front groove as the P-N knot, the glass-film that burns till rear backside trench as the convergent force in balance front for flattening silicon chip, 3-6h anneals under glass transition point-(10～20) ℃, realize reducing the glass swelling coefficient.
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| CN1199930A (en) * | 1997-05-19 | 1998-11-25 | 松下电子工业株式会社 | Semiconductor device and its producing method |
| CN201402808Y (en) * | 2009-05-07 | 2010-02-10 | 无锡固电半导体股份有限公司 | Single-resistance Darlington pipe used in excitation device of generator |
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| CN201402808Y (en) * | 2009-05-07 | 2010-02-10 | 无锡固电半导体股份有限公司 | Single-resistance Darlington pipe used in excitation device of generator |
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