CN107180858A - The controllable silicon and its manufacture method of a kind of use heterojunction structure - Google Patents
The controllable silicon and its manufacture method of a kind of use heterojunction structure Download PDFInfo
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- CN107180858A CN107180858A CN201710365079.1A CN201710365079A CN107180858A CN 107180858 A CN107180858 A CN 107180858A CN 201710365079 A CN201710365079 A CN 201710365079A CN 107180858 A CN107180858 A CN 107180858A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 86
- 239000010703 silicon Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 85
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052796 boron Inorganic materials 0.000 claims abstract description 42
- 238000001259 photo etching Methods 0.000 claims abstract description 39
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 24
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- 239000004411 aluminium Substances 0.000 claims abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 6
- 230000008020 evaporation Effects 0.000 claims abstract description 6
- 238000001704 evaporation Methods 0.000 claims abstract description 6
- 238000001459 lithography Methods 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 238000003763 carbonization Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 15
- 238000001465 metallisation Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 5
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000003892 spreading Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 10
- 230000007423 decrease Effects 0.000 abstract 1
- 238000000407 epitaxy Methods 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 1
- 239000010931 gold Substances 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 8
- 238000003199 nucleic acid amplification method Methods 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000001727 in vivo Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012886 linear function Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003380 propellant Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- Microelectronics & Electronic Packaging (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
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- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a kind of controllable silicon of use heterojunction structure, including p-type reach through region, N-type growing base area, P+ anode regions, the short base of p-type；Groove is provided between the short base of p-type and p-type reach through region；P-type reach through region, N+ cathodic regions, p-type are covered with silicon nitride passivation on the upside of short base；P-type is additionally provided with gate pole on the upside of short base；The manufacture craft of the present invention includes：Silicon chip twin polishing, oxidation, reach through region photoetching, break-through diffusion, the diffusion of short base, concentrated boron area photoetching, concentrated boron area diffusion, cathodic region photoetching, growth silicon carbide epitaxy, carbonization silicon etching, trench lithography, trench etching, silicon nitride passivation, glassivation, fairlead photoetching, evaporation of aluminum, aluminium are anti-carved, aluminium alloy, back of the body gold.Present invention decreases the trigger current of controllable silicon under normal temperature, it is to avoid the generation of launch site heavy doping effect, improves the stability that controllable silicon works at high temperature.
Description
Technical field
The invention belongs to the controllable silicon and its system in semi-conductor discrete device field, more particularly to a kind of use heterojunction structure
Make method.
Background technology
Controllable silicon is a kind of common three terminal device, and device can be triggered into conducting by applying suitable grid current
State.Trigger current is provided by gate bias circuit, and trigger current is excessive to mean that gate bias circuit power consumption is big, triggers circuit
Complexity, in order to reduce the power consumption of gate bias circuit, reduction trigger current is necessary in certain scope.In order to reduce
A kind of method commonly used under normal temperature in the trigger current of controllable silicon, technique is to improve N+The doping concentration in cathodic region, reduces p-type short
The doping concentration of base, reduces the effective base width of NPN triode so that the amplification coefficient of NPN triode becomes in controllable silicon body
Greatly, so as to play a part of reducing trigger current.But to N+Cathodic region carries out being heavily doped with may result in launch site heavily doped
Miscellaneous effect, N+The energy gap in cathodic region (launch site of NPN triode) narrows, and causes few electron current in NPN pipes launch site to increase
Greatly so that NPN triode amplification coefficient reduces, the trigger current of controllable silicon can increase on the contrary；And reduce the effective base of NPN triode
Sector width normally results in the reduction of controllable silicon breakdown voltage.
On the other hand, when the controllable silicon of smaller trigger current is worked under the high temperature conditions, the amplification coefficient of internal triode
It can raise and increase with temperature, silicon controlled trigger current reduces, and false triggering probability is greatly increased, and this influences whether device and circuit
Normal work, when serious even controllable silicon is constantly in conducting state, lose the effect of switch.Therefore, controllable silicon is in height
Become can not be ignored the problem of stability when working under the conditions of temperature.
The content of the invention
It is an object of the invention to overcome prior art exist problem above there is provided a kind of use heterojunction structure can
Control silicon and its manufacture method, it is therefore an objective to reduce the trigger current of controllable silicon under normal temperature, it is to avoid the generation of launch site heavy doping effect,
Improve the stability that controllable silicon works at high temperature.
To realize above-mentioned technical purpose and the technique effect, the present invention is achieved through the following technical solutions：
A kind of controllable silicon of use heterojunction structure, including p-type reach through region, N-type growing base area, P+ anode regions, the short base of p-type
Area, p-type reach through region, which is located on the upside of N-type growing base area both sides, N-type growing base area, is provided with the short base of p-type, and P+ is provided with the downside of N-type growing base area
It is connected on the downside of anode region, P+ anode regions with anode；
It is provided with the upside of N+ cathodic regions, N+ cathodic regions and is connected with negative electrode on the upside of the short base of p-type；
Groove is provided between the short base of p-type and p-type reach through region；
The p-type reach through region, N+ cathodic regions, p-type are covered with silicon nitride passivation on the upside of short base；
Gate pole is additionally provided with the upside of the short base of p-type.
Further, the p-type reach through region, N-type growing base area, P+ anode regions, the material of the short base of p-type are silicon, and N+ is cloudy
The material of polar region is carborundum.
Further, the material in the N+ cathodic regions is semiconductor material with wide forbidden band, and the semiconductor material with wide forbidden band is used
Gallium nitride or GaAs.
The present invention also provides a kind of controllable silicon manufacture method of use heterojunction structure, the described method comprises the following steps：
Backing material preparation, oxidation, reach through region photoetching, break-through diffusion, the diffusion of short base, concentrated boron area photoetching, concentrated boron area diffusion, cathodic region
Photoetching, n-type doping silicon carbide epitaxial growth, carbonization silicon etching, trench lithography, trench etching, silicon nitride passivation, glassivation,
Fairlead photoetching, evaporation of aluminum, aluminium are anti-carved, aluminium alloy, back face metalization.
Further, N-type semiconductor silicon chip, selected N-type semiconductor silicon chip electricity are selected in the backing material preparation process
Resistance rate is 30~300 Ω cm, and silicon wafer thickness is 230~300 μm, and carries out twin polishing.
Further, the condition of the oxidation step is that oxidizing temperature is 1000 DEG C~1100 DEG C, and the time is 4h~8h, oxygen
The thickness for changing layer is 1.4 μm~2 μm.
Further, the step of break-through is spread be：First to reach through region carry out boron pre-deposition, temperature be 1050 DEG C~
1100 DEG C, the time is 2h~4h, and square resistance is 3~5 Ω/；Then reach through region is spread again, temperature be 1200 DEG C~
1270 DEG C, the time is 120h~180h.
Further, the step of short base spreads be：Light boron pre-deposition is carried out to short base first, temperature is 850
DEG C~950 DEG C, the time is 0.5h~1h, and square resistance is 30~50 Ω/；Then carry out boron to short base to spread again, temperature
For 1200 DEG C~1250 DEG C, the time is 25h~30h, and square resistance is 60~100 Ω/, and junction depth is 35 μm~40 μm.
Further, the step of concentrated boron area is spread be：Dense boron pre-deposition is carried out first, and temperature is 1000 DEG C~1050
DEG C, the time is 1h~2h, and square resistance is 5~8 Ω/；Then carry out dense boron to spread again, temperature is 1200 DEG C~1250 DEG C,
Time is 5h~8h.
Further, the condition of the n-type doping silicon carbide epitaxial growth step is that temperature is 1500 DEG C~1700 DEG C, when
Between be 1h~2h；The condition of trench etching step is that groove depth is 50~70 μm.
The beneficial effects of the invention are as follows：
The present invention is compared with conventional SCR structure, by the short base of p-type and N in structure of the invention+Cathodic region is formed
PN junction exist only in vivo, device surface does not have a PN junction, and the front of this structure covers silicon nitride as passivation layer, this
A little features can greatly reduce adverse effect of the surface state to device, the leakage current of device is maintained a very low magnitude,
Reduce the trigger current of controllable silicon under normal temperature, it is to avoid the generation of launch site heavy doping effect, improve controllable silicon work at high temperature
The stability of work.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this hair
Bright schematic description and description is used to explain the present invention, does not constitute inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the structural representation of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is all other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
A kind of controllable silicon of use heterojunction structure as shown in Figure 1, including p-type reach through region 1, N-type growing base area 2, P+ sun
The short base 8 of polar region 3, p-type, p-type reach through region 1 is located at the both sides of N-type growing base area 2, and the upside of N-type growing base area 2 is provided with the short base 8, N of p-type
The downside of type growing base area 2 is provided with P+ anode regions 3, and the downside of P+ anode regions 3 is connected with anode 4, p-type reach through region 1, N-type growing base area 2, P+
Anode region 3, the material of the short base 8 of p-type are silicon, and the material in N+ cathodic regions 7 is carborundum or semiconductor material with wide forbidden band, the width
Bandgap semiconductor material can use gallium nitride or GaAs；
The short upside of base 8 of p-type is provided with N+ cathodic regions 7, and the upside of N+ cathodic regions 7 is connected with negative electrode 6, N+Cathodic region is short with p-type
Base constitutes the heterogeneous propellant knot of NPN triode；
Groove 10 is provided between the short base 8 of p-type and p-type reach through region 1；
P-type reach through region 1, N+ cathodic regions 7, the short upside of base 8 of p-type are covered with silicon nitride passivation 5；
The short upside of base 8 of p-type is additionally provided with gate pole 9.
The present invention technical principle be：
The energy gap of intrinsic silicon is 1.1eV at room temperature, and the energy gap of intrinsic carborundum is 2.9eV at room temperature, several
It is 3 times of intrinsic silicon energy gap.This also means that being used as N with carborundum+The material in cathodic region (NPN triode launch site)
Can significantly it reduce from the short base injection N of p-type+Few electron current in cathodic region, increases emitter junction injection efficiency, so as to increase
The amplification coefficient of NPN triode so that trigger current reduces.Because NPN triode can be significantly increased using heterojunction structure
Amplification coefficient, controllable silicon can also be made to meet unlocking condition without heavy doping even if launch site：
αNPN+αPNP≥1
(αNPNAnd αPNPThe current gain of NPN triode and PNP triode in controllable silicon body is represented respectively)
So the doping concentration of carborundum can be relatively lower, so it is possible to prevente effectively from launch site heavy doping effect
Occur.Because the amplification coefficient of triode has positive temperature characteristics, trigger current can reduce when controllable silicon works at high temperature, three poles
The amplification coefficient of pipe and the relation of temperature meet formula (1)：
(1)
C is the constant unrelated with T, ρ in formulaohIt is the square resistance of the short base of p-type, actual measurement shows ρohIt is approximately T's
Linear function, Δ EgeWith Δ EgbRespectively N+Cathodic region and the bandgap narrowing of the short base of p-type, φ are carborundum and silicon single crystal circle
The surface potential in face.Make functionSubstitution formula (1) is obtained：
(2)
Formula (2) both members ask local derviation to obtain T simultaneously：
Formula (3) shows hFETemperature characterisitic it is main by (Δ Ege-ΔEgb- q φ) item determines, to improve the temperature of controllable silicon
Degree stability needs to reduce the bandgap narrowing in cathodic region, and energy gap Eg is the function of temperature and doping concentration, specifically
Relational expression is as follows：
(4)
Section 1 represents the energy gap of intrinsic material at room temperature on the right of formula (4) equation, and Section 2 reflects temperature to forbidden band
N in the influence of width, Section 3DRepresent doping concentration, N0For occur degeneracy when doping concentration, for specific material Z, k,
N0, λ be all constant, ND/N0Value determine influence of the doping concentration to energy gap, it is clear that doping concentration NDIt is smaller, ND/N0Just
Smaller, the value of Section 3 is also just smaller, it means that influence of the doping concentration to energy gap is also just smaller, in other words, forbidden band
The amount of narrowing of width is influenceed also just smaller by doping concentration.Due to the N of this structure+Cathodic region doping concentration is small, (Δ Ege-Δ
Egb) more much smaller than the NPN triode in conventional controllable silicon body, sufficiently small (the Δ E of valuege-ΔEgb- q φ) also bring foot
It is enough smallIn summary, in this structure-controllable silicon body NPN triode amplification coefficient hFEIt is the minorant of temperature, by temperature
Degree influence is smaller, therefore influence of the hot environment to trigger current is corresponding also small, and the stability that controllable silicon works at high temperature is obtained
To significantly improving.
Embodiment 1：
A kind of controllable silicon manufacture method of use heterojunction structure, the manufacture method comprises the following steps：
S1：Backing material prepares：N-type semiconductor silicon chip is got out, selected N-type semiconductor silicon chip resistivity is 200 Ω
Cm, silicon wafer thickness is 270 μm, and carries out twin polishing；
S2：Oxidation：Silicon chip is aoxidized, oxidizing temperature is controlled at 1050 DEG C, and the time is 6h, and the thickness of oxide layer is
1.7μm；
S3：Reach through region photoetching：Using break-through reticle, by silicon chip double-sided alignment photoetching；
S4：Break-through is spread：Boron pre-deposition is carried out to reach through region first, temperature is 1070 DEG C, and the time is 3h, and square resistance is
4Ω/□；Then reach through region is spread again, temperature is 1235 DEG C, and the time is 150h；
S5：Short base diffusion：Light boron pre-deposition is carried out to short base first, temperature is 900 DEG C, and the time is 0.7h, square
Resistance is 40 Ω/；Then carry out boron to short base to spread again, temperature is 1225 DEG C, the time is 27h, square resistance be 80 Ω/
, junction depth is 37 μm；
S6：Concentrated boron area photoetching：Photoetching is carried out to concentrated boron area；
S7：Spread concentrated boron area：Dense boron pre-deposition is carried out first, and temperature is 1030 DEG C, and the time is 1.5h, and square resistance is 6
Ω/□；Then carry out dense boron to spread again, temperature is 1230 DEG C, and the time is 6h；
S8：Cathodic region photoetching：Photoetching is carried out to cathodic region using cathodic region reticle；
S9：N-type doping silicon carbide epitaxial growth：Temperature is 1600 DEG C, and the time is 1.5h；
S10：Be carbonized silicon etching：Version is anti-carved using carborundum to perform etching carborundum；
S11：Trench lithography：Photoetching is carried out to groove using groove version；
S12：Trench etching：Groove is corroded, groove depth is 60 μm；
S13：Silicon nitride passivation：Silicon nitride passivation is carried out on the upside of short base to p-type reach through region, N+ cathodic regions, p-type；
S14：Glassivation：To being sintered after gate pole, negative electrode and groove coating glass dust, glass passivation layer is formed；
S15：Fairlead photoetching：Fairlead photoetching is carried out using fairlead version；
S16：Evaporation of aluminum：Aluminum layer thickness is 4.5 μm；
S17：Aluminium is anti-carved：Version progress aluminium is anti-carved using aluminium to anti-carve；
S18：Aluminium alloy：Silicon chip after being anti-carved to aluminium carries out alloy operation；
S19：Back face metalization：Ti-Ni-Ag layers are evaporated to silicon chip back side.
Embodiment 2：
A kind of controllable silicon manufacture method of use heterojunction structure, the manufacture method comprises the following steps：
S1：Backing material prepares：N-type semiconductor silicon chip is got out, selected N-type semiconductor silicon chip resistivity is 300 Ω
Cm, silicon wafer thickness is 300 μm, and carries out twin polishing；
S2：Oxidation：Silicon chip is aoxidized, oxidizing temperature control is at 1100 DEG C, and the time is 8h, and the thickness of oxide layer is 2 μ
m；
S3：Reach through region photoetching：Using break-through reticle, by silicon chip double-sided alignment photoetching；
S4：Break-through is spread：Boron pre-deposition is carried out to reach through region first, temperature is 1100 DEG C, and the time is 4h, and square resistance is
5Ω/□；Then reach through region is spread again, temperature is 1270 DEG C, and the time is 180h；
S5：Short base diffusion：Light boron pre-deposition is carried out to short base first, temperature is 950 DEG C, the time is 1h, square electricity
Hinder for 50 Ω/；Then carry out boron to short base to spread again, temperature is 1250 DEG C, the time is 30h, square resistance be 100 Ω/
, junction depth is 40 μm；
S6：Concentrated boron area photoetching：Photoetching is carried out to concentrated boron area；
S7：Spread concentrated boron area：Carry out dense boron pre-deposition first, temperature is 1050 DEG C, the time is 2h, square resistance be 8 Ω/
□；Then carry out dense boron to spread again, temperature is 1250 DEG C, and the time is 8h；
S8：Cathodic region photoetching：Photoetching is carried out to cathodic region using cathodic region reticle；
S9：N-type doping silicon carbide epitaxial growth：Temperature is 1700 DEG C, and the time is 2h；
S10：Be carbonized silicon etching：Version is anti-carved using carborundum to perform etching carborundum；
S11：Trench lithography：Photoetching is carried out to groove using groove version；
S12：Trench etching：Groove is corroded, groove depth is 70 μm；
S13：Silicon nitride passivation：Silicon nitride passivation is carried out on the upside of short base to p-type reach through region, N+ cathodic regions, p-type；
S14：Glassivation：To being sintered after gate pole, negative electrode and groove coating glass dust, glass passivation layer is formed；
S15：Fairlead photoetching：Fairlead photoetching is carried out using fairlead version；
S16：Evaporation of aluminum：Aluminum layer thickness is 5.0 μm；
S17：Aluminium is anti-carved：Version progress aluminium is anti-carved using aluminium to anti-carve；
S18：Aluminium alloy：Silicon chip after being anti-carved to aluminium carries out alloy operation；
S19：Back face metalization：Ti-Ni-Ag layers are evaporated to silicon chip back side.
Embodiment 3：
A kind of controllable silicon manufacture method of use heterojunction structure, the manufacture method comprises the following steps：
S1：Backing material prepares：N-type semiconductor silicon chip is got out, selected N-type semiconductor silicon chip resistivity is 30 Ω
Cm, silicon wafer thickness is 230 μm, and carries out twin polishing；
S2：Oxidation：Silicon chip is aoxidized, oxidizing temperature is controlled at 1000 DEG C, and the time is 4h, and the thickness of oxide layer is
1.4μm；
S3：Reach through region photoetching：Using break-through reticle, by silicon chip double-sided alignment photoetching；
S4：Break-through is spread：Boron pre-deposition is carried out to reach through region first, temperature is 1050 DEG C, and the time is 2h, and square resistance is
3Ω/□；Then reach through region is spread again, temperature is 1200 DEG C, and the time is 120h；
S5：Short base diffusion：Light boron pre-deposition is carried out to short base first, temperature is 850 DEG C, and the time is 0.5h, square
Resistance is 30 Ω/；Then carry out boron to short base to spread again, temperature is 1200 DEG C, the time is 25h, square resistance be 60 Ω/
, junction depth is 35 μm；
S6：Concentrated boron area photoetching：Photoetching is carried out to concentrated boron area；
S7：Spread concentrated boron area：Carry out dense boron pre-deposition first, temperature is 1000 DEG C, the time is 1h, square resistance be 5 Ω/
□；Then carry out dense boron to spread again, temperature is 1200 DEG C, and the time is 5h；
S8：Cathodic region photoetching：Photoetching is carried out to cathodic region using cathodic region reticle；
S9：N-type doping silicon carbide epitaxial growth：Temperature is 1500 DEG C, and the time is 1h；
S10：Be carbonized silicon etching：Version is anti-carved using carborundum to perform etching carborundum；
S11：Trench lithography：Photoetching is carried out to groove using groove version；
S12：Trench etching：Groove is corroded, groove depth is 50 μm；
S13：Silicon nitride passivation：Silicon nitride passivation is carried out on the upside of short base to p-type reach through region, N+ cathodic regions, p-type；
S14：Glassivation：To being sintered after gate pole, negative electrode and groove coating glass dust, glass passivation layer is formed；
S15：Fairlead photoetching：Fairlead photoetching is carried out using fairlead version；
S16：Evaporation of aluminum：Aluminum layer thickness is 4.0 μm；
S17：Aluminium is anti-carved：Version progress aluminium is anti-carved using aluminium to anti-carve；
S18：Aluminium alloy：Silicon chip after being anti-carved to aluminium carries out alloy operation；
S19：Back face metalization：Ti-Ni-Ag layers are evaporated to silicon chip back side.
The present invention is compared with conventional SCR structure, by the short base of p-type and N in structure of the invention+Cathodic region is formed
PN junction exist only in vivo, device surface does not have a PN junction, and the front of this structure covers silicon nitride as passivation layer, this
A little features can greatly reduce adverse effect of the surface state to device, the leakage current of device is maintained a very low magnitude,
Reduce the trigger current of controllable silicon under normal temperature, it is to avoid the generation of launch site heavy doping effect, improve controllable silicon work at high temperature
The stability of work.
General principle, principal character and the advantages of the present invention of the present invention has been shown and described above.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and the simply explanation described in above-described embodiment and specification is originally
The principle of invention, without departing from the spirit and scope of the present invention, various changes and modifications of the present invention are possible, these changes
Change and improvement all fall within the protetion scope of the claimed invention.
Claims (10)
1. a kind of controllable silicon of use heterojunction structure, it is characterised in that：Including p-type reach through region (1), N-type growing base area (2), P+
Anode region (3), the short base of p-type (8), p-type reach through region (1), which is located on the upside of N-type growing base area (2) both sides, N-type growing base area (2), is provided with P
P+ anode regions (3) are provided with the downside of the short base of type (8), N-type growing base area (2), are connected on the downside of P+ anode regions (3) with anode (4)；
N+ cathodic regions (7) are provided with the upside of the short base of p-type (8), are connected on the upside of N+ cathodic regions (7) with negative electrode (6)；
Groove (10) is provided between the short base of p-type (8) and p-type reach through region (1)；
The p-type reach through region (1), N+ cathodic regions (7), the short base of p-type (8) upside are covered with silicon nitride passivation (5)；
Gate pole (9) is additionally provided with the upside of the short base of p-type (8).
2. a kind of controllable silicon of use heterojunction structure according to claim 1, it is characterised in that：The p-type reach through region
(1), N-type growing base area (2), P+ anode regions (3), the material of the short base of p-type (8) are silicon, and the material of N+ cathodic regions (7) is carbonization
Silicon.
3. a kind of controllable silicon of use heterojunction structure according to claim 1, it is characterised in that：The N+ cathodic regions
(7) material is semiconductor material with wide forbidden band, and the semiconductor material with wide forbidden band uses gallium nitride or GaAs.
4. a kind of controllable silicon manufacture method of use heterojunction structure according to claim 1, it is characterised in that：The side
Method comprises the following steps：It is backing material preparation, oxidation, reach through region photoetching, break-through diffusion, the diffusion of short base, concentrated boron area photoetching, dense
The diffusion of boron area, cathodic region photoetching, n-type doping silicon carbide epitaxial growth, carbonization silicon etching, trench lithography, trench etching, silicon nitride
Passivation, glassivation, fairlead photoetching, evaporation of aluminum, aluminium are anti-carved, aluminium alloy, back face metalization.
5. a kind of controllable silicon manufacture method of use heterojunction structure according to claim 4, it is characterised in that：The lining
N-type semiconductor silicon chip is selected in bottom material preparation process, selected N-type semiconductor silicon chip resistivity is 30~300 Ω cm, silicon chip
Thickness is 230~300 μm, and carries out twin polishing.
6. a kind of controllable silicon manufacture method of use heterojunction structure according to claim 4, it is characterised in that：The oxygen
The condition for changing step is that oxidizing temperature is 1000 DEG C~1100 DEG C, and the time is 4h~8h, and the thickness of oxide layer is 1.4 μm~2 μm.
7. a kind of controllable silicon manufacture method of use heterojunction structure according to claim 4, it is characterised in that：It is described to wear
Leading to the step of spreading is：Boron pre-deposition is carried out to reach through region first, temperature is 1050 DEG C~1100 DEG C, the time is 2h~4h, side
Block resistance is 3~5 Ω/；Then reach through region is spread again, temperature be 1200 DEG C~1270 DEG C, the time be 120h~
180h。
8. a kind of controllable silicon manufacture method of use heterojunction structure according to claim 4, it is characterised in that：It is described short
The step of base spreads be：Light boron pre-deposition is carried out to short base first, temperature is 850 DEG C~950 DEG C, the time be 0.5h~
1h, square resistance is 30~50 Ω/；Then carry out boron to short base to spread again, temperature is 1200 DEG C~1250 DEG C, and the time is
25h~30h, square resistance is 60~100 Ω/, and junction depth is 35 μm~40 μm.
9. a kind of controllable silicon manufacture method of use heterojunction structure according to claim 4, it is characterised in that：It is described dense
The step of boron area spreads be：Dense boron pre-deposition is carried out first, temperature is 1000 DEG C~1050 DEG C, the time is 1h~2h, square electricity
Hinder for 5~8 Ω/；Then carry out dense boron to spread again, temperature is 1200 DEG C~1250 DEG C, the time is 5h~8h.
10. a kind of controllable silicon manufacture method of use heterojunction structure according to claim 4, it is characterised in that：The N
The condition of type doped silicon carbide epitaxial growth steps is that temperature is 1500 DEG C~1700 DEG C, and the time is 1h~2h；Trench etching is walked
Rapid condition is that groove depth is 50~70 μm.
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| CN107634096A (en) * | 2017-09-27 | 2018-01-26 | 安徽富芯微电子有限公司 | A kind of controllable silicon and its manufacture method with channel cutoff ring |
| CN107658296A (en) * | 2017-10-25 | 2018-02-02 | 启东吉莱电子有限公司 | A kind of thyristor surge suppressor that there are three tunnels to protect and its manufacture method |
| CN108133953A (en) * | 2017-09-27 | 2018-06-08 | 中航（重庆）微电子有限公司 | A kind of silicon-controlled device and preparation method thereof |
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| CN107634096A (en) * | 2017-09-27 | 2018-01-26 | 安徽富芯微电子有限公司 | A kind of controllable silicon and its manufacture method with channel cutoff ring |
| CN108133953A (en) * | 2017-09-27 | 2018-06-08 | 中航（重庆）微电子有限公司 | A kind of silicon-controlled device and preparation method thereof |
| CN108133953B (en) * | 2017-09-27 | 2021-01-01 | 华润微电子（重庆）有限公司 | Silicon controlled rectifier device and preparation method thereof |
| CN107658296A (en) * | 2017-10-25 | 2018-02-02 | 启东吉莱电子有限公司 | A kind of thyristor surge suppressor that there are three tunnels to protect and its manufacture method |
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| CN110098254A (en) * | 2019-04-30 | 2019-08-06 | 江苏捷捷微电子股份有限公司 | Utilize the single table surface high-voltage thyristor chip and manufacturing method of the two-way scribing of symmetry |
| CN113410296A (en) * | 2021-06-17 | 2021-09-17 | 吉林华微电子股份有限公司 | Silicon controlled rectifier structure |
| CN113410296B (en) * | 2021-06-17 | 2024-03-22 | 吉林华微电子股份有限公司 | Silicon controlled rectifier structure |
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