CN109103242A - A kind of controlled silicon chip and its production method of punch-through - Google Patents
A kind of controlled silicon chip and its production method of punch-through Download PDFInfo
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- CN109103242A CN109103242A CN201811155899.9A CN201811155899A CN109103242A CN 109103242 A CN109103242 A CN 109103242A CN 201811155899 A CN201811155899 A CN 201811155899A CN 109103242 A CN109103242 A CN 109103242A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 67
- 239000010703 silicon Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 58
- 238000002955 isolation Methods 0.000 claims abstract description 57
- 238000001259 photo etching Methods 0.000 claims abstract description 20
- 230000009977 dual effect Effects 0.000 claims abstract description 19
- 238000001459 lithography Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052796 boron Inorganic materials 0.000 claims abstract description 16
- 238000004140 cleaning Methods 0.000 claims abstract description 15
- 230000003628 erosive effect Effects 0.000 claims abstract description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 6
- 239000011574 phosphorus Substances 0.000 claims abstract description 6
- 239000000243 solution Substances 0.000 claims description 15
- 229910052782 aluminium Inorganic materials 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- 239000000203 mixture Substances 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000004411 aluminium Substances 0.000 claims description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- 238000011161 development Methods 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 5
- 239000002253 acid Substances 0.000 claims description 4
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 238000003892 spreading Methods 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- 238000012545 processing Methods 0.000 claims description 2
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910017604 nitric acid Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 7
- 238000013461 design Methods 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000011521 glass Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010792 warming Methods 0.000 description 4
- 239000012634 fragment Substances 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 2
- 238000011068 loading method Methods 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- FGUJWQZQKHUJMW-UHFFFAOYSA-N [AlH3].[B] Chemical compound [AlH3].[B] FGUJWQZQKHUJMW-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 229910001868 water Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Weting (AREA)
Abstract
A kind of controlled silicon chip and its production method of punch-through, it is related to the manufacturing technology field of semiconductor devices, silicon wafer is oxidation-treated, dual surface lithography break-through isolation window carries out burn into cleaning, the diffusion of punch through isolation area boron doping, the diffusion of the area P1, P2 boron, the cathodic region photoetching N+, N to dual surface lithography break-through isolation window area+Area's phosphorus diffusion, photoetching circular table trench openings, etched mesa groove, passivated mesa groove and etc., obtain the controlled silicon chip of punch-through.When window is isolated in dual surface lithography break-through, window width is isolated in the break-through that the break-through isolation window width of positive photoetching is less than reverse side photoetching.Using the design method of the erosion grooves of the obverse and reverse sides different in width in punch through isolation area, the front mode narrow relative to reverse side shortens break-through diffusion time, improves the utilization rate of silicon wafer.
Description
Technical field
The present invention relates to the manufacturing technology fields of semiconductor devices, especially the life of the controlled silicon chip with punch-through
Production technology.
Background technique
For a long time, in field of manufacturing semiconductor devices, people are in structure design, cost reduction, reliability, raising product
Cost performance etc., made unremitting effort.
The break-through isolation structure used in controlled silicon chip production at present mainly has laser beam perforation vacuum to expand constructed of aluminium, boron aluminium
Break-through isolation structure is spread, these prior arts have the following deficiencies:
1, laser beam perforation vacuum expands aluminum technology, forms break-through by the method that laser boring, the diffusion of vacuum stopped pipe aluminium, aluminium are spread again
Isolated area, the shortcoming of this method is laser beam perforation low efficiency, due to being covered with thickly dotted reach through hole, chip list on silicon wafer
Face out-of-flatness, silicon warp deformation, fragment rate is high in subsequent production procedure.
2, boron aluminum extension dissipates break-through isolation technology, and the process flow which forms break-through has: window, double is isolated in dual surface lithography
Face boron gives that deposition, two-sided ion implanting aluminium, oxide layer are thinned, high temperature spreads knot again, and the technical matters is complicated, is easy in break-through
It is low that infiltration, production efficiency are formed other than region.
In order to improve break-through diffusion production efficiency, Chinese patent ZL201310682748.X discloses a kind of cutting groove and is formed
Silicon-controlled break-through method, it is symmetrical in the front and back sides of each reach through region in the front and back of chip before spreading break-through technique
Ground is equipped with cutting-up slot, and break-through technique is then diffused into chip from cutting-up slot again.With this shorten diffusion break-through technique when
Between, so that production process is accelerated, improve production efficiency.
But cutting groove is wherein gone out using scribing machine cutting-up, and it is very high for the required precision of production technology, it is larger with time-consuming,
And its cutting groove depth is larger and leads to chip surface out-of-flatness, and silicon wafer bad mechanical strength during following process is easily stuck up
Bent and deflection is larger, fragment rate is high, directly affects the qualification rate of product.
Summary of the invention
The present invention's first is designed to provide the controllable of the high punch-through of a kind of production of convenience and high-efficiency, silicon wafer utilization rate
Silicon chip.
The controlled silicon chip of punch-through of the present invention includes being arranged in N-The diffusion region P2 of the tow sides of type silicon wafer and P1
Diffusion region, in the surrounding of chip around punch through isolation area is arranged, in the outer rim towards chip front side and the punch through isolation area of reverse side
It is respectively equipped with front etch groove and reverse side erosion grooves；
N is being respectively equipped with towards the diffusion region the P2 surface of chip front side+Diffusion region and P2 gate electrode, in punch through isolation area
Side and in P2 gate electrode and N+The chip front side setting annular passivation groove in the outside of cathode electrode；In the P1 of chip reverse side
Anode electrode is respectively set in the surface of diffusion region and punch through isolation area；In N+N is arranged in the outer surface of diffusion region+Cathode electrode；In core
SiO is respectively set in the surface of the positive diffusion region P2 of piece and punch through isolation area2Protection zone；
Feature of present invention is: the width of the front etch groove is less than the width of reverse side erosion grooves；It is described towards chip just
The face width of the punch through isolation area in face is less than the face width towards the punch through isolation area of chip reverse side.
The present invention uses the design method in the erosion grooves of the obverse and reverse sides different in width of punch through isolation area, also, just
The face mode narrow relative to reverse side not only shortens break-through diffusion time, can also make the break-through isolation for being ultimately towards chip front side
The surface area in area is less than the surface area towards the punch through isolation area of chip reverse side, and the utilization rate of silicon wafer is substantially increased with this.
Further, front etch groove width of the present invention is 10~30 μm, and the reverse side erosion grooves width is
25~60 μm.
Reverse side diffusion window mouth width of the present invention, area is big, and total impurities are more, the junction depth spread in identical temperature-time compared with
It is deep, and the intersection area with front diffusion junctions is increased, reduce the deviation precision of the requirement to logical precision up and down and scribing
It is required that effectively having ensured the reliability of positive counter voltage.The design of the above front and back sides erosion grooves width facilitates production and processing.
The thickness of usual chip is in 220~250 μ ms, front and back sides disclosed in Chinese patent ZL201310682748.X
Symmetrical cutting groove depth is respectively 77 ± 2 μm, and front and back sides add up depth of cut and reach 150 μm.The cutting slot number of this depth
It easily causes product that warped occurs, or even slight crack, fragment occurs.
For the erosion grooves depth that the present invention uses for 10~15 μm, front and back sides cumulative depth is 20~30 μm, is significantly smaller than
The single side of Chinese patent ZL201310682748.X cuts groove depth, and the groove of the present invention depth does not influence the subsequent system of silicon wafer
To make, the mechanical strength of silicon wafer is big, and the junction depth of break-through diffusion spreads few 10~15cm than conventional, therefore the break-through time greatly shortens,
Improve production efficiency.
The production method of the controlled silicon chip for being designed to provide above-mentioned punch-through of the present invention second.
Clean silicon wafer is taken successively to carry out oxidation processes, dual surface lithography break-through isolation window, dual surface lithography break-through is isolated
Window area carries out burn into cleaning, the diffusion of punch through isolation area boron doping, the diffusion of the area P1 and P2 boron, the cathodic region photoetching N+, N+Area's phosphorus
Diffusion, photoetching circular table trench openings, etched mesa groove, passivated mesa groove, lithography fair lead, evaporation of aluminum, aluminium anti-carve, aluminium
Alloy, production anode electrode, scribing.Feature of the present invention is: when window is isolated in the dual surface lithography break-through, positive photoetching is worn
Window width is isolated in the break-through that logical isolation window width is less than reverse side photoetching.
Two-sided while erosion grooves of the invention, two-sided boron diffusion is primary to be completed, and process flow is simple, high production efficiency, easily
Control, it is the stable product quality of formation, reliable.
In addition, window width is isolated after window is isolated in dual surface lithography break-through, in the photoetching break-through that front is formed in the present invention
It is 10~30 μm, it is 25~60 μm that window width, which is isolated, in the photoetching break-through that reverse side is formed.
It is in dual surface lithography break-through isolation windowhood method specifically: the light of 100CP is respectively coated in the obverse and reverse sides of silicon wafer
Then photoresist successively carries out front baking, exposure, development, then in HF, the NH for being 3: 6: 10 by volume ratio4F and H2The mixing of O composition
The silica in window is removed in solution, the deionized water with resistivity greater than 14M Ω .cm is rinsed 30 minutes, drying.
The positive and negative trench depth formed after corroding to dual surface lithography break-through isolation window area is respectively 10~15
μm。
The method corroded to dual surface lithography break-through isolation window area is: it is 1 that silicon wafer, which is placed in by volume ratio:
1: HAC, HF and the HNO of (4~6)3After being impregnated in the mixed acid solution of composition, then silicon wafer is handled through aqueous sulfuric acid and removes silicon
The photoresist on piece surface.
The punch through isolation area boron doping diffusion is divided into prediffusion and spreads again to be carried out twice:
Prediffusion is: the silicon wafer that boron liquid source is respectively coated in obverse and reverse sides is placed in the diffusion furnace that temperature is 1070 ± 5 DEG C,
In the N for being 1: 1 by volume ratio2And O2Mixed gas in handle 100~120 minutes；
Spreading again is: in the diffusion furnace that temperature is 1265 ± 5 DEG C, first in the N for being 2: 1: 2 by volume ratio2、H2And O2It is mixed
It closes and is handled in gas 90 minutes, then in the N for being 1: 1 by volume ratio2And O2Mixed gas in handle 130~180 hours.
Detailed description of the invention
Fig. 1 is product of the present invention structural schematic diagram.
Specific embodiment
One, production technology:
Prepare No. 1 electronics cleaning solution: the NH for being 1: 2: 5 by volume ratio4OH、H2O2And H2O is mixed.
Prepare No. 2 electronics cleaning solutions: HCL, the H for being 1: 2: 6 by volume ratio2O2And H2The row mixing of O.
Selection resistivity is 35~45 Ω .cm, the N-type silicon materials corruption piece that piece thickness is 235~245 μm, according to following step
Rapid production controlled silicon chip.
1, Wafer Cleaning:
The N-type silicon materials corruption piece of selection is cleaned with No. 1 electronics cleaning solution and No. 2 electronics cleaning solutions, cleaning solution it is anti-
85 ± 5 DEG C of temperature are answered, the reaction time 10 minutes, is rinsed 30 minutes with deionized water (resistivity is greater than 14M Ω .cm), drying takes
Obtain clean silicon wafer.
2, it aoxidizes:
Clean silicon wafer is loaded into slide glass boat, diffusion furnace is pushed into, 1150 ± 5 DEG C is warming up to, in N2And O2The mixed gas of composition
Middle oxidation 40~50 minutes, then in N2、H2And O2It is aoxidized 240 ± 5 minutes in the mixed gas of composition, finally in N2And O2Composition
Mixed gas in aoxidize 40~50 minutes.
After slide glass boat is pulled out, remove silicon wafer.
The above N2And O2N in the mixed gas of composition2And O2Volume ratio is 1: 1；
N2、H2And O2N in the mixed gas of composition2、H2And O2Volume ratio be 2: 1: 2.
3, window is isolated in dual surface lithography break-through:
The photoresist of 100CP is coated respectively in the tow sides of silicon wafer, carries out front baking, exposure, development, is being 3 by volume ratio:
6: 10 HF, NH4F and H2The silica in window is removed in the mixed solution of O composition, with resistivity greater than 14M Ω .cm's
Deionized water is rinsed 30 minutes, drying.
The width L1 of the positive break-through isolation graph window formed after photoetching is 10~30 μm, and the arc radius at four angles is
300~700 μm, the width L2 of the logical isolation graph window of back side break-through is 25~60 μm, the arc radius at four angles is 350~
900μm.And pay attention to the width for being less than break-through isolation window in the back side in the width of positive break-through isolation window for each specific product
Degree.
4, photoetching break-through isolation window area is corroded:
It is 1: 1: HAC, HF and the HNO of (4~6) that silicon wafer, which is placed in by volume ratio,3It impregnates in the mixed acid solution of composition to corrode
It is molten to be put into sulfuric acid after the corrosion depth in positive and negative break-through isolation window area respectively reaches 10~15 μm by groove for silicon wafer
In liquid, the photoresist of silicon chip surface is removed.
5, it cleans:
It is cleaned with No. 1 electronics cleaning solution and No. 2 electronics cleaning solutions, 85 ± 5 DEG C of the reaction temperature of cleaning solution, the reaction time 10
Minute, the deionized water with resistivity greater than 14M Ω .cm is rinsed 30 minutes, drying.
6, punch through isolation area is spread:
Boron liquid source is being coated respectively by the silicon wafer obverse and reverse sides handled above, is loading onto slide glass boat, is pushed into diffusion furnace, heating
To 1070 ± 5 DEG C, in the N for being 1: 1 by volume ratio2And O2Mixed gas in carry out prediffusion, the time 100~120 minutes,
Slide glass boat is pulled out after diffusion, removes silicon wafer.
It spreads again punch through isolation area: loading onto slide glass boat, be pushed into diffusion furnace, 1265 ± 5 DEG C are warming up to, first by volume ratio
For 2: 1: 2 N2、H2And O2Mixed gas in spread 90 minutes, then in the N for being 1: 1 by volume ratio2And O2Gaseous mixture
It is spread 130~180 hours in body.
Slide glass boat is pulled out after diffusion, removes silicon wafer.
The present invention spreads relatively symmetrical corrosion-free ditch of total used time using the punch through isolation area of asymmetric two-sided erosion grooves
Slot mode shortens 10%~15%.
7, Wafer Cleaning:
With the HF and H for being 1: 1 by volume ratio2The SiO of the cleaning solution cleaning removal silicon chip surface of O mixing composition2。
8, the area P1 and P2 boron is spread:
Prediffusion: coating boron liquid source in silicon wafer tow sides respectively, loads onto slide glass boat, is pushed into diffusion furnace, is warming up to 930 ± 5
DEG C, in the N for being 1: 1 by volume ratio2And O2Mixed gas in spread 60~80 minutes.
Slide glass boat is pulled out after diffusion, removes silicon wafer.
It spreads again: silicon wafer being loaded into slide glass boat, diffusion furnace is pushed into, is warming up to 1250 ± 5 DEG C, be 2: 1: 2 by volume ratio
N2、H2、O2Mixed gas in spread 90 minutes, then again in the N for being 1: 1 by volume ratio2And O2Mixed gas in spread 9
~16 hours, the diffusion region P2 and the diffusion region P1 were formed in the front and back sides of silicon wafer.
Finally slide glass boat is pulled out, removes silicon wafer.
9, the cathodic region photoetching N+:
Coat 100CP photoresist in front side of silicon wafer, carry out front baking, exposure, development, then with the HF for being 3: 6: 10 by volume ratio,
NH4F and H2SiO in the mixed solution washing removal window of O composition2。
10、N+Area's phosphorus diffusion:
Phosphorus prediffusion: 1165 ± 5 DEG C, in the N for being 1: 1 by volume ratio2And O2Mixed gas in spread 100~120 minutes.
Phosphorus is spread again: 1240 ± 5 DEG C, first in the N for being 2: 1: 2 by volume ratio2、H2、O2Mixed gas in spread 90 points
Clock, then in the N for being 1: 1 by volume ratio2And O2Mixed gas in spread 150~200 minutes.
11, photoetching circular table trench openings, etched mesa groove:
450CP photoresist is coated in the front of silicon wafer, carries out front baking, exposure, development, it is 1: 1 that silicon wafer, which is put by volume ratio:
HAC, HF and the HNO of (4~6)3Table top molding is carried out in the mixed acid solution of composition, corrosion depth is 40~45 μm.
Horse is put into sulfuric acid solution, the photoresist of silicon chip surface is removed.
12, passivated mesa groove:
With GP350 type glass powder, it is coated in mesa trench.
13, lithography fair lead:
With 100CP photoresist.
14, evaporation of aluminum:
3~4 μm of aluminum layer thickness.
15, aluminium anti-carves:
With 100CP photoresist, P2 gate electrode and N+ cathode electrode are formed.
16, between P2 gate electrode and the diffusion region P2, in N+Cathode electrode and N+Aluminium conjunction is carried out between diffusion region simultaneously
Gold:
Temperature: 470 ± 10 DEG C, the time: 0.5 ± 0.1h.
17, silicon chip back side metallizes:
TiNiAg is evaporated, Ti film thickness is 1100~1500 angstroms；Ni film thickness is 4000~6000 angstroms；Ag film thickness is 0.6~0.9 μm,
Form anode electrode A.
18, it tests.
19, it takes the qualified product of test to carry out scribing, obtains controlled silicon chip.
Two, the controlled silicon chip design feature formed:
As shown in Figure 1, the present invention is in N-The obverse and reverse sides of type silicon wafer 1 are respectively arranged with the diffusion region P2 3 and the diffusion region P1 2, in core
The surrounding of piece is respectively equipped with around setting punch through isolation area 10 in the outer rim towards chip front side and the punch through isolation area 10 of reverse side
Front etch groove and reverse side erosion grooves 11.
Front etch groove width L1 is 10~30 μm, and depth H 1 is 10~15 μm.
Reverse side erosion grooves width L2 is 25~60 μm, and depth H 2 is 10~15 μm.
N is being respectively equipped with towards 3 surface of the diffusion region P2 of chip front side+Diffusion region 4 and P2 gate electrode 7, in N+Diffusion region
N is arranged in 4 outer surface+Cathode electrode 8.
SiO is respectively set in the diffusion region P2 3 of chip front side and the surface of punch through isolation area 102Protection zone 5.
In 10 inside of punch through isolation area and in P2 gate electrode 7 and N+Ring is arranged in the chip front side in the outside of cathode electrode 8
Shape is passivated groove 6；Anode electrode 9 is respectively set in the diffusion region P1 2 of chip reverse side and the surface of punch through isolation area 10.
It is less than towards the face width M1 of the punch through isolation area of chip front side 10 towards the punch through isolation area of chip reverse side 10
Face width M2.
Claims (9)
1. a kind of controlled silicon chip of punch-through, including be arranged in N-The diffusion region P2 of the tow sides of type silicon wafer and P1 diffusion
Distinguish in the surrounding of chip around punch through isolation area is arranged towards chip front side and the outer rim of the punch through isolation area of reverse side in area
Equipped with front etch groove and reverse side erosion grooves；N is being respectively equipped with towards the diffusion region the P2 surface of chip front side+Diffusion region and
P2 gate electrode, on the inside of punch through isolation area and in P2 gate electrode and N+Ring is arranged in the chip front side in the outside of cathode electrode
Shape is passivated groove；Anode electrode is respectively set in the diffusion region P1 of chip reverse side and the surface of punch through isolation area；In N+Diffusion region
Outer surface be arranged N+Cathode electrode；SiO is respectively set in the diffusion region P2 of chip front side and the surface of punch through isolation area2Protection
Area；It is characterized by: the width of the front etch groove is less than the width of reverse side erosion grooves；It is described towards chip front side
The face width of punch through isolation area is less than the face width towards the punch through isolation area of chip reverse side.
2. the controlled silicon chip of punch-through according to claim 1, it is characterised in that the front etch groove width is
10~30 μm, the reverse side erosion grooves width is 25~60 μm.
3. the controlled silicon chip of punch-through according to claim 2, which is characterized in that the depth of the front etch groove
It is 10~15 μm, the depth of the reverse side erosion grooves is 10~15 μm.
4. the production method of the controlled silicon chip of punch-through as described in claim 1, takes clean silicon wafer successively to be aoxidized
Processing, dual surface lithography break-through isolation window carry out burn into cleaning, punch through isolation area to dual surface lithography break-through isolation window area
Boron doping diffusion, the diffusion of the area P1 and P2 boron, the cathodic region photoetching N+, N+Area's phosphorus diffusion, photoetching circular table trench openings, corrosion platform
Face groove, passivated mesa groove, lithography fair lead, evaporation of aluminum, aluminium anti-carve, aluminium alloy, make anode electrode, scribing；
It is characterized by: the break-through isolation window width of positive photoetching is less than anti-when window is isolated in the dual surface lithography break-through
Window width is isolated in the break-through of face photoetching.
5. the production method of the controlled silicon chip of punch-through according to claim 4, it is characterised in that cut through in dual light
After logical isolation window, it is 10~30 μm that window width, which is isolated, in the photoetching break-through that front is formed, in the photoetching break-through that reverse side is formed
It is 25~60 μm that window width, which is isolated,.
6. the production method of the controlled silicon chip of punch-through according to claim 5, it is characterised in that described in dual light
Cutting through logical isolation windowhood method is: the photoresist of 100CP is respectively coated in the obverse and reverse sides of silicon wafer, then successively carry out front baking,
Exposure, development, then in HF, the NH for being 3: 6: 10 by volume ratio4F and H2The dioxy in window is removed in the mixed solution of O composition
SiClx, the deionized water with resistivity greater than 14M Ω .cm are rinsed 30 minutes, drying.
7. according to the production method of the controlled silicon chip of the punch-through of claim 5 or 6, it is characterised in that dual surface lithography
The positive and negative trench depth that break-through isolation window area is formed after being corroded is respectively 10~15 μm.
8. the production method of the controlled silicon chip of punch-through according to claim 7, it is characterised in that described to dual light
Cutting through the method that logical isolation window area is corroded is: it is 1: 1 by volume ratio that silicon wafer, which is placed in: HAC, the HF of (4~6) and
HNO3After impregnating in the mixed acid solution of composition, then silicon wafer is handled to the photoresist for removing silicon chip surface through aqueous sulfuric acid.
9. the production method of the controlled silicon chip of punch-through according to claim 4, it is characterised in that the break-through isolation
Boron doping diffusion in area's is divided into prediffusion and spreads again to be carried out twice；
Prediffusion is: the silicon wafer that boron liquid source is respectively coated in obverse and reverse sides is placed in the diffusion furnace that temperature is 1070 ± 5 DEG C,
In the N for being 1: 1 by volume ratio2And O2Mixed gas in handle 100~120 minutes；
Spreading again is: in the diffusion furnace that temperature is 1265 ± 5 DEG C, first in the N for being 2: 1: 2 by volume ratio2、H2And O2It is mixed
It closes and is handled in gas 90 minutes, then in the N for being 1: 1 by volume ratio2And O2Mixed gas in handle 130~180 hours.
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