CN103151263B - A kind of thyristor chip preparation method - Google Patents
A kind of thyristor chip preparation method Download PDFInfo
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- CN103151263B CN103151263B CN201310075823.6A CN201310075823A CN103151263B CN 103151263 B CN103151263 B CN 103151263B CN 201310075823 A CN201310075823 A CN 201310075823A CN 103151263 B CN103151263 B CN 103151263B
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- aluminium
- logical
- silicon chip
- diffusion
- chip
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 71
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 71
- 239000004411 aluminium Substances 0.000 claims abstract description 59
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000010703 silicon Substances 0.000 claims abstract description 54
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 54
- 238000009792 diffusion process Methods 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000005498 polishing Methods 0.000 claims abstract description 16
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- 238000001704 evaporation Methods 0.000 claims abstract description 10
- 230000008020 evaporation Effects 0.000 claims abstract description 10
- 238000003475 lamination Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000007796 conventional method Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000012797 qualification Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229960000583 acetic acid Drugs 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000003708 ampul Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 239000012362 glacial acetic acid Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- -1 hydrogen potassium oxide Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910001950 potassium oxide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
The present invention relates to a kind of thyristor chip preparation method, wherein aluminium adopts first photoetching and etching groove in logical method of diffusion, then carries out two-sided evaporation of aluminum, prediffusion, polishing and aluminium to silicon chip successively and spreads logical again, makes silicon chip form aluminium to logical isolated area.Grooving and polishing combine by the present invention, grooving is spread shorten logical diffusion time, thoroughly remove aluminium lamination by polishing and anti-carve residual aluminium island, solve the aluminium island problem that in the preparation of conventional method thyristor chip, silicon chip exists logical diffusion, the present invention can make thyristor chip rate of finished products improve more than 10%.
Description
Technical field
The present invention relates to a kind of thyristor chip preparation method, belong to semiconductor device processing technology field.
Background technology
At present, in the method preparing chip of square thyristor, generally all comprise and formed logical isolated area with to logical diffusion method, pure boron, gallium aluminium or fine aluminium are mainly divided into the diffuse source that logical part adopts.Fine aluminium be to the advantage of logical diffuse source be diffusion time short, speed fast, the N-type silicon chip two face portion P type of more than 400 microns can be realized to leading to.Silicon chip completes after logical isolation, then carries out passivation in p type impurity diffusion, photoetching, N-type impurity diffusion, table top moulding, groove, two-sided metallization and chip separation successively, finally makes thyristor chip.
The aluminium of prior art comprises the following steps logical diffusion conventional method: (1) Wafer Cleaning; (2) the two-sided evaporation of aluminum of silicon chip; (3) photoengraving aluminium; (4) to logical diffusion, aluminium is formed to logical isolated area.Conventional simple to logical diffusion method technique, but because this is carry out logical diffusion to the aluminium of silicon chip surface to circulation method, its diffusion time is long, diffusion temperature is high, and particularly owing to anti-carving aluminium, its reticle overwhelming majority is black matrix, area is larger, be difficult to intact in the process of reprint, then in photoetching process, silicon chip contact with reticle and easily causes reticle to damage, and inevitably produces aluminium island thus at silicon chip surface.And because silicon dioxide can not shield aluminium, gallium, aluminium island will spread in logical diffusion process in wafer bulk, its degree of depth and suitable to logical position diffusion depth, can cause forward and reverse voltage low pressure, even break-through, have a strong impact on the qualification rate of thyristor chip.
Summary of the invention
The present invention mainly solves the aluminium island problem that silicon chip in thyristor chip preparation uses conventional method to exist logical diffusion, newly provides a kind of thyristor chip preparation method, improves thyristor chip qualification rate.
A kind of thyristor chip preparation method of the present invention, comprises the following steps:
(1) select in the region of doing logical diffusion at silicon chip, with the etching groove of the method two sides symmetry of photoetching and corrosion, the wide 60-300 micron of its grooving, dark 20-120 micron;
(2) at the two-sided evaporation of aluminum of the silicon chip of grooving, aluminum layer thickness 0.3-3 micron;
(3) will the silicon chip of aluminium lamination in grooving, be had to be placed on prediffusion in diffusion furnace, temperature 600-1200 DEG C, time 1-20 hour;
(4) by the silicon chip twin polishing after prediffusion, one side removes thickness 5-15 micron;
(5) polished silicon slice is carried out in diffusion furnace aluminium to spread again logical, temperature 1200-1250 DEG C, time 10-50 hour, form aluminium to logical isolated area.
The present invention is in conjunction with grooving and finishing method, make silicon chip form aluminium to logical isolated area, its grooving shortened logical diffusion time, more thoroughly removed aluminium lamination through polishing and anti-carve residual island, with the conventional aluminium of employing to compared with circulation method, thyristor chip rate of finished products improves more than 10%.
Accompanying drawing explanation
Fig. 1 is that conventional method aluminium is to logical diffusion schematic flow sheet.
Fig. 2 is that aluminium of the present invention is to logical diffusion schematic flow sheet.
Embodiment
Accompanying drawing mark illustrate: after N-type silicon chip sectional view (1-1), the two-sided evaporation of aluminum of silicon chip after sectional view (1-2), silicon chip photoengraving aluminium sectional view (1-3), silicon chip aluminium to schematic cross-section (1-4) after logical diffusion; After N-type silicon chip schematic cross-section (2-1), silicon chip photoetching and etching groove after schematic cross-section (2-2), the two-sided evaporation of aluminum of silicon chip after schematic cross-section (2-3), silicon chip twin polishing schematic cross-section (2-4), silicon chip aluminium to schematic cross-section (2-5) after logical diffusion.And N-type silicon chip (10,20), grooving 21, aluminium lamination (12,22,23), aluminium is to logical isolated area (14,24).
As shown in (1-2) to (1-4) of Fig. 1, in conventional thyristor chip preparation method, its silicon chip aluminium to logical diffusing step is: the two-sided evaporation of aluminum of Wafer Cleaning, silicon chip, silicon chip photoengraving aluminium and silicon chip aluminium are to logical diffusion.
As shown in (1-2) to (1-5) of Fig. 2, a kind of thyristor chip preparation method of the present invention, comprises the following steps:
(1) in the selected region of doing logical diffusion isolation of silicon chip 20, with the etching groove 21 of the method two sides symmetry of photoetching and corrosion, the wide 60-300 micron of its grooving 21, dark 20-120 micron;
(2) at the two-sided evaporation of aluminum of the silicon chip of grooving 21, aluminium lamination (22,23) thickness 0.3-3 micron;
(3) will the silicon chip of aluminium lamination 23 in grooving 21, be had to be placed on prediffusion in diffusion furnace, temperature 600-1200 DEG C, time 1-20 hour;
(4) by the silicon chip twin polishing after prediffusion, one side removes thickness 5-15 micron;
(5) polished silicon slice is carried out in diffusion furnace aluminium to spread again logical, temperature 1200-1250 DEG C, time 10-50 hour, form aluminium to logical isolated area.
The present invention successively by Wafer Cleaning, photoetching corrosion grooving, evaporation of aluminum, prediffusion, polishing, spread logical, thus makes silicon chip complete aluminium to isolate logical diffusion again.Grooving and polishing combine by its method dexterously, shortened logical diffusion time, thoroughly remove aluminium lamination anti-carve residual island by polishing by grooving diffusion, and with conventional aluminium to compared with circulation method, thyristor chip rate of finished products of the present invention improves more than 10%.
In addition, polishing and aluminium are carried out passivation in p type impurity diffusion, photoetching, N-type impurity diffusion, table top moulding, groove, two-sided metallization and chip separation to the silicon chip after logical diffusion successively in rear operation, makes mesa thyristor chip.
Described p type impurity diffusion carries out the diffusion of gallium aluminium, temperature 1200-1260 DEG C under polishing and aluminium are placed on closed ampoule vacuum environment to the silicon chip after logical diffusion, time 10-30 hour, junction depth 30-120 micron, surface concentration 30-100 Europe nurse ∕ square, forms silicon chip base PN junction.
Described N-type impurity is diffused as phosphorus diffusion, diffusion temperature 1000-1200 DEG C, time 1-6 hour, junction depth 10-30 micron, surface concentration 0.08-1.5 Ou Mu ∕ square.
Described table top moulding, be adopt photoetching process to erode away etching tank, the component volume proportion of corrosive liquid is: fuming nitric aicd: nitric acid: hydrofluoric acid: glacial acetic acid=3:2:4:2, etching time: 5-8 minute; Groove depth 70-150 micron.
In described groove, passivation is glassivation.
Described two-sided metallization adopts evaporation aluminium, titanium, nickel, silver, alloy under vacuum and temperature 380-500 DEG C of condition.
Described chip separation is divided into single thyristor chip from aluminium to cutting in the middle of logical isolated area.
The present invention removes the deionized water solution that impurities on surface of silicon chip can use 5-20% concentration hydrogen potassium oxide or NaOH before photoetching corrosion grooving, heating 50-100 DEG C, etching time 5-30 minute, silicon chip surface glimmer.
The present invention carries out aluminium to logical diffusion in the bottom of grooving, and conventional aluminium carries out aluminium diffusion to logical method of diffusion at silicon chip surface, and with conventional method ratio, the present invention can shorten 20-50 hour to logical diffusion time.
At conventional aluminium in logical diffusion process, photo-mask process causes and remains island unavoidably at silicon face, makes the deliquescing of chip puncture voltage or break-through.And the inventive method carries out polishing after aluminium prediffusion, two-sidedly remove 5-15 micron respectively, by the aluminium lamination of silicon chip surface and anti-carve aluminium remain under aluminium island all remove totally, thus thyristor chip qualification rate is significantly improved.
The present invention adopts the method that grooving and polishing combine on silicon chip, enables silicon chip comparatively fast form aluminium to logical isolated area, and thoroughly solves the conventional aluminium of long-standing problem to the silicon chip surface residual aluminum island problem of logical diffusion technology.Polishing process removes silicon wafer thickness 5-15 micron, and rooved face width can be made to be reduced to width less than 1/2nd before polishing, but can not affect other operation and carry out.The present invention be also suitable for other semiconductor product to logical diffusion technology.
It is understood that above-described embodiment is just to explanation of the present invention, any innovation and creation do not exceeded in spirit of the present invention, all fall within protection scope of the present invention.
Claims (1)
1. a thyristor chip preparation method, is characterized in that: the method comprises the following steps:
(1) cleaning silicon chip;
(2) select in the region of doing logical diffusion at silicon chip, with the etching groove of the method two sides symmetry of photoetching and corrosion,
The wide 60-300 micron of its grooving, dark 20-120 micron;
(3) at the two-sided evaporation of aluminum of the silicon chip of grooving, aluminum layer thickness 0.3-3 micron;
(4) will the silicon chip of aluminium lamination in grooving, be had to be placed on prediffusion in diffusion furnace, temperature 600-1200 DEG C, time 1-20 hour;
(5) by the silicon chip twin polishing after prediffusion, one side removes thickness 5-15 micron;
(6) polished silicon slice is carried out in diffusion furnace aluminium to spread again logical, temperature 1200-1250 DEG C, time 10-50 hour, form aluminium to logical isolated area.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310075823.6A CN103151263B (en) | 2013-03-11 | 2013-03-11 | A kind of thyristor chip preparation method |
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| CN201310075823.6A CN103151263B (en) | 2013-03-11 | 2013-03-11 | A kind of thyristor chip preparation method |
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| CN103151263A CN103151263A (en) | 2013-06-12 |
| CN103151263B true CN103151263B (en) | 2015-08-19 |
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| CN104779156B (en) * | 2014-01-13 | 2017-10-17 | 中芯国际集成电路制造(上海)有限公司 | The minimizing technology of aluminium residual |
| CN105448807B (en) * | 2015-11-20 | 2017-11-10 | 浙江正邦电子股份有限公司 | A kind of semiconductor device chip is to logical isolation manufacturing process |
| CN114005743B (en) * | 2021-10-13 | 2022-08-30 | 华中科技大学 | Square semiconductor pulse power switch and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448589B1 (en) * | 2000-05-19 | 2002-09-10 | Teccor Electronics, L.P. | Single side contacts for a semiconductor device |
| CN1913130A (en) * | 2006-08-28 | 2007-02-14 | 汤庆敏 | Manufacturing process of semiconductor device chip punch through isolation area and PN junction |
| CN101901832A (en) * | 2010-06-28 | 2010-12-01 | 启东吉莱电子有限公司 | Controlled silicon punchthrough structure formed by gallium diffusion and production method thereof |
| CN101901763A (en) * | 2010-06-28 | 2010-12-01 | 启东吉莱电子有限公司 | Production technology of controllable silicon |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2743938B1 (en) * | 1996-01-19 | 1998-04-10 | Sgs Thomson Microelectronics | INTERFACE PROTECTION COMPONENT OF TELEPHONE LINES |
| CN201804873U (en) * | 2010-06-28 | 2011-04-20 | 启东吉莱电子有限公司 | Silicon-controlled structure capable of shortening punch-through time |
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- 2013-03-11 CN CN201310075823.6A patent/CN103151263B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448589B1 (en) * | 2000-05-19 | 2002-09-10 | Teccor Electronics, L.P. | Single side contacts for a semiconductor device |
| CN1913130A (en) * | 2006-08-28 | 2007-02-14 | 汤庆敏 | Manufacturing process of semiconductor device chip punch through isolation area and PN junction |
| CN101901832A (en) * | 2010-06-28 | 2010-12-01 | 启东吉莱电子有限公司 | Controlled silicon punchthrough structure formed by gallium diffusion and production method thereof |
| CN101901763A (en) * | 2010-06-28 | 2010-12-01 | 启东吉莱电子有限公司 | Production technology of controllable silicon |
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| CN103151263A (en) | 2013-06-12 |
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Address after: 321400 Zhejiang County of Jinyun city of Lishui Province East five East Industrial Zone Zhejiang Zhengbang Power Electronics Co Ltd Patentee after: ZHEJIANG ZHENGBANG ELECTRONIC CO.,LTD. Address before: 321400 Zhejiang County of Jinyun city of Lishui Province East five East Industrial Zone Zhejiang Zhengbang Power Electronics Co Ltd Patentee before: ZHEJIANG ZHENGBANG ELECTRIC POWER ELECTRONICS Co.,Ltd. |
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Denomination of invention: A method for preparing thyristor chips Granted publication date: 20150819 Pledgee: Lishui Jinyun Sub branch of Zhejiang Tailong Commercial Bank Co.,Ltd. Pledgor: ZHEJIANG ZHENGBANG ELECTRONIC CO.,LTD. Registration number: Y2024980007381 |