CN210575961U

CN210575961U - Reduce schottky diode chip of energy consumption

Info

Publication number: CN210575961U
Application number: CN201920980336.7U
Authority: CN
Inventors: 燕云峰
Original assignee: Shenzhen Dasenlin Optoelectronic Technology Co ltd
Current assignee: Shenzhen Dasenlin Optoelectronic Technology Co ltd
Priority date: 2019-06-26
Filing date: 2019-06-26
Publication date: 2020-05-19
Anticipated expiration: 2029-06-26

Abstract

The utility model discloses a Schottky diode chip for reducing energy consumption, which relates to a semiconductor device and comprises a silicon wafer substrate, wherein the bottom of the silicon wafer substrate is provided with a boron plating layer, the top of the silicon wafer substrate is provided with a phosphorus plating layer, the surface of the silicon wafer is provided with a light-doped boron diffusion layer P and a thick-doped boron diffusion layer P +, and an N-epitaxial layer is arranged on a semiconductor silicon wafer N + substrate; and etching the N-epitaxial layer to form a silicon groove, diffusing boron impurity to a certain depth in the silicon groove in a high-temperature oxidation and diffusion mode to form a P + active region, and forming an oxide layer with a certain thickness on the surface of the P + active region through high-temperature oxidation. The utility model discloses a V type groove is drawn out to the mode that the cutting adds the corruption on the chip, has increased the effective area of contact of chip, has reduced the power of diode to reduce the energy consumption of chip, it is more energy-concerving and environment-protective.

Description

Reduce schottky diode chip of energy consumption

Technical Field

The utility model relates to a semiconductor device specifically is a schottky diode chip of reduction energy consumption.

Background

With the development of the electronic industry, the improvement of the efficiency of a circuit system by the low conduction voltage drop and the extremely short reverse recovery time of a Schottky Barrier Diode (SBD) causes high attention and wide application of people, the conventional Schottky Barrier Diode chip does not perform slotting treatment on the chip, the effective contact area of the chip is small, and the energy consumption of the chip is high.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a reduce schottky diode chip of energy consumption has energy-concerving and environment-protective beneficial effect to solve the problem that proposes in the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

a Schottky diode chip capable of reducing energy consumption comprises a silicon wafer substrate, wherein a boron plating layer is arranged at the bottom of the silicon wafer substrate, a phosphorus plating layer is arranged at the top of the silicon wafer substrate, a light-doped boron diffusion layer P and a concentrated boron diffusion layer P + are arranged on the surface of a silicon wafer, and an N-epitaxial layer is arranged on a semiconductor silicon wafer N + substrate; and etching the N-epitaxial layer to form a silicon groove, diffusing boron impurity to a certain depth in the silicon groove in a high-temperature oxidation and diffusion mode to form a P + active region, and forming an oxide layer with a certain thickness on the surface of the P + active region through high-temperature oxidation.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses a V type groove is drawn out to the mode that the cutting adds the corruption on the chip, has increased the effective area of contact of chip, has reduced the power of diode to reduce the energy consumption of chip, it is more energy-concerving and environment-protective.

Drawings

Fig. 1 is a schematic structural diagram of the present invention.

Fig. 2 is a schematic structural view of the V-shaped groove of the present invention.

The labels in the figure are:

the structure comprises a passivation layer 1, a silicon wafer substrate 2, a PN junction surface 3 and a V-shaped groove 4.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-2, in an embodiment of the present invention, a schottky diode chip with reduced energy consumption includes a silicon wafer substrate 2, a boron-plated layer is disposed at the bottom of the silicon wafer substrate 2, a phosphorus-plated layer is disposed at the top of the silicon wafer substrate 2, a light-doped boron diffusion layer P and a heavy-doped boron diffusion layer P + are disposed on the surface of the silicon wafer, and an N-epitaxial layer is disposed on a semiconductor silicon wafer N + substrate; and etching the N-epitaxial layer to form a silicon groove, diffusing boron impurity to a certain depth in the silicon groove in a high-temperature oxidation and diffusion mode to form a P + active region, and forming an oxide layer with a certain thickness on the surface of the P + active region through high-temperature oxidation.

As a further aspect of the present invention: the manufacturing method of the chip comprises the following steps: the method comprises the following steps: original piece cleaning: cleaning the surface of the silicon wafer substrate 2 in an acid washing or alkali washing mode; step two: diffusion: manufacturing a phosphorus diffusion layer and a boron diffusion layer on a silicon substrate to form a PN junction; step three: primary photoetching: coating a layer of photoresist on the surface of a silicon wafer, and transferring a design pattern on a mask plate to the surface of the silicon wafer through exposure, development, fixation and hardening; step four: step corrosion: etching the part which is not covered by the photoresist to form a V-shaped groove 4 by using mixed acid; step five: secondary photoetching: coating a layer of photoresist on the surface of a silicon wafer, and transferring a design pattern on a mask plate to the surface of the silicon wafer through exposure, development, fixation and hardening; step six: and (4) corrosion of the V-shaped groove: etching the photoetched pattern by using a chemical etching mode, wherein the pattern is generally etched by using mixed acid, and the depth of the pattern needs to exceed the PN junction surface 3 so as to expose the PN junction; step seven: passivation: coating glass powder in a silicon wafer V-shaped groove 4, and melting and molding the glass powder in a high-temperature furnace tube to form a stable and compact passivation layer 1; eighthly: coating a layer of photoresist on the surface of a silicon wafer, and transferring a design pattern on a mask plate to the surface of the silicon wafer through exposure, development, fixation and hardening; nine: metallization, namely plating nickel and gold on the surfaces of the concentrated phosphorus-doped diffusion layer N + and the concentrated boron-doped diffusion layer P +; ten: and scribing, namely dividing the silicon wafer into single diode chips.

As a further aspect of the present invention: in the fourth step, a V-shaped groove 4 is formed by a high-speed grinding wheel groove cutting machine, so that the tube core forms a 75-90-degree negative bevel table top, and the groove depth is 90-100 mu m

The utility model discloses a V type groove 4 is drawn out to the mode that the cutting adds the corruption on the chip, has increased the effective area of contact of chip, has reduced the energy consumption of chip.

Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.

Claims

1. A Schottky diode chip capable of reducing energy consumption is characterized by comprising a silicon wafer substrate (2), wherein a boron plating layer is arranged at the bottom of the silicon wafer substrate (2), a phosphorus plating layer is arranged at the top of the silicon wafer substrate (2), a light-doped boron diffusion layer P and a concentrated boron diffusion layer P + are arranged on the surface of a silicon wafer, and an N-epitaxial layer is arranged on a semiconductor silicon wafer N + substrate; etching to form a silicon groove on the N-epitaxial layer, diffusing boron impurity to a certain depth in the silicon groove in a high-temperature oxidation and diffusion mode to form a P + active region, and forming an oxide layer with a certain thickness on the surface of the P + active region through high-temperature oxidation.