CN219979571U - Power transistor with low amplification factor change rate - Google Patents
Power transistor with low amplification factor change rate Download PDFInfo
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- CN219979571U CN219979571U CN202320813899.3U CN202320813899U CN219979571U CN 219979571 U CN219979571 U CN 219979571U CN 202320813899 U CN202320813899 U CN 202320813899U CN 219979571 U CN219979571 U CN 219979571U
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- epitaxial layer
- change rate
- power transistor
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- 230000003321 amplification Effects 0.000 title claims abstract description 13
- 238000003199 nucleic acid amplification method Methods 0.000 title claims abstract description 13
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 235000012431 wafers Nutrition 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 239000011521 glass Substances 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 230000002035 prolonged effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 32
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- HZEWFHLRYVTOIW-UHFFFAOYSA-N [Ti].[Ni] Chemical compound [Ti].[Ni] HZEWFHLRYVTOIW-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- Bipolar Transistors (AREA)
Abstract
The power transistor with low amplification factor change rate comprises an N+ collecting region formed by single-sided polished single crystal wafers, wherein an N-epitaxial layer is arranged on the N+ collecting region corresponding to the polished surface of the single crystal wafers, a P-type epitaxial layer is arranged on the upper surface of the N-epitaxial layer, a P+ contact region is arranged on the upper surface of the P-type epitaxial layer, an N+ emitting region is arranged on the upper surface of the P+ contact region, transistor base electrodes B and emitter electrodes E are respectively led out of the surfaces of the P+ contact region and the N+ emitting region, and a collector electrode C is led out of the N+ collecting region corresponding to the polished surface of the single crystal wafers. The P-type epitaxial layer is arranged on the upper surface of the N-epitaxial layer, the P+ contact region is arranged on the upper surface of the P-type epitaxial layer, and the P-type epitaxial base region is used for replacing base boron diffusion of the NPN transistor, so that high-temperature long-time diffusion is avoided, the process time is shortened, the production efficiency is improved, and the manufacturing cost is reduced; meanwhile, the low-temperature change rate of the amplification factor is also low, the minority carrier lifetime is prolonged, and the reliability of the device is improved.
Description
Technical Field
The present utility model relates to a semiconductor device, and more particularly, to a power transistor with a low amplification factor change rate.
Background
The conventional low-frequency high-power NPN transistor mostly adopts a triple diffusion process, namely, the substrate manufacturing, the base region manufacturing and the emitter region manufacturing are all adopted diffusion methods, the base region diffusion generally adopts an ion implantation or diffusion source method, a diffusion region of 20-25 mu m is formed at a high temperature, in order to obtain a lower amplification factor change rate, the base region generally adopts a higher doping concentration, no matter the implantation method and the diffusion source method cannot avoid a high-temperature long-time diffusion process, so that the production efficiency is low, the manufacturing cost is higher, and the amplification factor change rate of a product is not easy to meet the actual use requirements of special users.
Disclosure of Invention
The utility model aims to solve the technical problem of providing a power transistor with low amplification factor change rate, which not only avoids high-temperature long-time diffusion, but also can obtain low-temperature change rate with small amplification factor.
The technical scheme of the utility model is as follows:
the utility model provides a low magnification change rate's power transistor, includes the N+ collector region that is formed by single-sided polished monocrystalline wafer, is equipped with N-epitaxial layer at N+ collector region corresponds the polished surface of monocrystalline wafer, characterized by: the upper surface of the N-epitaxial layer is provided with a P-type epitaxial layer, the upper surface of the P-type epitaxial layer is provided with a P+ contact region, the upper surface of the P+ contact region is provided with an N+ emission region, the surfaces of the P+ contact region and the N+ emission region are respectively led out of a transistor base B and an emitter E, and the N+ collector region is correspondingly led out of a collector C from the grinding surface of the single crystal wafer.
Furthermore, a glass passivation groove table surface is arranged on the side surface of the P+ contact region and the collector junction, so that the collector junction is protected.
Further, a first silicon dioxide oxide layer is arranged on the upper surface of the P+ contact region, and a second silicon dioxide oxide layer is arranged on the surface of the first silicon dioxide oxide layer and the surface of the N+ emission region.
Further, the junction depth of the N+ emission region is greater than that of the P+ contact region.
Further, the n+ emission region is comb-shaped.
Further, the single-sided polished single-crystal wafer has a crystal orientation of <111>, a resistivity of 0.002 to 0.003 Ω·cm, and a thickness of 450±5 μm.
Further, the thickness of the N-epitaxial layer is 20-50 mu m, and the resistivity of the N-epitaxial layer is 7-20Ω & cm.
Further, the thickness of the P-type epitaxial layer is 20-25 mu m, and the resistivity of the P-type epitaxial layer is 4-5Ω & cm.
Further, the junction depth of the P+ contact region is 1.5-2 μm, and the surface concentration is 4-5×10 18 cm -3 。
Further, the junction depth of the N+ emission region is 2.1-3 μm, and the surface impurity concentration of the N+ emission region is 1-2×10 20 cm -3 。
The beneficial effects of the utility model are as follows: the upper surface of the N-epitaxial layer is provided with a P-type epitaxial layer, the upper surface of the P-type epitaxial layer is provided with a P+ contact region, the upper surface of the P+ contact region is provided with an N+ emitter region, and the boron diffusion base region of the NPN transistor is replaced by a P-type epitaxial base region, so that high-temperature long-time diffusion is avoided, the process time is shortened, the production efficiency is improved, and the manufacturing cost is reduced; meanwhile, the low-temperature change rate (-55 ℃) of the amplification factor is also obtained, the delta beta/beta is less than or equal to 40 percent, the minority carrier lifetime is prolonged, and the reliability of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a low magnification change rate power transistor die made in accordance with the present utility model;
fig. 2 is a schematic diagram of a low magnification change rate power transistor die layout made in accordance with the present utility model.
In the figure: the first metal aluminum electrode comprises a second 1-silicon dioxide oxide layer, a first 2-silicon dioxide oxide layer, a first 3-inner groove table surface, a 4-N-epitaxial layer region, a 5-N+ collector region, a 6-metal titanium nickel silver electrode, a 7-P-type epitaxial layer, an 8-P+ contact region, a 9-N+ emission region, a second 10-metal aluminum electrode and a first 11-metal aluminum electrode.
Detailed Description
The utility model is described in detail below with reference to the attached drawing figures:
as shown in the figure, the power transistor with low amplification factor change rate comprises an N+ collector region 5 formed by single-sided polished N-type single crystal wafers, an N-epitaxial layer 4 is arranged on the polished surface of the N+ collector region 5 corresponding to the N-type single crystal wafers, a P-type epitaxial layer 7 is arranged on the upper surface of the N-epitaxial layer 5, a P+ contact region 8 is arranged on the upper surface of the P-type epitaxial layer 7, an N+ emitter region 9 is arranged on the upper surface of the P+ contact region 8, a silicon dioxide oxide layer I2 is arranged on the upper surface of the P+ contact region 8, a silicon dioxide oxide layer II 1 is arranged on the surface of the silicon dioxide oxide layer I2 and the surface of the N+ emitter region 9, glass passivation is carried out around the P+ contact region and the collector junction by glass powder to form an inner groove table top 3, so that the collector junction is protected, a metal aluminum electrode I11, a metal aluminum electrode II 10 and a metal titanium nickel electrode 6 are respectively formed on the polished surfaces of the P+ contact region 8 and the N+ emitter region 9 corresponding to the N-type single crystal wafers, and the corresponding transistor base B, emitter E and collector C are led out.
The manufacturing method of the power transistor with low amplification factor change rate comprises the following steps:
s1, selecting a single-side polished N-type single crystal wafer with a crystal orientation <111> to form an N+ collector region 5, wherein the resistivity of the N+ collector region is 0.002-0.003 omega cm, and the thickness of the N+ collector region is 450+/-5 mu m;
s2, forming an N-epitaxial layer 4 on the polished surface of the N+ collector region 5 corresponding to the N-type single crystal wafer through an epitaxial process, wherein the resistivity is 10-15 omega cm, and the thickness is 25-30 mu m;
s3, forming a P-type epitaxial layer 7 on the upper surface of the N-epitaxial layer 4 through an epitaxial process, wherein the resistivity of the P-type epitaxial layer is 4-5Ω & cm, and the thickness of the P-type epitaxial layer is 20-25 mu m;
s4, boron is spread on the surface of the P-type epitaxial layer 7 to form a P+ contact region 8, the junction depth of the P+ contact region 8 is controlled to be 1.5-2 mu m, and the surface concentration is controlled to be 4-5 multiplied by 10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Forming a silicon dioxide protection layer I2 on the upper surface of the P+ contact region 8;
s5, photoetching and corroding the surface center of the P+ contact region 8, diffusing phosphorus to form an N+ emission region 9, wherein the surface impurity concentration is 1-2 multiplied by 10 20 cm -3 The junction depth is 2.1-3 mu m; forming a second silicon nitride protective layer 1 on the surface of the first silicon dioxide protective layer 2 and the surface of the N+ emission region 9;
s6, forming an inner groove table top 3 at the side surface of the P+ contact area and the side surface of the collector junction by using a photoetching masking and glass passivation process, so as to realize the protection of the collector junction;
and S7, evaporating metal on the grinding surfaces of the P+ contact region 8, the emitting region 9 and the N+ collector region 5 corresponding to the N-type single crystal wafer, etching the metal and passivating the silicon nitride to form a first metal aluminum electrode 11, a second metal aluminum electrode 10 and a second metal titanium nickel silver electrode 6 respectively, and leading out a base electrode B, an emitter electrode E and a collector electrode C of the transistor.
User requirements: at-55 ℃, Δβ/β+.40%; the final electrical parameters of the fabricated devices were tested according to the process steps and process conditions of example 3 as follows:
Claims (10)
1. the power transistor with low amplification factor change rate comprises an N+ collecting region formed by single-sided polished single crystal wafers, wherein an N-epitaxial layer is arranged on the N+ collecting region corresponding to the polished surface of the single crystal wafers.
2. The low-amplification-factor-change-rate power transistor of claim 1, wherein glass passivation trench mesas are provided on sides of the p+ contact region and the collector junction to protect the collector junction.
3. A low magnification change rate power transistor according to claim 1 or 2, wherein a first silicon oxide layer is provided on the upper surface of the p+ contact region, and a second silicon oxide layer is provided on the first silicon oxide layer and the surface of the n+ emitter region.
4. The low-magnification change rate power transistor according to claim 1 or 2, wherein a junction depth of the n+ emitter region is larger than a junction depth of the p+ contact region.
5. The low-magnification change rate power transistor according to claim 1 or 2, wherein the n+ emission region is comb-shaped.
6. The low magnification power transistor according to claim 1 or 2, wherein the single-sided polished single crystal wafer has a crystal orientation of <111>, a resistivity of 0.002 to 0.003 Ω -cm, and a thickness of 450±5 μm.
7. A low magnification change rate power transistor according to claim 1 or 2, characterized in that the thickness of the N-epitaxial layer is 20-50 μm and the resistivity of the N-epitaxial layer is 7-20Ω -cm.
8. A low magnification change rate power transistor according to claim 1 or 2, wherein the P-type epitaxial layer has a thickness of 20-25 μm and a resistivity of 4-5 Ω -cm.
9. A low magnification change rate power transistor according to claim 1 or 2, wherein the junction depth of the p+ contact region is 1.5-2 μm, and the surface concentration is 4-5 x 10 18 cm -3 。
10. The low-magnification change rate power transistor according to claim 1 or 2, wherein the junction depth of the n+ emitter region is 2.1-3 μm, and the surface impurity concentration of the n+ emitter region is 1-2 x 10 20 cm -3 。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320813899.3U CN219979571U (en) | 2023-04-13 | 2023-04-13 | Power transistor with low amplification factor change rate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320813899.3U CN219979571U (en) | 2023-04-13 | 2023-04-13 | Power transistor with low amplification factor change rate |
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| Publication Number | Publication Date |
|---|---|
| CN219979571U true CN219979571U (en) | 2023-11-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202320813899.3U Active CN219979571U (en) | 2023-04-13 | 2023-04-13 | Power transistor with low amplification factor change rate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116487413A (en) * | 2023-04-13 | 2023-07-25 | 锦州辽晶电子科技有限公司 | Power transistor with low amplification factor change rate and manufacturing method thereof |
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- 2023-04-13 CN CN202320813899.3U patent/CN219979571U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116487413A (en) * | 2023-04-13 | 2023-07-25 | 锦州辽晶电子科技有限公司 | Power transistor with low amplification factor change rate and manufacturing method thereof |
| CN116487413B (en) * | 2023-04-13 | 2024-04-12 | 锦州辽晶电子科技股份有限公司 | Power transistor with low amplification factor change rate and manufacturing method thereof |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 121000 No. 58, Songshan street, Taihe District, Jinzhou City, Liaoning Province Patentee after: Jinzhou Liaojing Electronic Technology Co.,Ltd. Address before: 121000 No. 58, Songshan street, Taihe District, Jinzhou City, Liaoning Province Patentee before: JINZHOU LIAOJING ELECTRONIC TECHNOLOGY CO.,LTD. |
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| CP01 | Change in the name or title of a patent holder |