CN212625614U

CN212625614U - Crystalline silicon solar cell

Info

Publication number: CN212625614U
Application number: CN202021157912.7U
Authority: CN
Inventors: 姚骞; 常青; 张家峰; 马列; 王秀鹏
Original assignee: Tongwei Solar Meishan Co Ltd
Current assignee: Tongwei Solar Meishan Co Ltd
Priority date: 2020-06-19
Filing date: 2020-06-19
Publication date: 2021-02-26
Anticipated expiration: 2030-06-19

Abstract

The utility model relates to a crystalline silicon solar cell. It includes: an N-type silicon wafer; a P-type doped layer configured on the top surface of the N-type silicon wafer; a silicon dioxide tunneling layer configured on the bottom surface of the N-type silicon wafer; and an N-type passivation layer is configured after the silicon dioxide protection layer is configured on the top surface of the P-type doped layer, the N-type passivation layer is a polysilicon passivation layer or a doped polysilicon passivation layer, and the N-type passivation layer is arranged on the bottom surface of the silicon dioxide tunneling layer. According to the utility model discloses, set up one deck silica protective layer on the top surface of silicon chip earlier before preparation N type passivation layer, phosphorus is avoided around plating to the top surface when preparing N type passivation layer, can guarantee that the PN junction of battery piece is not destroyed promptly, is difficult to produce the problem of battery short circuit or inefficacy. Wherein, the silicon dioxide protective layer formed by introducing the silicon source has a compact structure and can play an excellent protection role.

Description

Crystalline silicon solar cell

Technical Field

The utility model relates to an energy field especially relates to a crystalline silicon solar cell piece.

Background

With the increasing consumption of conventional fossil energy such as global coal, oil, natural gas and the like, the ecological environment is continuously deteriorated, and particularly, the sustainable development of the human society is seriously threatened due to the increasingly severe global climate change caused by the emission of greenhouse gases. Various countries in the world make respective energy development strategies to deal with the limitation of conventional fossil energy resources and the environmental problems caused by development and utilization. Solar energy has become one of the most important renewable energy sources by virtue of the characteristics of reliability, safety, universality, long service life, environmental protection and resource sufficiency, and is expected to become a main pillar of global power supply in the future.

In a new energy revolution process, the photovoltaic industry in China has grown into a strategic emerging industry with international competitive advantages. However, the development of the photovoltaic industry still faces many problems and challenges, and the conversion efficiency and reliability are the biggest technical obstacles restricting the development of the photovoltaic industry, while the cost control and the scale-up are economically restricted.

In recent years, various novel crystal silicon technologies have emerged. At present, the market mainly uses the PERC solar cell, the main production efficiency can exceed 22%, however, the improvement of the conversion efficiency of the PERC solar cell is more limited. The current novel passivation contact structure can reduce the battery conversion efficiency and improve the battery conversion efficiency to more than 23% through overlapping 2-3 procedures on the basis of the existing PERC technology. Passivation contact technology is becoming more and more popular with the market and various research institutes due to its strong compatibility with existing PERC technology.

The existing passivation contact technology for the crystalline silicon solar cell is to prepare an N-type doped polycrystalline silicon film on the back of N-type crystalline silicon, but phosphorus is plated around the front of the silicon wafer in the doping process, and a P-type thin layer and a PN junction on the front can be damaged due to the fact that the diffusion coefficient of the phosphorus is larger than that of boron, so that the solar cell is low in efficiency and even fails.

There is therefore a need to provide a crystalline silicon solar cell to at least partially solve the above problems.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a crystalline silicon solar cell, it sets up one deck silica protective layer on the top surface of silicon chip earlier before preparing N type passivation layer in the manufacturing process, avoids phosphorus when preparing N type passivation layer around plating to the top surface, can guarantee that the PN junction of battery piece is not destroyed promptly, is difficult to produce the problem of battery short circuit or inefficacy. Wherein, the silicon dioxide protective layer formed by introducing the silicon source has a compact structure and can play an excellent protection role.

And, the utility model discloses a higher microwave frequency prepares N type passivation layer, and under the high frequency electric field, reaction gas activation degree is stronger, and ion concentration is high, thereby can ionize out the deposition rate that more high energy electron and positive and negative ion increase the film, can reduce around plating to the probability on silicon chip top surface. Further, the utility model discloses still set up the mist that lets in ammonia and oxidation nitrogen before the step of this high frequency preparation, carry out the step that rich hydrogen plasma handled to the basal surface of N type silicon chip to make the basal surface passivation of N type silicon chip, reduce the damage of high frequency power to the battery piece.

According to the utility model discloses an aspect provides a crystalline silicon solar wafer, and crystalline silicon solar wafer includes:

an N-type silicon wafer;

a P-type doped layer configured on the top surface of the N-type silicon wafer;

a silicon dioxide tunneling layer configured on the bottom surface of the N-type silicon wafer;

and an N-type passivation layer is configured after the silicon dioxide protection layer is configured on the top surface of the P-type doped layer, the N-type passivation layer is a polysilicon passivation layer or a doped polysilicon passivation layer, and the N-type passivation layer is arranged on the bottom surface of the silicon dioxide tunneling layer.

In one embodiment, the N-type passivation layer is a whole layered structure prepared by using a microwave frequency of 60KHz or more.

In one embodiment, the N-type passivation layer is an integral layered structure prepared by using a microwave frequency of 80kHz-100kHz and at a temperature of 400 ℃ to 600 ℃ and a pressure of 1kPa to 13 kPa.

In one embodiment, the N-type passivation layer is a whole layered structure prepared after introducing a mixed gas of ammonia gas and dinitrogen oxide and performing hydrogen-rich plasma treatment on the bottom surface of the N-type silicon wafer.

In one embodiment, the solar cell further comprises an aluminum oxide passivation layer disposed on the top surface of the P-doped layer.

In one embodiment, the method further comprises forming an antireflective film on the top surface of the aluminum oxide passivation layer and on the bottom surface of the N-type passivation layer, the antireflective film being a silicon nitride antireflective film, a silicon oxynitride antireflective film, or a silicon carbide antireflective film.

In one embodiment, the silicon dioxide tunneling layer has a thickness of 0.5nm to 5 nm.

In one embodiment, the antireflective film has a thickness of 70nm to 200 nm.

According to the utility model provides a scheme sets up the silica protective layer that the one deck is fine and close on the top surface of silicon chip earlier before preparation N type passivation layer, avoids phosphorus when preparation N type passivation layer around plating to the top surface, can guarantee not destroyed in the PN junction of battery piece promptly, is difficult to produce the problem of battery short circuit or inefficacy. The silicon source is introduced into the surface of the silicon wafer, and a silicon dioxide protective layer formed by chain oxidation is compact in structure and can play an excellent protection role.

And, the utility model discloses a higher microwave frequency prepares N type passivation layer, and under the high frequency electric field, reaction gas activation degree is stronger, and ion concentration is high, thereby can ionize out the deposition rate that more high energy electron and positive and negative ion increase the film, reduces around plating to the probability on silicon chip top surface. Further, the utility model discloses still set up the mist that lets in ammonia and oxidation nitrogen before the step of this high frequency preparation, carry out the step that rich hydrogen plasma handled to the basal surface of N type silicon chip to make the basal surface passivation of N type silicon chip, reduce the damage of high frequency power to the battery piece.

In a word, the utility model discloses on current traditional TOPCon battery manufacturing process basis, through forming the one deck protective layer in the front, improve the process in order to reduce the degree of plating around of doping polycrystalline silicon simultaneously at back PECVD coating film process to can promote the yield and the efficiency of TOCPon battery by a wide margin.

Drawings

For a better understanding of the above and other objects, features, advantages and functions of the present invention, reference should be made to the preferred embodiments illustrated in the accompanying drawings. Like reference numerals in the drawings refer to like parts. It will be appreciated by persons skilled in the art that the drawings are intended to illustrate preferred embodiments of the invention without any limiting effect on the scope of the invention, and that the various components in the drawings are not to scale.

Fig. 1 is a flow chart of a manufacturing method according to a preferred embodiment of the present invention;

fig. 2 is a top view of an in-process or manufactured crystalline silicon solar cell according to a preferred embodiment of the present invention;

fig. 3 is a schematic view of the cross-sectional view of fig. 2 taken along line a-a after 90 ° clockwise rotation, fig. 3 showing the structure of a crystalline silicon solar cell during processing and before the fabrication of an N-type passivation layer;

fig. 4 is a schematic view after a 90 ° clockwise rotation of a sectional view taken along line a-a of fig. 2, and fig. 4 shows a structure of a completed crystalline silicon solar cell.

Detailed Description

Referring now to the drawings, specific embodiments of the present invention will be described in detail. What has been described herein is merely a preferred embodiment in accordance with the present invention, and those skilled in the art will appreciate that other ways of implementing the present invention on the basis of the preferred embodiment will also fall within the scope of the present invention.

The utility model provides a crystalline silicon solar cell. Fig. 1 shows a flow chart of a method for manufacturing a crystalline silicon solar cell, and fig. 2 to 4 are schematic diagrams of an in-process or completed crystalline silicon solar cell.

Fig. 1 shows a schematic view of a method for manufacturing a crystalline silicon solar cell according to a preferred embodiment of the present invention, the method comprising steps S1 to S6, S1 to S6 occurring in sequential order from S1 to S6.

S1 is a preceding processing step, which includes, for example, a step of providing an N-type silicon wafer, and the step of providing an N-type silicon wafer further includes, for example, processes of cleaning and texturing the N-type silicon wafer to remove metal ions and a cutting damage layer on the surface of the N-type silicon wafer.

S2 is a step of preparing a P-type doped layer. The method comprises the following steps: boron diffusion is performed on the top surface of the N-type silicon wafer to create a P-type doped layer. The boron diffusion step is realized by a thermal diffusion or ion implantation method, so that the surface sheet resistance of the P-type doped layer is 40 omega/□ -300 omega/□.

S3 is a step of chain oxidation, which comprises: and introducing a silicon source on the top surface of the P-type doped layer to perform chain oxidation so as to generate a silicon dioxide protective layer. The silicon source includes, for example, at least one of sodium silicate, methyl silicate, polysiloxane, and silicon alkoxide. Preferably, the amount and time of passing the silicon source may be controlled in step S3 so that the thickness of the resultant silicon dioxide protective layer is 3nm to 1 μm.

S4 is an intermediate processing step, and S4 may include, for example, steps S41 and S42 (not shown in the figure).

S41 may be, for example, an etching process for the edge and the bottom surface of an N-type silicon wafer, and the etching step may be specifically realized by a chemical wet and/or dry etching method.

S42 may be, for example, a step of providing a silicon dioxide tunneling layer on a bottom surface of an N-type silicon wafer, and preferably, the silicon dioxide tunneling layer may be prepared using at least one of thermal oxidation, ozone, wet oxidation, and ALD methods such that the thickness of the silicon dioxide tunneling layer is 0.5nm to 5 nm.

S5 is a step of preparing an N-type passivation layer, which may include steps S51 and S52 (not shown in the figure).

S51 is, for example, a mixed gas of ammonia gas and dinitrogen oxide is introduced to perform a hydrogen-rich plasma treatment on the bottom surface of the N-type silicon wafer, thereby passivating the bottom surface of the N-type silicon wafer.

S52 occurs after S51, S52 specifically includes: and introducing a phosphorus source on the bottom surface of the silicon dioxide tunneling layer to generate an N-type passivation layer, wherein the N-type passivation layer is a polysilicon passivation layer or a doped polysilicon passivation layer. Preferably, in step S52, the N-type passivation layer may be prepared using a microwave frequency of 60KHz or more. More preferably, in step S52, a microwave frequency of 80kHz to 100kHz may be employed, and the temperature in the manufacturing furnace of the manufacturing furnace accommodating the solar cell sheet is controlled to 400 ℃ to 600 ℃, and the pressure in the manufacturing furnace is controlled to 1kPa to 13 kPa.

The higher microwave frequency used in step S52 to prepare the N-type passivation layer as described above can produce a better crystalline silicon solar cell, because the reaction gas is activated more strongly and the ion concentration is higher under the high frequency electric field, so that more energetic electrons and positive and negative ions can be ionized to increase the deposition rate of the thin film, reduce the probability of the top surface being coated with the thin film, and reduce the probability of damaging the PN junction on the top surface of the cell. And the step of S51 is set, so that excessive H atoms on the top surface of the silicon wafer can passivate the surface of the silicon wafer, and the damage of the high-frequency power bombardment on the cell is reduced.

And, as mentioned above, step S5 occurs after step S3, that is, the N-type passivation layer is prepared after the silicon dioxide protective layer is generated, so as to avoid the problem that phosphorus is plated around the top surface when the N-type passivation layer is prepared, that is, the PN junction of the battery piece is not damaged, and the battery is not easy to short circuit or fail. Compared with dielectric films such as silicon carbide and silicon nitride, the silicon dioxide protective layer formed by introducing silicon source chain oxidation is more compact in structure, can play an excellent protection role, and can be conveniently removed in an etching mode after a passivation film is formed.

That is, the present embodiment provides two designs for reducing phosphorus wrap-plating to the front side of the silicon wafer when forming the polysilicon passivation film: arranging a silicon dioxide protective layer on the top surface of the silicon wafer before arranging the N-type passivation layer; and a high-frequency mode is adopted during the preparation of the N-type passivation layer.

S6 is a subsequent processing step. This step may include steps (not shown in the figure) such as S61 to S65.

S61 may be, for example, a step of removing a silicon dioxide protective layer.

S62 may be, for example, an etching process of the edge of an N-type silicon wafer and the top surface of a P-type doped layer.

S63 may be, for example, a step of providing an aluminum oxide passivation film on the top surface of the P-type doped layer.

S64 may be, for example, a step of providing an antireflective film on a top surface of the aluminum oxide passivation film and a bottom surface of the N-type passivation film, and the antireflective film may be a silicon nitride antireflective film, a silicon oxynitride antireflective film, a silicon carbide antireflective film, a silicon dioxide antireflective film, or a stack of these antireflective films. Preferably, the antireflective film may be provided by a PECVD method, and the thickness of the silicon nitride antireflective film, the silicon oxynitride antireflective film, or the silicon carbide antireflective film may be, for example, 70nm to 200 nm.

S65 can be, for example, a step of printing a gate line, or a step of printing an electrode. In this step, the main and sub-grid lines may be printed with one or more of silver, gold, copper, aluminum, nickel on the top and bottom surfaces of the base sheet, the grid lines shown in fig. 3 being sub-grid lines.

Fig. 2 shows a schematic top surface view of a crystalline silicon solar cell sheet 1 made or being prepared according to the above method, wherein top side main grid lines 8 and sub-grid lines 81 of the crystalline silicon solar cell sheet 1 are shown. The cross-sectional views of fig. 3 and 4 taken along line a-a are schematic after being rotated 90 ° clockwise.

Fig. 3 shows the structure of a crystalline silicon solar cell piece 1 in the process and before the preparation of an N-type passivation layer, and since only the steps of preparing a P-type doping layer and a silicon dioxide protection layer are completed at this time and an N-type passivation layer is not prepared yet, only an N-type silicon wafer 2 and a P-type doping layer 3 disposed on the top surface of the N-type silicon wafer 2 and a silicon dioxide protection layer 31 disposed on the top surface of the P-type doping layer 3 are shown in fig. 3. The preparation of the N-type passivation layer in the presence of the silicon dioxide protection layer 31 can avoid phosphorus from being plated around the top surface of the battery piece to damage PN junctions and other structures at the top surface.

Fig. 4 shows the prepared crystalline silicon solar cell 1, in which the silicon dioxide protective layer 31 is not present in the prepared crystalline silicon solar cell 1, because the silicon dioxide protective layer 31 is washed away after the preparation of the N-type passivation layer 7.

Referring to fig. 4, a crystalline silicon solar cell sheet 1 includes a base sheet and gate lines disposed on top and bottom surfaces of the base sheet. Referring to fig. 4, the base sheet includes an N-type silicon wafer 2, an alumina passivation layer 4, a silica tunneling layer 6 pre-configured before configuring the structural layer of the top surface of the N-type silicon wafer 2, and an N-type passivation layer 7 pre-configured before configuring the structural layer of the top surface of the N-type silicon wafer 2. The grid lines further comprise secondary grid lines and main grid lines, and the secondary grid lines and the main grid lines can be made of one or more of metals such as silver, gold, copper, aluminum, nickel and the like. Shown in fig. 2 are top side bus bars 8 on the top side of the N-type silicon die 2 and bottom side bus bars 9 on the bottom side of the N-type silicon die 2.

The thickness of the N-type silicon wafer 2 is 100-220 μm, the top surface of the N-type silicon wafer 2 is a P-type doped layer 3, and a structure similar to a PN junction is formed between the N-type silicon wafer 2 and the P-type doped layer 3. An alumina passivation layer 4 is disposed on the P-doped layer 3 and the alumina passivation layer 4 has a thickness of approximately 1nm-20 nm. The silicon dioxide tunneling layer 6 is disposed on the bottom surface of the N-type silicon wafer 2 and has a thickness of approximately 0.5nm to 5 nm.

The N-type passivation layer 7 is arranged on the bottom surface of the silicon dioxide tunneling layer 6, the N-type passivation layer 7 is a phosphorus-doped passivation layer, and the silicon dioxide tunneling layer 6 can be protected and a passivation effect can be provided for the crystalline silicon solar cell 1. The thickness of the N-type polysilicon passivation layer 7 may be, for example, 20nm to 300 nm.

Preferably, a silicon nitride anti-reflective film 5 (or a silicon oxynitride anti-reflective film, a silicon carbide anti-reflective film, a silicon oxide anti-reflective film or a stack of these films) may also be disposed on the top surface of the aluminum oxide passivation layer 4 and the bottom surface of the N-type passivation layer 7. For example, it may be 70nm to 200 nm.

According to the utility model provides a scheme sets up one deck silica protective layer on the top surface of silicon chip earlier before preparation N type passivation layer, avoids phosphorus when preparation N type passivation layer around plating to the top surface, can guarantee that the PN junction of battery piece is not destroyed promptly, is difficult to produce the problem of battery short circuit or inefficacy. The property of the silicon dioxide enables the structure of the silicon dioxide protective layer to be compact, and the silicon dioxide protective layer can play a better protective role.

And, the utility model discloses a higher microwave frequency prepares N type passivation layer, and under the high frequency electric field, reaction gas activation degree is stronger, and ion concentration is high, thereby can ionize out the deposition rate that more high energy electron and positive and negative ion increase the film, further reduces around plating to the probability on silicon chip top surface. Further, the utility model discloses still set up the mist that lets in ammonia and oxidation nitrogen before the step of this high frequency preparation, carry out the step that rich hydrogen plasma handled to the basal surface of N type silicon chip to make the basal surface passivation of N type silicon chip, reduce the damage of high frequency power to the battery piece.

The foregoing description of various embodiments of the invention is provided to one of ordinary skill in the relevant art for the purpose of illustration. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. As above, various alternatives and modifications of the present invention will be apparent to those skilled in the art of the above teachings. Thus, while some alternative embodiments are specifically described, other embodiments will be apparent to, or relatively easily developed by, those of ordinary skill in the art. The present invention is intended to embrace all such alternatives, modifications and variances of the present invention described herein, as well as other embodiments that fall within the spirit and scope of the present invention as described above.

Claims

1. A crystalline silicon solar cell is characterized by comprising:

an N-type silicon wafer;

a P-type doped layer configured on the top surface of the N-type silicon wafer;

2. The crystalline silicon solar cell of claim 1, wherein the N-type passivation layer is an integral layered structure prepared by using a microwave frequency of 60KHz or higher.

3. The crystalline silicon solar cell of claim 1, wherein the N-type passivation layer is an integral layered structure prepared using a microwave frequency of 80kHz to 100kHz and produced in a preparation furnace at a temperature of 400 ℃ to 600 ℃ and a pressure of 1kPa to 13 kPa.

4. The crystalline silicon solar cell as defined in claim 2 or 3, wherein the N-type passivation layer is a whole layered structure prepared after introducing a mixed gas of ammonia gas and dinitrogen oxide and performing hydrogen-rich plasma treatment on the bottom surface of the N-type silicon wafer.

5. The crystalline silicon solar cell of claim 1, further comprising an aluminum oxide passivation layer disposed on the top surface of the P-type doped layer.

6. The crystalline silicon solar cell of claim 5, further comprising an antireflective film on a top surface of the aluminum oxide passivation layer and on a bottom surface of the N-type passivation layer, the antireflective film comprising at least one of a silicon nitride bulk film structure, a silicon oxynitride bulk film structure, a silicon carbide bulk film structure, a silicon oxide bulk film structure.

7. The crystalline silicon solar cell as defined in claim 1 wherein the silicon dioxide tunneling layer has a thickness of 0.5nm to 3 nm.