CN110911504A - Method for manufacturing crystalline silicon solar cell and crystalline silicon solar cell - Google Patents

Method for manufacturing crystalline silicon solar cell and crystalline silicon solar cell Download PDF

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Publication number
CN110911504A
CN110911504A CN201911319956.7A CN201911319956A CN110911504A CN 110911504 A CN110911504 A CN 110911504A CN 201911319956 A CN201911319956 A CN 201911319956A CN 110911504 A CN110911504 A CN 110911504A
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layer
passivation layer
silicon
silicon wafer
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常青
姚骞
张家峰
马列
王秀鹏
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Tongwei Solar Meishan Co Ltd
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Tongwei Solar Meishan Co Ltd
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    • H01L31/02168
    • H01L31/02363
    • H01L31/074
    • H01L31/1804
    • H01L31/1868
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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  • Sustainable Development (AREA)
  • Engineering & Computer Science (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The invention relates to a method for manufacturing a crystalline silicon solar cell and the crystalline silicon solar cell. The method comprises the steps of setting a substrate piece and applying grid lines on the top surface and the bottom surface of the substrate piece, wherein the solar cell piece comprises an N-type silicon wafer, an N-type polycrystalline silicon passivation layer located on the bottom surface of the N-type silicon wafer and a P-type doping layer located on the top surface of the N-type silicon wafer and generated in the boron doping step, and the N-type polycrystalline silicon passivation layer is prepared before boron doping is carried out on the top surface of the N-type silicon wafer when the crystalline silicon solar cell piece is set. According to the invention, the N-type polycrystalline silicon passivation layer is generated in the manufacturing process and then boron doping is carried out on the surface of the silicon wafer, so that a PN junction is not formed on the top surface of the silicon wafer when the N-type polycrystalline silicon passivation layer is generated, and the performance of the solar cell is not influenced even if phosphorus is wound and plated on the top surface.

Description

Method for manufacturing crystalline silicon solar cell and crystalline silicon solar cell
Technical Field
The invention relates to the field of energy, in particular to a crystalline silicon solar cell and a manufacturing method thereof.
Background
With the increasing consumption of conventional fossil energy such as global coal, oil, natural gas and the like, the ecological environment is continuously deteriorated, and particularly, the sustainable development of the human society is seriously threatened due to the increasingly severe global climate change caused by the emission of greenhouse gases. Various countries in the world make respective energy development strategies to deal with the limitation of conventional fossil energy resources and the environmental problems caused by development and utilization. Solar energy has become one of the most important renewable energy sources by virtue of the characteristics of reliability, safety, universality, long service life, environmental protection and resource sufficiency, and is expected to become a main pillar of global power supply in the future.
In a new energy revolution process, the photovoltaic industry in China has grown into a strategic emerging industry with international competitive advantages. However, the development of the photovoltaic industry still faces many problems and challenges, and the conversion efficiency and reliability are the biggest technical obstacles restricting the development of the photovoltaic industry, while the cost control and the scale-up are economically restricted.
In recent years, various novel crystal silicon technologies have emerged. At present, the market mainly uses the PERC solar cell, the main production efficiency can exceed 22%, however, the improvement of the conversion efficiency of the PERC solar cell is more limited. The current novel passivation contact structure can reduce the battery conversion efficiency and improve the battery conversion efficiency to more than 23% through overlapping 2-3 procedures on the basis of the existing PERC technology. Passivation contact technology is becoming more and more popular with the market and various research institutes due to its strong compatibility with existing PERC technology.
The existing passivation contact technology for the crystalline silicon solar cell is to prepare an N-type doped polycrystalline silicon film on the back of N-type crystalline silicon, but phosphorus is plated around the front of the silicon wafer in the doping process, and a P-type thin layer and a PN junction on the front can be damaged due to the fact that the diffusion coefficient of the phosphorus is larger than that of boron, so that the solar cell is low in efficiency and even fails.
In order to solve the problems, a layer of protective film such as silicon nitride, silicon carbide and the like is plated on the front emitter, and the protective film on the front is washed off after the back N-type doped polycrystalline silicon is plated, so that the damage of phosphorus to a front PN junction in the process can be effectively avoided, but extra coating and washing processes are required, the manufacturing cost of the battery is increased, and the development of a passivation contact battery technology is not facilitated.
There is therefore a need to provide a method of manufacturing a crystalline silicon solar cell and a crystalline silicon solar cell to at least partially solve the above problems.
Disclosure of Invention
The invention aims to provide a method for manufacturing a crystalline silicon solar cell and the crystalline silicon solar cell, wherein an N-type polycrystalline silicon or doped silicon carbide passivation layer is firstly generated in the manufacturing process, then boron doping is carried out on the surface of a silicon wafer, so that a PN junction is not formed on the top surface of the silicon wafer when the N-type passivation layer is generated, and the performance of the solar cell cannot be influenced even if phosphorus is wound and plated on the top surface.
In addition, the invention also omits the step of additionally arranging the protective layer, thereby omitting the redundant working procedure and reducing the cost. The crystalline silicon solar cell provided by the invention has a simpler structure and is easy to produce and manufacture, and the manufacturing method provided by the invention has a simple process route and is easy to realize.
According to one aspect of the invention, a method for manufacturing a crystalline silicon solar cell is provided, the method comprises the steps of arranging a substrate and applying grid lines on the top surface and the bottom surface of the substrate, the solar cell comprises an N-type silicon wafer, an N-type passivation layer and a P-type doping layer, the N-type passivation layer is located on the bottom surface of the N-type silicon wafer, the P-type doping layer is generated by a boron doping step and located on the top surface of the N-type silicon wafer, the N-type passivation layer is an N-type polycrystalline silicon passivation layer or a doped silicon carbide passivation layer, and the N-type passivation layer is prepared before boron doping is carried out on the top surface of the N-type silicon wafer when the crystalline silicon solar cell is.
In one embodiment, the method comprises the following steps in sequence:
setting an N-type silicon wafer;
arranging a silicon dioxide tunneling layer on the bottom surface of the N-type silicon wafer;
arranging an N-type passivation layer on the bottom surface of the silicon dioxide tunneling layer, wherein the N-type passivation layer is a polycrystalline silicon passivation layer or a doped silicon carbide passivation layer;
etching the edge and the top surface of the N-type silicon wafer to remove phosphorus on the N-type silicon wafer;
and carrying out boron doping or ion implantation on the top surface of the N-type silicon wafer so as to form a P-type doped layer on the top surface of the N-type silicon wafer.
In one embodiment, the method further comprises the following step after the step of boron doping the top surface of the N-type silicon wafer: and etching the edge of the N-type silicon wafer and the bottom surface of the N-type passivation layer to remove boron on the N-type silicon wafer.
In one embodiment, the steps of etching the edge and the top surface of the N-type silicon wafer and etching the edge of the N-type silicon wafer and the bottom surface of the N-type passivation layer are performed by a chemical wet and/or dry etching method.
In one embodiment, the method further comprises: and after etching the bottom surface of the N-type polycrystalline silicon passivation layer to remove boron, arranging an aluminum oxide passivation film on the top surface of the P-type doped layer.
In one embodiment, the method further comprises the following step after the step of providing an aluminum oxide passivation film: and arranging a silicon nitride antireflection film, a silicon oxynitride antireflection film or a silicon carbide antireflection film on the top surface of the aluminum oxide passivation film and the bottom surface of the N-type passivation layer.
In one embodiment, the silicon nitride anti-reflection film, the silicon oxynitride anti-reflection film or the silicon carbide anti-reflection film is provided by a PECVD method, and the thickness of the silicon nitride anti-reflection film, the silicon oxynitride anti-reflection film or the silicon carbide anti-reflection film is formed to be 70nm-200 nm.
In one embodiment, the tunneling layer is a silicon dioxide tunneling layer, and the step of disposing the silicon dioxide tunneling layer includes: the silicon dioxide tunneling layer is prepared by at least one of thermal oxidation, ozone, wet oxidation and ALD method, so that the thickness of the silicon dioxide tunneling layer is 0.5nm-3 nm.
In one embodiment, the step of disposing the N-type passivation layer includes: and preparing the N-type polycrystalline silicon passivation layer by using at least one of an LPCVD (low pressure chemical vapor deposition) method, a PECVD (plasma enhanced chemical vapor deposition) method, an ion implantation method and an ALD (atomic layer deposition) method, so that the thickness of the N-type polycrystalline silicon passivation layer is 20nm-300 nm.
In one embodiment, the boron doping step is implemented by thermal diffusion or ion implantation, so that the surface sheet resistance of the P-type doped layer is 40 Ω/□ -300 Ω/□.
In one embodiment, there is no step of disposing a protective layer on the top surface of the N-type silicon wafer prior to disposing the N-type passivation layer.
According to another aspect of the present invention, there is provided a crystalline silicon solar cell manufactured by the method according to any one of the above aspects, the crystalline silicon solar cell comprising:
an N-type silicon wafer;
a tunneling layer pre-configured prior to configuring a structural layer of a top surface of the N-type silicon wafer, the tunneling layer disposed on a bottom surface of the N-type silicon wafer;
an N-type passivation layer which is pre-configured before a structural layer of the top surface of the N-type silicon wafer is configured, wherein the N-type passivation layer is a polycrystalline silicon passivation layer or a doped silicon carbide passivation layer, and is arranged on the bottom surface of the tunneling layer;
preparing a P-type doping layer configured after the N-type passivation layer is prepared, wherein the P-type doping layer is arranged on the top surface of the N-type silicon wafer;
an aluminum oxide passivation layer disposed on a top surface of the P-doped layer.
In one embodiment, further comprising a silicon nitride antireflective film, a silicon oxynitride antireflective film, or a silicon carbide antireflective film on the top surface of the aluminum oxide passivation layer and on the bottom surface of the N-type passivation layer.
In one embodiment, the tunneling layer is a silica tunneling layer, and the thickness of the silica tunneling layer is 0.5nm to 3 nm.
In one embodiment, the thickness of the N-type passivation layer is 20nm to 300 nm.
In one embodiment, the silicon nitride antireflective film has a thickness of 70nm to 200 nm.
According to the invention, the N-type passivation layer is firstly generated in the process of manufacturing the solar cell, and then boron doping is carried out on the surface of the silicon wafer, so that a PN junction is not formed on the top surface of the silicon wafer when the N-type passivation layer is generated, and the performance of the solar cell is not influenced even if phosphorus is plated around the top surface. In addition, the invention also omits the step of additionally arranging the protective layer, thereby omitting the redundant working procedure and reducing the cost.
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For a better understanding of the above and other objects, features, advantages and functions of the present invention, reference should be made to the preferred embodiments illustrated in the accompanying drawings. Like reference numerals in the drawings refer to like parts. It will be appreciated by persons skilled in the art that the drawings are intended to illustrate preferred embodiments of the invention without any limiting effect on the scope of the invention, and that the various components in the drawings are not drawn to scale.
FIG. 1 is a flow chart of a method of manufacture according to a preferred embodiment of the present invention;
fig. 2 is a top view of a crystalline silicon solar cell according to a preferred embodiment of the present invention;
fig. 3 is a schematic view of the cross-sectional view of fig. 1 taken along line a-a after being rotated 90 ° clockwise.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. What has been described herein is merely a preferred embodiment in accordance with the present invention and other ways of practicing the invention will occur to those skilled in the art and are within the scope of the invention.
The invention provides a method for manufacturing a crystalline silicon solar cell and the crystalline silicon solar cell. Fig. 1 shows a flow chart of a method for manufacturing a crystalline silicon solar cell, and fig. 2 and 3 are schematic views of the crystalline silicon solar cell.
Fig. 1 shows a schematic view of a method for manufacturing a crystalline silicon solar cell piece according to a preferred embodiment of the present invention, which includes steps S1 to S6 in sequence.
S1 is a preamble processing step. Which includes sub-steps (not shown) such as S11 and S12.
S11 is, for example, a step of providing an N-type silicon wafer, which includes a process of cleaning and texturing the N-type silicon wafer to remove metal ions and a dicing damage layer on the surface of the N-type silicon wafer.
S12 is, for example, a step of providing a silicon dioxide tunneling layer on the bottom surface of an N-type silicon wafer. This step may be achieved, for example, by at least one of thermal oxidation, ozone, wet oxidation, and ALD methods, and the silicon dioxide tunneling layer may be generated to have a thickness of 0.5nm to 3 nm.
S2 is a step of disposing an N-type polysilicon passivation layer (or a doped silicon carbide passivation layer) on the bottom surface of the silicon dioxide tunneling layer. This step may be achieved by at least one of an LPCVD method, a PECVD method, an ion implantation method, an ALD method, for example, and the thickness of the N-type passivation layer may be formed to be 20nm to 300 nm. During this step, some phosphorus will be around-plated to the edges and top surface of the N-type silicon wafer.
S3 is a step of etching the edge and the top surface of the N-type silicon wafer, which is capable of removing the phosphorus around the edge and the top surface of the N-type silicon wafer plated in step S2. The etching can be effected, for example, by chemical wet and/or dry etching methods.
S4 is a step of doping boron on the top surface of the N-type silicon wafer, wherein a P-type doped layer can be formed on the top surface of the N-type silicon wafer by doping boron on the top surface of the N-type silicon wafer, and a structure similar to a PN junction can be formed between the P-type doped layer and the N-type silicon wafer. The boron doping step is realized by a thermal diffusion or ion implantation method, so that the surface sheet resistance of the P-type doping layer is 40 omega/□ -300 omega/□. Part of the boron will be plated around the edge of the N-type silicon wafer and the bottom surface of the N-type polysilicon passivation layer during this step.
S5 is a step of etching the edge of the N-type silicon wafer and the bottom surface of the N-type passivation layer, which is capable of removing boron around the edge of the N-type silicon wafer and the bottom surface of the N-type passivation layer. This step can be realized, for example, by chemical wet and/or dry etching methods.
The P-type doped layer and the PN junction are generally damaged by phosphorus which is plated around the top surface of the N-type silicon wafer when the N-type passivation layer is prepared, but the P-type doped surface and the PN junction are not formed on the top surface of the N-type silicon wafer when the N-type passivation layer is generated before the boron doping step on the top surface of the N-type silicon wafer in the step of arranging the N-type passivation layer, so that the performance of the solar cell cannot be influenced even if the phosphorus is plated around the top surface of the N-type silicon wafer. In addition, the invention also omits the step of additionally arranging the protective layer, thereby omitting the redundant working procedure and reducing the cost.
S6 is a subsequent processing step. This step may include sub-steps (not shown) such as S61 through S62.
S61 may be, for example, a step of providing a silicon nitride antireflective film, a silicon oxynitride antireflective film, or a silicon carbide antireflective film on the top surface of the aluminum oxide passivation film and the bottom surface of the N-type passivation layer, and preferably, the thickness of the silicon nitride antireflective film, the silicon oxynitride antireflective film, or the silicon carbide antireflective film may be, for example, 70nm to 200 nm.
S62 can be, for example, a step of printing a gate line, or a step of printing an electrode. In this step, the main and sub-grid lines may be printed with one or more of silver, gold, copper, aluminum, nickel on the top and bottom surfaces of the base sheet, the grid lines shown in fig. 3 being sub-grid lines.
Fig. 2 and 3 show schematic views of a crystalline silicon solar cell sheet 1 manufactured according to the above method, and the crystalline silicon solar cell sheet 1 comprises a substrate sheet and grid lines arranged on the top surface and the bottom surface of the substrate sheet. Referring to fig. 3, the substrate sheet includes an N-type silicon wafer 2, an alumina passivation layer 4, a silica tunneling layer 6 pre-configured before configuring the structural layer of the top surface of the N-type silicon wafer 2, and an N-type passivation layer 7 pre-configured before configuring the structural layer of the top surface of the N-type silicon wafer 2. The grid lines further comprise secondary grid lines and main grid lines, and the secondary grid lines and the main grid lines can be made of one or more of metals such as silver, gold, copper, aluminum, nickel and the like. Shown in fig. 2 are top side finger lines 8 on the top side of the N-type silicon die 2 and bottom side finger lines 9 on the bottom side of the N-type silicon die 2.
The thickness of the N-type silicon wafer 2 is 100-220 microns, the top surface of the N-type silicon wafer 2 is a P-type doping layer 3, the P-type doping layer is a structural layer configured after an N-type passivation layer 7 is prepared, and a structure similar to a PN junction is formed between the N-type silicon wafer 2 and the P-type doping layer 3. An alumina passivation layer 4 is disposed on the P-doped layer 3 and the alumina passivation layer 4 has a thickness of approximately 1nm-20 nm. The silicon dioxide tunneling layer 6 is disposed on the bottom surface of the N-type silicon wafer 2 and has a thickness of approximately 0.5nm to 3 nm.
The N-type passivation layer 7 is arranged on the bottom surface of the silicon dioxide tunneling layer 6, the N-type passivation layer 7 is a phosphorus-doped passivation layer, and the silicon dioxide tunneling layer 6 can be protected and a passivation effect can be provided for the crystalline silicon solar cell 1. The thickness of the N-type polysilicon passivation layer 7 may be, for example, 20nm to 300 nm.
Preferably, a silicon nitride anti-reflective film 5 (or a silicon oxynitride anti-reflective film, a silicon carbide anti-reflective film) may also be disposed on the top surface of the aluminum oxide passivation layer 4 and the bottom surface of the N-type passivation layer 7. The thickness of the silicon nitride antireflective film 5 may be, for example, 70nm to 200 nm.
The invention provides a method for manufacturing a crystalline silicon solar cell and the crystalline silicon solar cell, wherein an N-type passivation layer is firstly generated in the manufacturing process, then boron doping is carried out on the surface of a silicon wafer, so that a PN junction is not formed on the top surface of the silicon wafer when the N-type passivation layer is generated, and the performance of the solar cell cannot be influenced even if phosphorus is wound and plated on the top surface.
In addition, the invention also omits the step of additionally arranging the protective layer, thereby omitting the redundant working procedure and reducing the cost. The crystalline silicon solar cell provided by the invention has a simpler structure and is easy to produce and manufacture, and the manufacturing method provided by the invention has a simple process route and is easy to realize.
The foregoing description of various embodiments of the invention is provided for the purpose of illustration to one of ordinary skill in the relevant art. It is not intended that the invention be limited to a single disclosed embodiment. As mentioned above, many alternatives and modifications of the present invention will be apparent to those skilled in the art of the above teachings. Thus, while some alternative embodiments are specifically described, other embodiments will be apparent to, or relatively easily developed by, those of ordinary skill in the art. The present invention is intended to embrace all such alternatives, modifications and variances of the present invention described herein, as well as other embodiments that fall within the spirit and scope of the present invention as described above.
Reference numerals:
crystalline silicon solar cell 1
N-type silicon wafer 2
P-type doped layer 3
Aluminium oxide passivation layer 4
Silicon nitride anti-reflective film 5
Silicon dioxide tunneling layer 6
N-type passivation layer 7
Top side secondary grid line 8
The bottom side finger 9.

Claims (16)

1. A method for manufacturing a crystalline silicon solar cell comprises the steps of setting a substrate and applying grid lines on the top surface and the bottom surface of the substrate, wherein the solar cell comprises an N-type silicon wafer, an N-type passivation layer positioned on the bottom surface of the N-type silicon wafer and a P-type doping layer generated by a boron doping step and positioned on the top surface of the N-type silicon wafer, and the N-type passivation layer is an N-type polycrystalline silicon passivation layer or a doped silicon carbide passivation layer.
2. The method according to claim 1, characterized in that it comprises the following steps in sequence:
setting an N-type silicon wafer;
arranging a tunneling layer on the bottom surface of the N-type silicon wafer;
arranging an N-type passivation layer on the bottom surface of the silicon dioxide tunneling layer, wherein the N-type passivation layer is a polycrystalline silicon passivation layer or a doped silicon carbide passivation layer;
etching the edge and the top surface of the N-type silicon wafer to remove phosphorus on the N-type silicon wafer;
and carrying out boron doping or ion implantation on the top surface of the N-type silicon wafer so as to form a P-type doped layer on the top surface of the N-type silicon wafer.
3. The method of claim 2 further comprising the step of, after the step of boron doping the top surface of the N-type silicon wafer: and etching the edge of the N-type silicon wafer and the bottom surface of the N-type polycrystalline silicon passivation layer to remove boron on the N-type silicon wafer.
4. The method according to claim 3, wherein the steps of etching the edge and the top surface of the N-type silicon wafer and etching the edge of the N-type silicon wafer and the bottom surface of the N-type polysilicon passivation layer are performed by a chemical wet and/or dry etching method.
5. The method of claim 2, further comprising: and after etching the bottom surface of the N-type polycrystalline silicon passivation layer to remove boron, arranging an aluminum oxide passivation film on the top surface of the P-type doped layer.
6. The method of claim 5, further comprising, after the step of disposing an aluminum oxide passivation film, the steps of: and arranging a silicon nitride antireflection film, a silicon oxynitride antireflection film or a silicon carbide antireflection film on the top surface of the aluminum oxide passivation film and the bottom surface of the N-type passivation layer.
7. The method according to claim 6, wherein the silicon nitride anti-reflection film, the silicon oxynitride anti-reflection film or the silicon carbide anti-reflection film is provided by a PECVD method and is formed to have a thickness of 70nm to 200 nm.
8. The method of claim 2, wherein the tunneling layer is a silicon dioxide tunneling layer, and wherein disposing the silicon dioxide tunneling layer comprises: the silicon dioxide tunneling layer is prepared by at least one of thermal oxidation, ozone, wet oxidation and ALD method, so that the thickness of the silicon dioxide tunneling layer is 0.5nm-3 nm.
9. The method of claim 2, wherein the step of disposing the N-type passivation layer comprises: the N-type passivation layer is prepared by at least one of an LPCVD method, a PECVD method, an ion implantation method and an ALD method, so that the thickness of the N-type passivation layer is 20nm-300 nm.
10. The method of claim 2, wherein the boron doping step is performed by thermal diffusion or ion implantation, so that the surface sheet resistance of the P-type doped layer is 40 Ω/□ -300 Ω/□.
11. The method of claim 2 wherein there is no step of disposing a protective layer on the top surface of the N-type silicon wafer prior to disposing the N-type passivation layer.
12. A crystalline silicon solar cell fabricated according to the method of any one of claims 1-11, characterized in that it comprises:
an N-type silicon wafer;
a tunneling layer pre-configured prior to configuring a structural layer of a top surface of the N-type silicon wafer, the tunneling layer disposed on a bottom surface of the N-type silicon wafer;
an N-type passivation layer which is pre-configured before a structural layer of the top surface of the N-type silicon wafer is configured, wherein the N-type passivation layer is a polycrystalline silicon passivation layer or a doped silicon carbide passivation layer, and is arranged on the bottom surface of the tunneling layer;
preparing a P-type doping layer configured after the N-type passivation layer is prepared, wherein the P-type doping layer is arranged on the top surface of the N-type silicon wafer;
an aluminum oxide passivation layer disposed on a top surface of the P-doped layer.
13. The crystalline silicon solar cell of claim 12, further comprising a silicon nitride antireflective film, a silicon oxynitride antireflective film, or a silicon carbide antireflective film on a top surface of the aluminum oxide passivation layer and on a bottom surface of the N-type passivation layer.
14. The crystalline silicon solar cell of claim 12, wherein the tunneling layer is a silica tunneling layer having a thickness of 0.5nm to 3 nm.
15. The crystalline silicon solar cell of claim 12, wherein the thickness of the N-type passivation layer is 20nm to 300 nm.
16. The crystalline silicon solar cell of claim 13, wherein the silicon nitride antireflective film has a thickness of 70nm to 200 nm.
CN201911319956.7A 2019-12-19 2019-12-19 Method for manufacturing crystalline silicon solar cell and crystalline silicon solar cell Pending CN110911504A (en)

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