CN111640823B - N-type passivated contact battery and preparation method thereof - Google Patents
N-type passivated contact battery and preparation method thereof Download PDFInfo
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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Abstract
The invention discloses a preparation method of an n-type passivated contact cell, which comprises the steps of preparing a silicon dioxide layer on the front surface of a silicon wafer after preparing a front emitter as a front passivation layer, polishing a mask layer and removing a mask layer in a phosphorus-doped polycrystalline silicon step of winding plating; carrying out edge isolation and polishing on the back of the silicon wafer by using an alkaline solution to form a smooth polished surface on the back of the silicon wafer; and using the back silicon nitride as a buffer blocking layer for metallization, a back antireflection layer and a mask layer in the step of removing the phosphorus-doped polycrystalline silicon which is plated in a winding way. Furthermore, the invention also discloses an n-type passivated contact battery prepared by the method. The invention simplifies the preparation process of the n-type passivated contact battery, reduces the preparation cost and has high feasibility while ensuring the good performance of the battery.
Description
Technical Field
The invention belongs to the technical field of crystalline silicon solar cells, and particularly relates to an n-type passivated contact cell and a preparation method thereof.
Background
In the field of solar cells, a Tunnel Oxide and Passivated Contact (TOPCon) is a novel high-efficiency solar cell, which achieves selective passing of photon-generated carriers by tunneling silicon Oxide and passivating the surface of a crystalline silicon solar cell (hereinafter referred to as a cell) by doped polysilicon, that is, majority carriers can enter a doped polysilicon thin film through a tunneling silicon Oxide layer without obstacle and then are collected, and meanwhile, the recombination rate of minority carriers at the interface of the tunneling silicon Oxide and the silicon is very low and the minority carriers cannot reach the doped polysilicon thin film through the tunneling silicon Oxide. The TOPCon battery can realize one-dimensional collection of photon-generated carriers, reduce the recombination probability of minority carriers and increase the collection probability of majority carriers, thereby having excellent photoelectric conversion efficiency.
At present, in a conventional n-type passivation contact battery preparation process, the back surface of a battery is polished by an acidic solution, so that the back surface of the battery is in a porous silicon shape, the roughness of the back surface is higher and is not smooth enough, the reflectivity of incident long-wave band light can be reduced, and the utilization rate of the long-wave band light by the battery is reduced; in addition, in the preparation process, a nitric acid + hydrofluoric acid system is used for etching the back of the battery and isolating the edges, and the generated harmful gas has great harm to the environment. On the other hand, the conventional preparation process of the n-type passivated contact cell mostly uses alumina as a passivation layer of the front emitter, and the preparation equipment of the alumina needs higher cost investment; in the preparation process of the battery, the step of removing the doped polycrystalline silicon subjected to the winding plating is complex, so that the preparation cost is increased, and the productivity is reduced.
Disclosure of Invention
In view of the above, the invention provides a method for preparing an n-type passivated contact cell, which comprises the steps of preparing a silicon dioxide layer on the front surface of a silicon wafer as a front passivation layer after preparing a front emitter, polishing the mask layer and removing the mask layer of the phosphorus-doped polysilicon step of the plating; carrying out edge isolation and polishing on the back of the silicon wafer by using an alkaline solution to form a smooth polished surface on the back of the silicon wafer; the back silicon nitride is used as a metallization buffer blocking layer, a back antireflection layer (under the condition of double-sided power generation, the back silicon nitride can reduce the back reflectivity when light enters the back of the cell, so that the power generation performance of the back of the cell under the condition of incident light can be effectively improved, and the comprehensive conversion efficiency of the cell is further improved. Furthermore, the invention also discloses an n-type passivated contact battery, wherein a passivated antireflection layer consisting of a silicon dioxide layer and a silicon nitride layer covers above the emitting electrode on the front side of the battery; the surface state of the back surface of the battery is a smooth polished surface, and the passivated contact layer and the silicon nitride layer are covered on the polished surface of the back surface of the battery.
The specific technical scheme of the invention comprises the following steps:
the first scheme is as follows: a method for preparing an n-type passivated contact cell, comprising the steps of:
providing an n-type silicon wafer, and preparing a textured structure on the surface of the n-type silicon wafer;
preparing a boron emitter on the front side of the silicon wafer;
removing borosilicate glass formed on the surface of the silicon wafer in the preparation process of the boron emitter;
preparing a silicon dioxide layer on the surface of a silicon wafer in a thermal oxidation mode; the silicon dioxide layer is used as a front passivation layer, and the mask layer of the subsequent polishing step and the phosphorus-doped polysilicon step of removing the silicon wafer in the winding plating process;
removing the silicon dioxide layer on the back and the edge of the silicon wafer, and reserving the silicon dioxide layer on the front of the silicon wafer;
polishing the back of the silicon wafer in an alkali polishing mode to form a polished surface structure on the back of the silicon wafer, wherein in the process, the silicon dioxide layer on the front of the silicon wafer is partially etched, and the thickness of the silicon dioxide layer is reduced;
preparing a passivation contact layer on the back of the silicon wafer, wherein the passivation contact layer comprises a tunneling silicon oxide layer and a phosphorus-doped polycrystalline silicon layer;
preparing a silicon nitride layer on the back surface of the silicon wafer, wherein the back surface silicon nitride layer is used as a metalized buffer blocking layer, a back surface antireflection layer and a mask layer for removing the phosphorus-doped polycrystalline silicon which is plated in a winding manner;
removing the phosphorus-doped polysilicon formed on the front surface of the silicon wafer in the passivation contact layer preparation step in an alkaline solution etching manner, wherein the phosphorus-doped polysilicon formed on the front surface of the silicon wafer is completely etched, the silicon dioxide layer on the front surface and the silicon nitride layer on the back surface are partially etched, and the thicknesses of the silicon dioxide layer and the silicon nitride layer are reduced;
preparing a silicon nitride layer on the front side of the silicon wafer, wherein the front side silicon nitride layer and the front side silicon oxide layer are superposed to form a front side passivation anti-reflection layer;
and preparing metal electrodes on the front and back surfaces of the silicon wafer.
As a preferable scheme, after the phosphorus-doped polysilicon which is wound and plated is removed, the thickness of the front silicon dioxide layer is 3-20 nm.
Preferably, the thermal oxidation process is implemented by a thermal oxidation furnace tube or a chain type rapid thermal processing furnace.
As a preferable scheme, the thermal oxidation conditions are as follows: the oxidation temperature is 700-1100 ℃, the time is 5-120min, the oxygen proportion is 20-100%, the diluent gas is nitrogen, and the thickness of the prepared silicon dioxide layer is 10-100 nm.
As a preferred embodiment, the silica layer is prepared to a thickness of 30-50 nm.
As a preferable scheme, a silicon dioxide layer on the back surface and the edge of the silicon wafer is removed by using a hydrofluoric acid water bleaching method, wherein the hydrofluoric acid water bleaching conditions are as follows: the concentration of the hydrofluoric acid solution is 3-40%, and the process time is 10-600 s.
As a preferable scheme, the conditions for carrying out alkali polishing on the back surface of the silicon wafer are as follows: the method comprises the steps of selecting 1.5-20% of aqueous solution of potassium hydroxide or sodium hydroxide, wherein the concentration of a polishing additive is 0.05-5%, the temperature of the solution is 45-85 ℃, the polishing time is 10-600s, and the polishing additive is used for reducing the reaction rate of a silicon dioxide layer in the aqueous solution.
As a preferable scheme, after the phosphorus-doped polysilicon which is plated around is removed, the thickness of the back silicon nitride layer is 60-150 nm.
As a preferable scheme, the thickness of the silicon nitride layer prepared on the back surface of the silicon wafer is 90-180nm, and the refractive index is 1.9-2.3.
As a preferable scheme, the silicon nitride layer prepared on the front surface of the silicon wafer has the thickness of 50-80nm and the refractive index of 1.9-2.3.
As a preferred scheme, the thickness of the tunneling silicon oxide layer is 0.3-5nm, and the thickness of the phosphorus-doped polycrystalline silicon layer is 20-200 nm.
As a preferred scheme, the aqueous solution for removing the phosphorus-doped polysilicon in the winding plating is aqueous solution of sodium hydroxide or potassium hydroxide, the concentration of the aqueous solution is 0.5-10%, the temperature of the solution is 25-70 ℃, and the etching time is 5-1200 s.
Preferably, the boron emitter is a uniform emitter or a selective emitter, and when the front-side emitter is a selective emitter, the front-side metal electrode is located right above a heavily doped region in the front-side emitter.
Scheme II: the invention also discloses an n-type passivated contact battery which is prepared by any one of the scheme I and the preferred scheme thereof; the n-type passivated contact cell comprises an n-type silicon substrate, a boron emitter, a front passivated antireflection layer and a front metal electrode, wherein the boron emitter, the front passivated antireflection layer and the front metal electrode are positioned on the front surface of the n-type silicon substrate, and a back passivated contact layer, a back silicon nitride layer and a back metal electrode are positioned on the back surface of the n-type silicon substrate; the back surface of the n-type silicon substrate is of a polished surface structure; the front passivation anti-reflection layer comprises a front silicon dioxide layer and a front silicon nitride layer which are sequentially formed on the boron emitter; the back passivation contact layer comprises a tunneling silicon oxide layer and a phosphorus-doped polysilicon layer.
Preferably, the thickness of the front-side silicon dioxide layer is 3-20 nm; the thickness of the back silicon nitride layer is 60-150 nm.
As a preferred scheme, the thickness of the tunneling silicon oxide layer is 0.5-2nm, and the thickness of the phosphorus-doped polycrystalline silicon layer is 20-200 nm; the thickness of the front silicon nitride layer is 50-80nm, and the refractive index is 1.9-2.3; the surface concentration of the front boron emitter is 5E18cm-3-5E19cm-3。
As a preferred scheme, the thickness of the tunneling silicon oxide layer is 1.2-1.6nm, and the thickness of the phosphorus-doped polycrystalline silicon layer is 70-150 nm; the surface concentration of the front boron emitter is 9E18cm-3-2E19cm-3。
The invention has the following beneficial effects:
(1) the silicon dioxide layer prepared on the front side can play multiple roles of serving as a front passivation layer, a mask layer in a polishing step and a mask layer in a step of removing the phosphorus-doped polycrystalline silicon which is plated in a winding mode, and the silicon nitride layer prepared on the back side can play multiple roles of a metallization buffer blocking layer, a back antireflection layer (double-sided power generation condition) and a mask layer for removing the phosphorus-doped polycrystalline silicon which is plated in a winding mode.
(2) The passivation antireflection layer formed by superposing the silicon dioxide layer and the silicon nitride layer is adopted on the front surface, so that the equipment cost investment is greatly reduced while the excellent surface passivation effect is ensured; compared with the relatively rough polished surface obtained by acid polishing, the polished surface prepared by the alkali polishing method on the back can improve the internal reflection of the cell, thereby effectively improving the utilization rate of the cell to long-wave band light and further improving the open-circuit voltage and short-circuit current of the cell.
(3) After the silicon dioxide layer on the back is removed, the back polishing and the edge isolation of the silicon wafer are realized through alkali polishing, and harmful gas generated after a nitric acid and hydrofluoric acid system is used in the preparation process and the environment is prevented from being damaged.
(4) The phosphorus-doped polysilicon which is wound and plated is removed by an alkali solution etching method, so that the electric leakage influence on the edge of the battery can be effectively reduced.
(5) The n-type passivated contact battery prepared by the invention is flexible in practical application, and can be applied to conventional single-sided power generation and double-sided power generation.
Drawings
FIG. 1 is a schematic process flow diagram of a method for manufacturing an n-type passivated contact cell according to the present invention;
fig. 2 is a schematic diagram of the structure of an n-type passivated contact cell made in accordance with the present invention.
Detailed Description
With reference to fig. 1, the present invention provides a method for manufacturing an n-type passivated contact cell, which mainly comprises the following steps:
step 1: an n-type silicon wafer is selected.
Step 2: and preparing a suede required by the battery on the surface of the n-type silicon wafer. Different texturing methods are selected according to different silicon wafer types, and the specific preparation method is not limited. For example, a regular pyramid-shaped textured surface is prepared on the surface of a silicon wafer by alkali texturing, or an inverted pyramid-shaped textured surface is prepared on the surface of the silicon wafer by a catalytic method.
And step 3: and preparing a boron emitter on the front side of the silicon wafer, wherein the boron emitter on the front side can be a uniform emitter or a selective emitter. The specific preparation method of the boron emitter is not limited, and for example, the boron emitter can be prepared by one or more of furnace tube boron diffusion (boron tribromide or boron trichloride), boron ion implantation, boron slurry doping, laser doping and the like. The square resistance of the front emitter is 30-180 omega/□ (preferably 50-100 omega/□). After the front-side boron emitter is prepared in this step, a layer of borosilicate glass is usually formed on the surface of the silicon wafer.
And 4, step 4: and removing the borosilicate glass on the surface of the silicon wafer. And removing the borosilicate glass on the surface of the silicon wafer by using a hydrofluoric acid cleaning method. Cleaning conditions of hydrofluoric acid: the concentration of hydrofluoric acid is 2-30%, and the cleaning time is 2-120 min.
And 5: and preparing a silicon dioxide layer on the front side of the silicon wafer by a thermal oxidation method. It is emphasized that this silicon dioxide layer can serve multiple functions of a front side passivation layer, a polishing step masking layer, and a masking layer for a step of removing the phosphorus doped polysilicon that is plated around. The thermal oxidation process may be achieved by furnace thermal oxidation or a chained rapid thermal processing furnace. The specific technological conditions are that the oxidation temperature is 700-. The thickness of the prepared silicon dioxide layer is 10-100nm, preferably 30-50 nm.
It should be noted that the thermal oxidation process described in this step may further redistribute the doping profile of the front side boron emitter, the specific variation degree depends on the specific thermal oxidation process conditions, and the final doping profile distribution (i.e. boron surface doping concentration, junction depth and sheet resistance) of the front side boron emitter of the cell is finally formed after the thermal oxidation process of this step. Therefore, in the actual battery process preparation flow, the boron emitter distribution which finally meets the design requirement can be obtained by jointly adjusting and optimizing the boron diffusion and thermal oxidation process parameters, and generally, the final front boron emitter surface concentration is 5E18cm-3-5E19cm-3(preferably: 9E18cm-3-2E19cm-3) The sheet resistance is 50-200 Ω/□ (preferably: 70-120 Ω/□). In addition, in the thermal oxidation process of the step, a silicon dioxide layer is formed on the back surface of the n-type silicon wafer concomitantly.
Step 6: and removing the silicon dioxide layer on the back of the n-type silicon wafer. And removing the silicon dioxide layer on the back of the silicon wafer by using a hydrofluoric acid water bleaching method, wherein in the removing process, the silicon dioxide layer on the front of the silicon wafer is protected and cannot be removed due to the fact that the water film covers the silicon dioxide layer on the front, the silicon dioxide layers on the back and the edge of the silicon wafer are completely removed after the step is completed, and the silicon dioxide layer on the front is reserved. Hydrofluoric acid water bleaching condition: the concentration of the hydrofluoric acid solution is 3-40%, and the process time is 10-600 s.
And 7: and polishing the back surface of the n-type silicon wafer. And polishing the back surface of the n-type silicon wafer by an alkali polishing method, wherein the silicon dioxide layer on the front surface of the silicon wafer is slowly reacted with the alkali solution, so that the thickness of the silicon dioxide layer is reduced, but the silicon dioxide layer is not polished by the alkali solution. The alkaline polishing conditions may be: the aqueous solution is prepared from potassium hydroxide or sodium hydroxide 1.5-20%, polishing additive 0.05-5%, solution temperature 45-85 deg.C, and polishing time 10-600 s. The polishing additive is a chemical containing fatty alcohol-polyoxyethylene ether and the like, and has the function of further reducing the reaction rate of the silicon dioxide layer in the alkali solution. After alkali polishing, the silicon dioxide layer on the front surface of the n-type silicon wafer is partially etched, and the thickness is reduced to 5-95 nm.
And 8: and preparing a passivation contact layer on the back of the n-type silicon wafer. The passivation contact layer comprises a tunneling silicon oxide layer and a phosphorus-doped polycrystalline silicon layer. Wherein the tunneling silicon oxide layer has a thickness of 0.5-2nm (preferably: 1.2-1.6nm), and the phosphorus-doped polysilicon layer has a thickness of 20-200nm (preferably: 70-150 nm). The method for preparing the passivation contact layer is not limited in the invention, and the conventional preparation method in the industry can be used. The preparation of the tunneling silicon oxide layer can be realized by thermal oxidation, nitric acid oxidation, ozone oxidation, plasma enhanced chemical vapor deposition, and the like, without being limited thereto. The specific preparation method of the phosphorus-doped polysilicon layer can be, for example, preparing intrinsic amorphous silicon by low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, and then completing phosphorus doping by adopting phosphorus oxychloride diffusion or ion implantation combined annealing. Alternatively, when depositing the amorphous silicon by PECVD, phosphorane (process gases are generally silane, hydrogen and phosphorane, and nitrogen) is introduced to dope the phosphorus dopant on-line, and then the crystallization of the amorphous silicon to the polysilicon and the activation and redistribution of the phosphorus dopant are completed by annealing. After the phosphorus-doped polycrystalline silicon layer is prepared, the phosphorus-doped polycrystalline silicon which is subjected to winding plating can be generated on the edge of the front side of the n-type silicon wafer due to the winding plating phenomenon.
And step 9: and preparing a back silicon nitride layer. The specific preparation method is not limited, and the preparation method can be, for example, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, physical vapor deposition, and the like. It is emphasized that the back side silicon nitride layer has several functions, in the first aspect, it can be used as a buffer barrier layer for subsequent metallization, which is used to buffer and block excessive diffusion of metal through the polysilicon layer and the tunneling silicon oxide layer into the silicon substrate in the subsequent sintering annealing, and ideally, the metal is completely limited in the polysilicon layer; in the second aspect, the silicon wafer can also be used as a mask layer for removing the phosphorus-doped polycrystalline silicon wound and plated on the front surface of the n-type silicon wafer; in a third aspect, the back silicon nitride layer can also be used as a back antireflection layer in a double-sided power generation environment of the n-type passivated contact battery, so that the comprehensive efficiency of double-sided power generation of the battery (and the power generation amount of a module and a photovoltaic system are increased). The thickness of the prepared back silicon nitride layer is 90-180nm, and the refractive index is 1.9-2.3.
Step 10: and removing the phosphorus-doped polysilicon wound and plated on the front surface of the n-type silicon wafer by an alkali solution etching method. The phosphorus-doped polysilicon which is wound and plated is positioned above the silicon dioxide layer on the front surface, and the phosphorus-doped polysilicon which is wound and plated is directly contacted with an alkali solution and reacts; the front-side silicon dioxide layer is positioned above the front-side boron emitter and is directly contacted with the alkali solution to react; the back silicon nitride layer is positioned above the back passivation contact layer and is directly contacted with the alkali solution and reacts. Because the reaction speed of the polysilicon and the alkali solution is faster than that of the silicon oxide and the silicon nitride and the alkali solution, the phosphorus-doped polysilicon which is wound and plated is completely removed in the preset time, the silicon dioxide layer on the front side is removed in a small amount, the thickness of the silicon dioxide layer on the front side is reduced to about 3-20nm, the silicon nitride layer on the back side is also removed in a small amount, and the thickness of the silicon nitride layer on the back side is reduced to about 60-150 nm. The alkali solution can be sodium hydroxide or potassium hydroxide, and the etching conditions of the alkali solution are as follows: the concentration of the alkali solution is 0.5-10%, the temperature of the solution is 25-70 ℃, and the etching time is 5-1200 s.
Step 11: and preparing a front silicon nitride layer. The front silicon nitride layer is prepared by plasma enhanced chemical vapor deposition, physical vapor deposition and other methods. And the front silicon nitride layer and the front silicon oxide layer are superposed to form a front passivation antireflection layer. The thickness of the front silicon nitride layer is 50-80nm, and the refractive index is 1.9-2.3.
Step 12: and preparing metal electrodes on two sides of the n-type silicon wafer. The metal electrode comprises a front metal electrode and a back metal electrode of the silicon chip. The conventional metallization preparation methods in the industry can be used, such as screen printing, electroplating, sputtering and the like. It should be noted that if the selective emitter is prepared in step 3, the front metal electrode should be located right above the heavily doped region in the front emitter.
According to the invention, the final front emitter of the battery is formed by preparing the front emitter in the step 3, removing borosilicate glass on the surface of the silicon wafer in the step 4 and preparing a silicon dioxide layer on the front of the silicon wafer in the step 5, and meanwhile, the silicon dioxide layer is generated on the front of the silicon wafer and is used as a mask layer when the back of the silicon wafer is polished in the step 7, and is used as a mask layer when phosphorus-doped polysilicon which is wound and plated is removed in the step 10 and is used as a front passivation layer.
In the invention, it is considered that the borosilicate glass formed in the step 3 of preparing the front emitter has uneven thickness, and the borosilicate glass contains boron element with high concentration, which can reduce passivation effect, and is not suitable for being used as a passivation anti-reflection layer. In addition, the borosilicate glass contains high content of boron element, and because the borosilicate glass contains high concentration of boron element, if not removed in advance, the boron element is easy to enter into the phosphorus-doped polycrystalline silicon in the winding plating in the step 8, so that the phosphorus-doped polycrystalline silicon in the winding plating is difficult to be removed in the step 10. The silicon oxide prepared on the boron emitter by the thermal oxidation mode has uniform thickness and excellent passivation effect, and does not contain high-concentration boron element. Therefore, after the borosilicate glass is removed, a silicon dioxide layer with a certain thickness is formed on the front surface of the silicon chip through a thermal oxidation mode, and the silicon dioxide layer is used as a passivation layer of a front emitter on one hand and can also be used as a mask layer in a subsequent polishing step and a mask layer in a step of removing phosphorus-doped polycrystalline silicon which is plated in a winding manner on the other hand.
Because the silicon dioxide layer is generated on the back surface of the silicon wafer when the silicon dioxide layer on the front surface of the silicon wafer is prepared in the step 5, the reaction speed of the silicon dioxide layer and the alkaline solution is low, and in order to ensure that the step 7 can be smoothly carried out, the step 6 is added before polishing to remove the silicon dioxide layer on the back surface of the silicon wafer. According to the invention, the silicon dioxide layer on the back of the silicon wafer is removed in the step 6, and the back of the silicon wafer is polished in the step 7 to realize polishing and edge isolation of the back of the silicon wafer, so that an etching system which is commonly used in the industry and is formed by hydrofluoric acid and nitric acid is replaced. The alkaline polishing effect of the invention is superior to that of a hydrofluoric acid and nitric acid etching system, and the back of the polished silicon wafer is a smooth polished surface, thereby not only effectively improving the utilization rate of the cell to long-wave band light, but also not generating nitrogen-containing toxic gas and being more environment-friendly. Because the silicon dioxide layer is arranged on the front side of the silicon wafer in the step 7, the silicon dioxide layer is not arranged on the back side of the silicon wafer, the back side of the silicon wafer can be polished by the alkali solution, the front side of the silicon wafer cannot be polished by the alkali solution, only the thickness is slightly reduced, and the passivation performance of the silicon wafer is hardly influenced.
The method comprises the steps of preparing a back silicon nitride layer in step 9, and then removing phosphorus-doped polycrystalline silicon wound and plated on the front surface of a silicon wafer in step 10. Compared with the method that borosilicate glass is used as the front mask layer in the step 10, when the silicon dioxide layer is used as the front mask layer for removing the phosphorus-doped polysilicon which is wound and plated, the uniformity of the silicon dioxide layer is better, the reaction rate with alkali solution is lower, and the protection effect on a front emitter is better; and the silicon dioxide layer does not contain high-concentration boron element, so that a large amount of boron element cannot enter the phosphorus-doped polycrystalline silicon which is subjected to the winding plating, and the phosphorus-doped polycrystalline silicon which is subjected to the winding plating can quickly react in an alkaline solution so as to be removed. Compared with other methods for removing the phosphorus-doped polysilicon in the winding plating in the industry, the method can retain a part of the front silicon dioxide layer as the front passivation layer and a part of the back silicon nitride layer as the subsequent metallization buffer blocking layer and the back antireflection layer after removing the phosphorus-doped polysilicon in the winding plating in the step 10.
It should be further noted that the front-side silicon dioxide layer plays a role in back-side alkali polishing and removing a mask layer of phosphorus-doped polysilicon which is plated around in the battery preparation process, and the front-side silicon dioxide layer plays a role in front-side passivation and anti-reflection film after the battery preparation is finished; similarly, the back silicon nitride layer of the invention plays a role in removing the mask layer and the metallization buffer barrier layer of the phosphorus-doped polysilicon which is plated around in the preparation of the cell, and the back silicon nitride layer plays a role in a back antireflection layer (in the case of double-sided power generation) after the preparation of the cell is finished. Therefore, in the preparation of the cell, the optimized film thickness of the front silicon dioxide and the back silicon nitride at the final cell end can be obtained through the optimized design and integration of the cell preparation process flow, such as the combined design, optimization and integration of several process parameters of the thickness of the initially prepared front silicon dioxide (or back silicon nitride), the alkali polishing process, the thickness of the phosphorus-doped polysilicon, the alkali solution etching process for removing the phosphorus-doped polysilicon which is plated around, and the like, so that the good photoelectric conversion efficiency of the cell is obtained.
The method greatly shortens the preparation process of the n-type passivated contact battery and greatly reduces the preparation cost of the battery.
The invention also discloses an n-type passivated contact battery which can be prepared by adopting the method and is shown in the combined figure 2. The n-type passivated contact cell mainly comprises an n-type silicon substrate 1, a front emitter 2, a front silicon dioxide layer 3, a front silicon nitride layer 4, a front metal electrode 5, a back passivated contact layer 6, a back silicon nitride layer 7 and a back metal electrode 8. The front passivation antireflection layer is composed of a silicon dioxide layer and a silicon nitride layer which cover the emitter on the front side of the battery; the surface appearance of the back surface of the battery is a smooth polished surface, and a passivation contact layer (namely, the passivation contact layer consists of a tunneling silicon oxide layer and a phosphorus-doped polycrystalline silicon layer) and a silicon nitride layer are covered on the polished surface of the back surface of the battery. The cell has excellent surface passivation effect and utilization rate of long-wavelength band light.
Based on the above method, to further illustrate the technical solution of the present invention, a specific example of a method for manufacturing an n-type passivated contact cell is given below, which mainly comprises the following steps:
1) an n-type monocrystalline silicon wafer with a (100) crystal orientation is selected, and the resistivity of the silicon wafer is about 1 omega cm.
2) And preparing a texture surface with a random pyramid shape on the surface of the n-type silicon wafer by using an alkali texture surface preparation method.
3) And preparing a uniform emitter on the front surface of the n-type silicon wafer by using a furnace tube boron diffusion method, wherein the square resistance of the emitter on the front surface is 80 omega/□. After the boron diffusion of the furnace tube is finished, a layer of borosilicate glass is generated on the surface of the silicon wafer.
4) And removing the borosilicate glass on the surface of the n-type silicon wafer by using a hydrofluoric acid cleaning method. Cleaning conditions of hydrofluoric acid: the concentration of hydrofluoric acid is 10%, and the cleaning time is 20 min.
5) And preparing a silicon dioxide layer on the front side of the silicon wafer on the front side of the n-type silicon wafer by using a furnace tube thermal oxidation method, wherein the silicon dioxide layer is used as a front passivation layer and a mask layer in the step of removing the phosphorus-doped polycrystalline silicon which is subjected to winding plating. The thermal oxidation conditions of the furnace tube are as follows: the oxidation temperature is 950 ℃, the time is 60min, the oxygen proportion is 50%, and the diluent gas is nitrogen. The thickness of the prepared silicon dioxide layer is about 40 nm. After the thermal oxidation of this step, the surface concentration of the front-side boron emitter finally becomes 1E19cm-3The sheet resistance finally becomes 100 Ω/□. In addition, in the thermal oxidation process of the step, a silicon dioxide layer is formed on the back surface of the n-type silicon wafer concomitantly.
6) And removing the silicon dioxide layer on the back surface of the n-type silicon wafer by using a hydrofluoric acid water bleaching method, covering a water film on the front surface of the silicon wafer to protect the silicon dioxide layer on the front surface from being removed, completely removing the silicon dioxide layer on the back surface and the edge of the silicon wafer after the step is finished, and reserving the silicon dioxide layer on the front surface. Hydrofluoric acid water bleaching condition: the concentration of the hydrofluoric acid solution is 5%, and the etching time is 120 s.
7) And polishing the back surface of the n-type silicon wafer by using an alkali polishing method. Because the reaction between the silicon dioxide layer on the front surface of the silicon wafer and the alkali solution is slow, the thickness of the silicon dioxide layer is reduced, and the front surface of the silicon wafer cannot be polished by the alkali solution. The aqueous alkali is potassium hydroxide aqueous solution. Alkali polishing conditions: the concentration of the potassium hydroxide is 3 percent, the concentration of the polishing additive is 1 percent, the temperature of the solution is 60 ℃, and the polishing time is 200 s. The polishing additive refers to chemicals containing fatty alcohol-polyoxyethylene ether and the like, and has the function of further reducing the reaction rate of silicon dioxide in an alkali solution. After alkali polishing, the thickness of the silicon dioxide layer on the front surface of the n-type silicon wafer is reduced by about 10 nm.
8) And preparing a passivation contact layer on the back surface of the n-type silicon wafer by using a low-pressure chemical vapor deposition heating annealing method. The passivation contact layer includes a tunneling silicon oxide layer and a phosphorus-doped polysilicon layer. Wherein the thickness of the tunneling silicon oxide layer is 1.5nm, and the thickness of the phosphorus-doped polycrystalline silicon layer is 100 nm. After the passivation contact layer is prepared, the phosphorus-doped polycrystalline silicon which is subjected to winding plating can be generated at the edge of the front side of the n-type silicon wafer due to the winding plating phenomenon.
9) And preparing the back silicon nitride layer by using a plasma enhanced chemical vapor deposition method. The back silicon nitride layer is simultaneously used as a mask layer for removing the phosphorus-doped polysilicon which is plated in a winding way, a metallization buffer blocking layer and a back antireflection layer. The back silicon nitride layer has a thickness of 100nm and a refractive index of 2.0.
10) And removing the phosphorus-doped polysilicon wound and plated on the front surface of the n-type silicon wafer by using an alkali solution etching method. The aqueous alkali is potassium hydroxide aqueous solution, and the etching conditions of the aqueous alkali are as follows: the concentration of the alkali solution is 5 percent, the temperature of the solution is 60 ℃, and the etching time is 100 s. And completely removing the phosphorus-doped polysilicon which is etched by the alkaline solution, wherein the thickness of the silicon dioxide layer on the front surface of the n-type silicon wafer is about 15nm, and the thickness of the silicon nitride layer on the back surface of the n-type silicon wafer is about 80 nm.
11) And preparing the front silicon nitride layer by using a plasma enhanced chemical vapor deposition method. The thickness of the front silicon nitride layer is 60nm, and the refractive index is 2.0. And the front silicon nitride layer and the front silicon oxide layer are superposed to form a front passivation antireflection layer.
12) And preparing metal electrodes on two sides of the n-type silicon wafer by using a screen printing and sintering method. The metal electrodes on the two surfaces are distributed in a grid shape at equal intervals.
Finally, it should be noted that while the above describes exemplifying embodiments of the invention with reference to the accompanying drawings, the invention is not limited to the embodiments and applications described above, which are intended to be illustrative and instructive only, and not limiting. Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto without departing from the scope of the invention as defined by the appended claims.
Claims (14)
1. A method for preparing an n-type passivated contact cell, comprising the steps of:
providing an n-type silicon wafer, and preparing a textured structure on the surface of the silicon wafer;
preparing a boron emitter on the front side of the silicon wafer;
removing borosilicate glass formed on the surface of the silicon wafer in the preparation process of the boron emitter;
preparing a silicon dioxide layer on the surface of the silicon wafer in a thermal oxidation mode; the silicon dioxide layer is used as a front passivation layer, and the mask layer of the subsequent polishing step and the phosphorus-doped polysilicon step of removing the silicon wafer in the winding plating process;
removing the silicon dioxide layer on the back and the edge of the silicon wafer, and reserving the silicon dioxide layer on the front of the silicon wafer;
polishing the back of the silicon wafer in an alkali polishing mode to form a polished surface structure on the back of the silicon wafer, wherein in the process, the silicon dioxide layer on the front of the silicon wafer is partially etched, and the thickness of the silicon dioxide layer is reduced;
preparing a passivation contact layer on the back of the silicon wafer, wherein the passivation contact layer comprises a tunneling silicon oxide layer and a phosphorus-doped polycrystalline silicon layer;
preparing a silicon nitride layer on the back surface of the silicon wafer, wherein the back surface silicon nitride layer is used as a metalized buffer blocking layer, a back surface antireflection layer and a mask layer for removing the phosphorus-doped polycrystalline silicon which is plated in a winding manner;
removing the phosphorus-doped polysilicon formed on the front surface of the silicon wafer in the passivation contact layer preparation step in an alkaline solution etching manner, wherein the phosphorus-doped polysilicon formed on the front surface of the silicon wafer is completely etched, and the silicon dioxide layer on the front surface and the silicon nitride layer on the back surface are partially etched, so that the thickness is reduced;
preparing a silicon nitride layer on the front side of the silicon wafer, wherein the front side silicon nitride layer and the front side silicon oxide layer are superposed to form a front side passivation anti-reflection layer;
and preparing metal electrodes on the front and back surfaces of the silicon wafer.
2. The method of claim 1, wherein the thickness of the silicon dioxide layer prepared on the surface of the silicon wafer is 10-100 nm; and after removing the phosphorus-doped polysilicon which is plated in a winding way, the thickness of the silicon dioxide layer on the front surface is 3-20 nm.
3. The method of claim 2, wherein the silicon dioxide layer is prepared on the surface of the silicon wafer to a thickness of 30 to 50 nm.
4. The method of claim 1, wherein the thermal oxidation process is performed by a thermal oxidation furnace tube or a chained rapid thermal processing furnace.
5. The method according to claim 4, characterized in that the conditions of the thermal oxidation are: the oxidation temperature is 700 ℃ and 1100 ℃, the time is 5-120min, the oxygen proportion is 20-100%, and the diluent gas is nitrogen.
6. The method of claim 1, wherein the silicon dioxide layer on the back surface and the edge of the silicon wafer is removed by using an aqueous hydrofluoric acid rinsing method, and the conditions of the aqueous hydrofluoric acid rinsing method are as follows: the concentration of the hydrofluoric acid solution is 3-40%, and the process time is 10-600 s.
7. The method of claim 1, wherein the conditions for alkali polishing the back surface of the silicon wafer are: the method comprises the steps of selecting 1.5-20% of aqueous solution of potassium hydroxide or sodium hydroxide, wherein the concentration of a polishing additive is 0.05-5%, the temperature of the solution is 45-85 ℃, the polishing time is 10-600s, and the polishing additive is used for reducing the reaction rate of a silicon dioxide layer in the aqueous solution.
8. The method of claim 1 wherein the back side silicon nitride layer has a thickness of 60-150nm after removing the phosphorus doped polysilicon layer.
9. The method of claim 8, wherein the silicon nitride layer prepared on the back side of the silicon wafer has a thickness of 90 to 180nm and a refractive index of 1.9 to 2.3.
10. The method as claimed in claim 1, wherein the aqueous alkali solution for removing the phosphorus-doped polysilicon is an aqueous solution of sodium hydroxide or potassium hydroxide, the concentration of the aqueous alkali solution is 0.5-10%, the temperature of the solution is 25-70 ℃, and the etching time is 5-1200 s.
11. An n-type passivated contact cell, characterized by being prepared by the method of any one of claims 1 to 10; the n-type passivated contact cell comprises an n-type silicon substrate, a boron emitter, a front passivated antireflection layer and a front metal electrode, wherein the boron emitter, the front passivated antireflection layer and the front metal electrode are positioned on the front surface of the n-type silicon substrate, and a back passivated contact layer, a back silicon nitride layer and a back metal electrode are positioned on the back surface of the n-type silicon substrate; the back surface of the n-type silicon substrate is of a polished surface structure; the front passivation anti-reflection layer comprises a front silicon dioxide layer and a front silicon nitride layer which are sequentially formed on the boron emitter; the back passivation contact layer comprises a tunneling silicon oxide layer and a phosphorus-doped polysilicon layer.
12. The n-type passivated contact cell of claim 11 wherein the front side silicon dioxide layer has a thickness of 3-20nm and the back side silicon nitride layer has a thickness of 60-150 nm.
13. The n-type passivated contact cell of claim 12 wherein the tunneling silicon oxide layer is 0.5-2nm thick and the phosphorus doped polysilicon layer is 20-200nm thick; the thickness of the front silicon nitride layer is 50-80nm, and the refractive index is 1.9-2.3; the surface concentration of the front boron emitter is 5E18cm-3-5E19 cm-3The sheet resistance of the front boron emitter is 50-200 omega/□.
14. The n-type passivated contact cell of claim 13 wherein the tunneling silicon oxide layer is 1.2-1.6nm thick and the phosphorus doped polysilicon layer is 70-150nm thick; the surface concentration of the front boron emitter is 9E18cm-3-2E19 cm-3And the square resistance of the front boron emitter is 70-120 omega/□.
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