CN111509057A - N-type battery and preparation method thereof - Google Patents

N-type battery and preparation method thereof Download PDF

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CN111509057A
CN111509057A CN202010359582.8A CN202010359582A CN111509057A CN 111509057 A CN111509057 A CN 111509057A CN 202010359582 A CN202010359582 A CN 202010359582A CN 111509057 A CN111509057 A CN 111509057A
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符黎明
黄海冰
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Changzhou Shichuang Energy Co Ltd
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Abstract

The invention provides an n-type cell, wherein an emitter junction on the front side of the cell is a selective emitter junction consisting of a p-type lightly doped region and a local p-type heavily doped region higher than the lightly doped region, and a cell back side doped layer, a cell passivation layer and a metal electrode are compatible with the back side technology of other n-type cells. By adopting the front selective emitter junction, ohmic contact resistance of a metal semiconductor on the front surface of the n-type cell and recombination loss of a photon-generated carrier on the front surface of the cell can be effectively reduced, so that the performance of the cell is improved, and the surface appearances of a heavy doping area and a light doping area of the selective emitter junction can be independently controlled, so that different metallization schemes of the cell can be conveniently selected.

Description

N-type battery and preparation method thereof
Technical Field
The invention relates to the technical field of crystalline silicon solar cell preparation, in particular to an n-type cell and a preparation method thereof.
Background
Common n-type batteries mainly comprise passivated emitter junction full back field diffusion (PERT) batteries, passivated emitter junction back local diffusion (PER L) batteries and tunneling oxidation passivation contact (TOPCon) batteries, and the batteries are all focused on the back design of a battery structure so as to improve the performance of the batteries.
The design of the front structure of the n-type battery is used for further improving the battery performance, and the selective boron emitter junction technology is mainly used for simultaneously reducing the recombination loss of a non-metal contact area and a metal contact area. However, selective emitter junctions of n-type cells have been difficult to achieve, mainly for the following reasons: 1) the solid solubility of boron element in silicon oxide is higher than that of boron element in silicon, and the boron surface concentration in a laser heat treatment area can be reduced by a method of boron diffusion and laser doping; 2) the ion implantation method limits further industrial application due to higher equipment cost investment; 3) the method of boron doping agent and laser doping requires high-power laser, which causes crystal damage; 4) the boron dopant and high-temperature annealing method can cause boron element to volatilize from the boron dopant, so that an uneven light diffusion layer is formed in other areas of the silicon wafer, and the loss of photon-generated carriers is increased. In addition, the surface topography of the heavily doped region of the metal contact in the selective emitter junction of the front side of the cell is generally the same as that of the lightly doped light receiving region, and thus cannot be flexibly selected and controlled, thereby being unfavorable for the selection of the front side metallization scheme.
Disclosure of Invention
In view of the above, the present invention provides an n-type cell and a method for manufacturing the same, wherein a p-type doped layer on a front surface of the cell is a selective emitter junction structure composed of a p-type lightly doped emitter junction and a local p-type heavily doped region higher than the lightly doped region, and the doped layer on a back surface of the cell, a passivation layer and a metal electrode are compatible with other n-type cell technologies. By adopting the front selective emitter junction, the contact resistance of the front of the n-type cell and the recombination loss of a photon-generated carrier on the front of the cell can be effectively reduced, the performance of the cell is further improved, and the surface appearances of a heavily doped region and a lightly doped region of the front selective emitter junction of the cell can be independently controlled, so that the selection range of a corresponding metallization technical scheme can be widened.
In order to achieve the purpose, the technical scheme of the invention comprises the following steps:
the first scheme is as follows: a preparation method of an n-type battery comprises the following steps:
selecting a (100) crystal orientation n-type monocrystalline silicon wafer, and carrying out surface structuring treatment on the n-type monocrystalline silicon wafer to form a specific morphology (such as a textured structure and a polishing structure) on the surface of the silicon wafer;
partially covering the front surface of the n-type silicon wafer subjected to the structuring treatment with a boron dopant, and carrying out high-temperature propulsion on the n-type silicon wafer to form a local p-type heavily doped region on the front surface of the n-type silicon wafer, wherein the surface concentration of boron in the local p-type heavily doped region is 7E19-1E22cm-3；
Removing borosilicate glass generated on the surface of the n-type silicon wafer in the high-temperature propelling process, then carrying out alkali texturing on the n-type silicon wafer, etching a light diffusion layer which is formed outside a local area covered by the boron dopant in the high-temperature propelling process and is formed by volatilization of boron elements in the boron dopant, and reforming a textured structure on the surface of the n-type silicon wafer, wherein in the process, the local p-type heavily doped region retains the original surface appearance;
carrying out p-type light doping (namely p-type light doped emitter junction) on the front surface of the n-type silicon wafer subjected to alkali texturing to form a p-type light doped region, wherein the surface concentration of boron elements in the p-type light doped region is lower than that of boron elements in a local p-type heavily doped region, and the height of the boron elements is lower than that of the local p-type heavily doped region;
manufacturing an n-type doping layer on the back surface of the n-type silicon wafer, wherein the n-type doping layer is any one of a phosphorus-doped full-area back field structure, a local phosphorus-doped back field structure and a passivation contact structure;
manufacturing a passivation antireflection layer on the front surface of the n-type silicon wafer, and manufacturing a passivation layer on the back surface of the n-type silicon wafer
And manufacturing metal electrodes on the front surface and the back surface of the n-type silicon wafer, wherein the front metal electrode corresponds to the local p-type heavily doped region (note: corresponding means alignment in the whole patent).
As a preferred scheme, a boron doping agent is partially covered on the front surface of the n-type silicon wafer subjected to the structuring treatment in a screen printing or printing mode; the boron dopants include, but are not limited to, boron-containing slurries, boron inks, and boron-doped silicon powders.
As a preferable scheme, the alkali texturing conditions are as follows: the alkaline wool making solution is 2-5% potassium hydroxide (KOH) or sodium hydroxide (NaOH) solution, and the temperature of the alkaline wool making solution is 50-80 ℃ and the wool making time is 5-10 min.
As a preferable scheme, after the alkali texturing is finished, the height of the local p-type heavily doped region is 0.5-2um higher than that of the p-type lightly doped region of the textured structure.
Preferably, the junction depth of the local p-type heavily doped region is deeper than that of the p-type lightly doped region.
As a preferable scheme, the high-temperature advancing process scheme is as follows: the propulsion temperature is 750-; after the high-temperature propelling process is finished, the junction depth of the local p-type heavily doped region is 1-3um, and the square resistance is 20-80 omega/□.
As a preferable scheme, the light doping can be realized by boron tribromide tube type boron diffusion, boron ion implantation or vapor phase chemical deposition, the junction depth of the p-type light doping area is 0.3-1um, and the square resistance is 80-500 omega/□.
Preferably, the local p-type heavily doped region is patterned, and the pattern corresponds to the front metal electrode pattern.
As a preferable scheme, the manufacturing mode of the metal electrode comprises screen printing, electroplating or physical vapor deposition; and the scheme of the surface structuring treatment can be determined according to the selected metallization preparation technology; for example, when the metal electrode is manufactured by electroplating or physical vapor deposition, the surface structuring process is performed by polishing, so as to form a polishing structure in the local p-type heavily doped region optimally; when the metal electrode is manufactured by screen printing, the surface structuring treatment adopts a texturing method, so that a texture surface structure is formed in the local p-type heavily doped region optimally.
Scheme II: an n-type cell prepared by the method of scheme one or any of its preferred schemes, comprising: a monocrystalline n-type silicon wafer; the p-type doping layer is positioned on the front surface of the n-type silicon wafer, the p-type doping layer is of a selective emitter junction structure consisting of a p-type lightly doped emitter junction and a local p-type heavily doped region, and the height of the local p-type heavily doped region is 0.5-2um higher than that of the p-type lightly doped emitter junction region; the junction depth of the local p-type heavily doped region is 1-3um, and the square resistance is 20-80 omega/□; the junction depth of the p-type lightly doped region is 0.3-1um, and the square resistance is 80-500 omega/□; the n-type doping layer is positioned on the back surface of the n-type silicon wafer and is any one of a phosphorus-doped full-area back field structure, a local phosphorus-doped back field structure and a passivation contact structure; a passivation anti-reflection layer positioned on the front p-type doped layer; the passivation layer is positioned on the back n-type doped layer; the front metal electrode is positioned on the front passivation anti-reflection layer, and the back metal electrode is positioned on the back passivation layer, and the front metal electrode corresponds to the position of the local p-type heavily doped region.
The invention has the following beneficial effects:
(1) the invention provides a preparation method of an n-type battery, which is characterized in that a boron dopant and high-temperature propulsion method is used for manufacturing a p-type heavily doped region of a selective emitter junction on the front surface of the battery, a p-type lightly doped region of the selective emitter junction is manufactured outside the p-type heavily doped region on the front surface of the battery, and before the p-type lightly doped region is manufactured, an alkali texturing method is used for etching and removing boron elements volatilized from the boron dopant in the heavily doped process to form an uneven light diffusion layer and generate a textured surface. The surface appearance, the surface concentration and the doping depth of the lightly doped region and the heavily doped region of the n-type cell front selective emitter junction prepared by the method can be independently controlled, so that the negative influence caused by uneven doping formed by volatilization of boron from a boron dopant is avoided, the selection of different metallization schemes is widened, and the performance of the n-type cell is improved.
(2) When the uneven lightly doped region formed by volatilization of boron element in the high-temperature propelling process is removed by using the alkaline solution etching, the local heavily doped p-type region is kept, and the boron-rich layer on the surface of the boron dopant covering region can be corroded, so that the junction splitting phenomenon can be remarkably reduced, the parallel resistance of the battery is improved, the electric leakage of the battery is reduced, and the performance of the n-type battery can be greatly improved.
(3) The cell is a selective emitter junction structure consisting of a p-type lightly doped emitter junction and a local p-type heavily doped region higher than the lightly doped region, and the back doped layer, the back passivation layer and the metallization of the cell can be compatible with the back technology of other n-type cells. Compared with other n-type batteries, the contact resistance of the front surface of the n-type battery and the recombination loss of current carriers on the front surface of the battery can be effectively reduced, and the performance of the battery is further improved. In addition, the surface morphology of the local p-type heavily doped region can be determined according to the selected front metal electrode manufacturing mode, the surface morphologies of the selective emitter junction heavily doped region and the lightly doped region are respectively controlled, and different metallization schemes of the battery can be conveniently selected.
(4) The invention forms 7E19cm by a partial boron dopant capping step in combination with a high temperature drive-in step-3The boron doping concentration above can be realized by most doping methods; and because the concentration of boron is high enough, the window range of the alkali solution chemical etching process parameter conditions is wide, the local heavy doping area is easy to realize after the alkali etching through the chemical etching step, the peripheral unnecessary light diffusion area is easy to completely etch and remove, and the feasibility is very high. Compared with other preparation methods of the n-type cell front emitter junction, the preparation method has the characteristics of simple process, wide process window, low equipment cost investment, wide application prospect and the like.
Drawings
FIG. 1 is a schematic diagram of a process for manufacturing an n-type cell according to the present invention;
FIG. 2 is a schematic diagram of an n-type cell according to the present invention;
fig. 3 is a schematic diagram of doping curves of local p-type heavy doping and p-type light doping on the front surface of the n-type cell in the invention.
Detailed Description
Referring to fig. 1 to 3, the present invention provides a method for manufacturing an n-type cell, which mainly comprises the following steps:
1) an n-type monocrystalline silicon wafer (hereinafter referred to as an n-type silicon wafer) with a (100) crystal orientation is selected to be subjected to surface structuring treatment (texturing or polishing) so as to form a textured structure or a polishing structure on the front surface of the n-type silicon wafer. Specifically, methods such as alkali polishing, alkali texturing, acid texturing and Reactive Ion Etching (RIE) can be selected for texturing or polishing, and the selected texturing or polishing method and the texturing or polishing condition finally determine the surface topography of the selective emitter junction heavily doped region on the front surface of the battery.
2) And partially covering the boron dopant on the front surface of the n-type silicon wafer after texturing or polishing. Specifically, a screen printing or printing mode can be selected to partially cover the surface of the n-type silicon wafer with boron dopants, wherein the boron dopants can be in a patterned grid-line-shaped distribution, partially cover the surface of the silicon wafer and correspond to the position of the front electrode (namely are positioned right below the front electrode to be printed). The boron dopant used on the surface of the n-type silicon wafer includes but is not limited to boron-containing slurry, boron Ink (Ink), and boron-doped silicon powder.
3) And putting the n-type silicon wafer partially covered with the boron dopant into high-temperature heat treatment equipment for propulsion to form a local p-type heavily doped region. The propulsion process scheme can be set as follows: the propulsion temperature is 750-1100 ℃, the time is 30-120min, the nitrogen flow is 3000-20000sccm, and the oxygen flow is 0-20000 sccm. The surface concentration of boron element in the local p-type heavily doped region after the drive-in process is 7E19-1E22cm-3The junction depth is 1-3um, and the square resistance is 20-80 omega/□. After the drive-in process is completed, the area outside the local p-type heavily doped region forms uneven surface concentration lower than 5E19cm due to the volatilization of boron in boron dopant-3And borosilicate glass (BSG) is formed above the doped layer on the surface of the n-type silicon wafer.
4) And removing the borosilicate glass generated on the surface of the n-type silicon wafer in the high-temperature propulsion process by chemical etching. Specifically, hydrofluoric acid can be used for etching, and the hydrofluoric acid etching process conditions are that the concentration of the hydrofluoric acid is 5-15% and the cleaning time is 10-30 min.
5) And (3) alkali texturing is carried out on the n-type silicon wafer cleaned by hydrofluoric acid, uneven p-type lightly doped layers which are formed in other areas outside the area of the n-type silicon wafer surface covering the boron dopant and are formed due to volatilization of boron in the boron dopant are removed by etching, and random pyramid-shaped textured surfaces are formed. In the process, the local p-type heavily doped region and the surface topography thereof are still preserved. The alkali texturing condition is as follows: the temperature of the alkali wool making liquid is 50-80 ℃, the wool making time is 5-10min, the concentration of KOH or NaOH is 2-5%, and the concentration of the auxiliary chemical for wool making is 0.05-2%. The auxiliary texturing chemical is a texturing (alkali texturing) additive, generally refers to a mixture mainly containing isopropanol, can enhance the various anisotropic ratios of alkali corrosion in the texturing process and improve the texturing effect, and the texturing additive is a conventional texturing additive in the photovoltaic industry. After the alkali texturing is finished, the height of the local p-type heavily doped region is 0.5-2um higher than that of the other textured regions which are not covered with the boron dopant. The selected texturing conditions finally determine the surface topography of the lightly doped region of the battery.
6) And carrying out boron doping on the n-type silicon wafer subjected to alkali texturing to form a p-type lightly doped region on the front surface of the n-type silicon wafer. Optionally, p-type light doping of the n-type silicon wafer is achieved through methods such as boron tribromide tubular boron diffusion, boron ion implantation, vapor phase chemical deposition and the like, and meanwhile, a layer of borosilicate glass is formed on the surface of the n-type silicon wafer. The surface concentration of boron element in the lightly doped region is lower than that in the heavily doped region, the junction depth is 0.3-1um, and the sheet resistance is 80-500 omega/□.
7) And (3) carrying out back polishing on the n-type silicon wafer subjected to the p-type light doping in the last step, etching to remove the p-type doping layer formed by the back and the edge of the silicon wafer due to the winding and expansion in the p-type light doping process, and forming a polishing morphology on the back of the silicon wafer. The method can be realized by an alkali polishing etching or acid etching method by adopting a water floating method, and borosilicate glass on the front side of the silicon wafer is still reserved after etching so as to block a doped layer on the back side of the n-type silicon wafer.
The alkali polishing and etching mode is as follows: firstly, removing borosilicate glass on the back of the silicon wafer by using a hydrofluoric acid water bleaching method, and then polishing the back of the silicon wafer by using a potassium hydroxide or sodium hydroxide aqueous solution, wherein the alkali concentration is 3-15%, the solution temperature is 50-80 ℃, and the time is 30-600 s.
Wherein, the acid etching mode is as follows: and corroding the back of the silicon wafer by using a method of rinsing the mixed solution of hydrofluoric acid and nitric acid on water, wherein the concentration of the hydrofluoric acid is 4-14%, the concentration of the nitric acid is 15-40%, the temperature of the solution is 2-20 ℃, and the etching time is 3-60 s.
8) Alternatively, the back side doped layer can be a phosphorus-doped full-area back field structure (n-type PERT cell structure), a local phosphorus-doped back field structure (n-type PER L cell structure) or a tunneling oxidation passivation contact structure (n-type TOPCon cell structure).
If a phosphorus-doped full-area back field structure is selected, the method can be realized by selecting tubular phosphorus diffusion, phosphorus source spin coating, phosphorus ion implantation and vapor phase chemical deposition. The sheet resistance of the full back field phosphorus diffusion is 20-100 omega/□.
If the local back field structure doped with phosphorus is selected, the method can be realized by selecting phosphorus dopant, phosphorus ion implantation and mask etching. The sheet resistance of the local phosphorus diffusion is 15-80 omega/□.
If the tunneling oxidation passivation contact structure is selected, the tunneling oxidation passivation contact structure comprises an ultrathin tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer.
Alternatively, the ultra-thin tunneling oxide layer can be fabricated by thermal nitric acid oxidation, ozone oxidation, thermal oxidation, plasma enhanced chemical vapor deposition, or the like. The thickness of the ultrathin tunneling oxide layer is 1-2nm, and the refractive index is about 1.45-1.5.
Optionally, the preparation method of the phosphorus-doped polysilicon layer mainly has two preparation methods, which are not limited to this. The first technical route is to deposit intrinsic amorphous silicon by processes such as low-pressure chemical vapor deposition, plasma enhanced vapor deposition or physical vapor deposition; then, phosphorus oxychloride (POCl3) is adopted for diffusion, the full conversion from amorphous silicon to polysilicon is completed in the diffusion, and the phosphorus doping in the polysilicon film is also completed; ion implantation of phosphorus (PH3) followed by a high temperature anneal may also be used, in which a sufficient conversion of amorphous silicon to polysilicon is accomplished, as well as a sufficient activation of the phosphorus doping and redistribution within the polysilicon film. The second technical route is that when amorphous silicon is subjected to plasma enhanced vapor deposition, phosphorus is doped online by introducing phosphine (PH3), and specific process gases are silane (SiH 4), hydrogen, phosphine and nitrogen. Then high-temperature annealing is carried out, and full conversion from amorphous silicon to polycrystalline silicon, full activation of phosphorus doping and redistribution in the polycrystalline silicon film are completed in the annealing. The annealing process can adopt furnace tube annealing, chain furnace rapid heat treatment annealing and the like, and the selection of the annealing process parameters needs to be compatible with the amorphousSufficient conversion of silicon to polysilicon, and sufficient activation and redistribution of the doped phosphorus within the polysilicon film. After the preparation is completed, the thickness of the phosphorus-doped polycrystalline silicon film is 30-200nm, and the phosphorus doping concentration is 1E19-1E21cm-3。
9) And manufacturing a back passivation layer on the n-type silicon wafer back doped layer. The back passivation layer can be a layer of silicon nitride deposited on the back of the silicon wafer by a plasma enhanced chemical vapor deposition method, the thickness of the silicon nitride layer is 80-150nm, and the refractive index is 1.9-2.25. And manufacturing a passivation antireflection layer on the front surface of the n-type silicon wafer, wherein the passivation antireflection layer can be one or more of aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, magnesium fluoride and zinc sulfide. Optionally, the front passivation antireflective layer has a thickness of 50-200nm and a refractive index of 1.5-2.3.
10) And manufacturing metal electrodes on the front surface and the back surface of the n-type silicon wafer. The front surface of the n-type silicon wafer can be a grid-line-shaped metal electrode, and the front metal electrode is positioned right above the local p-type heavily doped region; the back electrode of the n-type silicon wafer can also be a grid-line-shaped metal electrode, wherein if the back doped layer is of a back local phosphorus back field structure, the back metal electrode is positioned right above the back local phosphorus back field region. The manufacturing method of the metal electrode can be realized by selecting methods such as electroplating, evaporation, screen printing and the like, and the invention can match the surface appearance of the heavily doped region according to the manufacturing method selected by the front metal electrode, namely, the specific method of the surface structuring treatment in the step 1) is determined according to the electrode manufacturing method adopted in the step.
Thus, the n-type cell is completed, and the structure of the n-type cell is shown in fig. 2, which mainly comprises: the device comprises a monocrystalline n-type silicon wafer (n-type silicon substrate) 1, a local p-type heavily doped region 2, a p-type lightly doped region, a front passivation anti-reflection layer 4, a front metal electrode 5, an n-type doped layer 6 (which can be a full-area phosphorus back field structure, a local phosphorus back field structure, a tunneling oxidation passivation contact structure), a back passivation layer 7 and a back metal electrode 8.
The invention utilizes the boron dopant used in the step 2) and the high-temperature propelling process of the step 3) to form a local p-type heavily doped region on the front surface of the silicon wafer. And 2) boron in the boron dopant printed on the surface of the silicon wafer can diffuse into the silicon wafer and can diffuse into the atmosphere in the high-temperature propelling process of the step 3), the boron diffused into the atmosphere can diffuse into the region without printing the boron dopant to form secondary diffusion, the concentration of the boron doped in the region without printing the boron dopant is extremely uneven, the relationship between the concentration distribution and the position is large, and the closer to the region with printing the boron dopant, the higher the concentration of the boron on the surface of the silicon wafer is. This non-uniform boron doping has a negative effect on carrier collection and also increases the rate of carrier recombination in this region.
The boron dopant used in the step 2) should meet the requirement of high boron content as much as possible, and the concentration of boron element in the heavily doped region on the surface of the silicon wafer after the high-temperature propulsion in the step 3) reaches 7E19cm-3This is so that step 5) can be carried out smoothly, otherwise the heavily doped regions may be etched away in the step 5) of alkali etching. Meanwhile, the boron dopant used in step 2) needs to satisfy low volatility to reduce the light diffusion concentration formed in the unprinted boron dopant region. For example, "NanoGram" silicon slurry available from Diricho corporation may be used. In general, the light doping concentration of the region not printed with boron dopant is lower by 1 order of magnitude or more than the boron doping concentration of the region printed with boron paste, and is usually 5E19cm-3 or less, because boron in boron dopant volatilizes.
And 5) etching and removing the light diffusion layer formed by volatilizing boron in the boron dopant outside the local p-type heavily doped region on the surface of the silicon wafer by utilizing alkali texturing. Doping of the printed boron dopant region after the high temperature advance of step 3) is heavily doped (boron surface concentration 7E19 cm)-3Above), the reaction rate of silicon and alkaline chemical solution is lower and lower with the increase of boron doping concentration on the surface of the crystalline silicon (the reaction rate of the heavily boron-doped crystalline silicon in the alkaline down liquid can be lower by more than 1 order of magnitude than that of the crystalline silicon without boron doping in the alkaline down liquid). When the boron doping concentration of the surface of the crystalline silicon reaches 7E19cm-3After the above, the reaction speed of the crystalline silicon and the alkaline chemical solution is extremely slow, and only a thin layer of the surface of the local p-type heavily doped region is corroded after the alkaline etching in the step 5). While the areas not printed with boron dopant during the high temperature advancing process of step 3) are due to the boron dopantThe light diffusion layer formed by boron volatilization is easy to corrode in alkaline solution due to the low concentration of boron, so that boron in the area is completely etched and removed after the alkaline texturing in the step 5) and a textured surface structure is regenerated again, the textured surface generation process cannot affect the local p-type heavily doped area, and the surface appearances of the textured surface structure and the local p-type heavily doped area in the area can be independently controlled.
The invention will be further described with reference to the accompanying drawings and specific examples, which are provided as an illustration of the method of carrying out the invention and are intended to facilitate understanding.
Example 1: a method for preparing an n-type cell with a back surface doping layer of a back surface field structure (namely the back surface structure of the n-type PERT cell) doped with phosphorus in a full area. The method mainly comprises the following steps:
1) an n-type monocrystalline silicon wafer with a (100) crystal orientation is subjected to texturing by using an alkali texturing method, so that a textured structure with a random pyramid morphology is formed on the front surface of the n-type silicon wafer.
2) The front surface of the n-type silicon wafer after texturing is partially covered with boron dopant by using a screen printing method, the boron dopant is distributed in a grid line shape with equal intervals, the width of the grid line is about 40 mu m, the interval of the grid line is about 1.5mm, and the boron dopant is partially covered under a metal front electrode to be printed on the surface of the silicon wafer. The boron dopant used on the surface of the n-type silicon wafer is boron ink.
3) And putting the n-type silicon wafer partially covered with the boron dopant into a high-temperature furnace for propelling to form a partial p-type heavily doped region on the front surface. The propulsion process scheme can be set as follows: the propulsion temperature is 930 ℃, the propulsion time is 120min, the nitrogen flow is 20000sccm, and the oxygen flow is 0 sccm. The surface concentration of boron element in the partial p-type heavily doped region is 6E21cm after the drive-in process is finished-3The junction depth is 1.2 um. After the drive-in process is completed, a p-type lightly doped concentration layer formed by volatilization of boron in the boron dopant is formed in a region outside the local p-type heavily doped region, and the surface concentration of the p-type lightly doped concentration layer is lower than 1E19cm-3And borosilicate glass is formed above the doped layer on the surface of the n-type silicon wafer.
4) And removing the borosilicate glass generated on the surface of the n-type silicon wafer in the high-temperature propulsion by using a hydrofluoric acid etching method. The hydrofluoric acid cleaning condition is that the concentration of the hydrofluoric acid is 5%, and the cleaning time is 30 min.
5) And (3) alkali texturing is carried out on the n-type silicon wafer cleaned by hydrofluoric acid, a p-type light doping concentration layer formed at the position of the n-type silicon wafer surface, which is not covered by the boron doping agent, due to volatilization of boron in the boron doping agent is etched to remove, a random pyramid-shaped textured surface is formed in the region, and meanwhile, a local p-type heavy doping region and the surface appearance of the region are still kept. The alkali texturing process conditions are as follows: the temperature of the alkali wool making liquid is 60 ℃, the wool making time is 10min, the KOH concentration is 2 percent, and the concentration of the wool making auxiliary chemical is 0.05 percent. After the alkali texturing is finished, the height of the local p-type heavily doped region is 0.5um higher than that of other boron-doped textured regions which are not covered.
6) And lightly doping the n-type silicon wafer subjected to alkali texturing by using a boron tribromide tubular boron diffusion method, forming a lightly doped p-type emitter junction on the front surface of the n-type silicon wafer, and forming a layer of borosilicate glass on the surface of the n-type silicon wafer. The surface concentration of the lightly doped region is 2E19cm-3The junction depth is 0.6 um.
7) And (3) polishing the back surface of the n-type silicon wafer after the step 6) is finished by using an acid etching method, etching to remove the p-type doping layer which is wound and expanded and is carried out on the back surface and the edge of the silicon wafer in the p-type light doping process in the step 6), and forming a polished surface on the back surface of the silicon wafer.
The acid etching conditions were as follows: and performing single-side etching on the back side of the silicon wafer by using a method of rinsing the mixed solution of hydrofluoric acid and nitric acid on water, wherein the concentration of the hydrofluoric acid is 4 percent, the concentration of the nitric acid is 40 percent, the temperature of the solution is 8 ℃, the etching time is 10s, and the borosilicate glass on the front side of the silicon wafer is still retained after the single-side acid etching.
8) And manufacturing a back surface doping layer on the back surface of the n-type silicon wafer by using a tubular phosphorus oxychloride diffusion method. The back doped layer is a full back field phosphorus diffused junction (n-type PERT battery structure). The sheet resistance of the full back field phosphor diffused junction was 40 Ω/□. After the back doping layer is manufactured, a part of phosphorus is doped to the borosilicate glass on the front side of the n-type silicon wafer in a surrounding mode.
9) And manufacturing a back passivation layer on the n-type silicon wafer back doped layer. The back passivation layer can be a layer of silicon nitride deposited on the back of the silicon wafer by a plasma enhanced chemical vapor deposition method, the thickness of the silicon nitride layer is 100nm, and the refractive index is 1.9.
10) And manufacturing a front passivation antireflection layer on the front surface of the n-type silicon wafer, wherein the passivation antireflection layer can be a laminated layer of aluminum oxide and silicon nitride, and the aluminum oxide layer is positioned below the silicon nitride layer, wherein the aluminum oxide is 5nm, and the silicon nitride is 70 nm.
11) And manufacturing metal electrodes on the front surface and the back surface of the n-type silicon wafer by using a screen printing method. The front metal electrode is made of silver-aluminum paste, the electrode patterns are distributed in a grid line shape at equal intervals, the width of each grid line is about 25 mu m, the interval between the grid lines is about 1.5mm, and the front metal electrode is positioned right above the local p-type heavily doped region; wherein back metal electrode adopts silver thick liquid, and its pattern design is the grid line form distribution of equidistant, and grid line width is about 30um, and the grid line interval is about 1 mm.
In the n-type cell provided by this embodiment, the cell front emitter junction is a selective emitter junction composed of a p-type lightly doped region and a p-type heavily doped region that is higher than the p-type lightly doped region and deeper than the lightly doped region, and the cell back doped layer is a full-area phosphorus back field structure (n-type PERT cell structure). Compared with other traditional n-type PERT batteries, the n-type battery provided by the embodiment of the invention can effectively reduce the contact resistance of the front surface of the battery and the recombination loss of photon-generated carriers on the front surface of the battery, thereby improving the performance of the battery; and the surface appearance of the heavily doped region of the selective emitter junction on the front surface of the battery is a suede structure of a random pyramid, which is beneficial to the ohmic contact performance of a metal semiconductor formed by a screen printing metallization method.
Embodiment 2 a method for manufacturing an n-type cell with a back-doped layer having a back-side local phosphorus back-field structure (i.e., a back-side structure of an n-type PER L cell), the method mainly includes the following steps:
1) polishing an n-type monocrystalline silicon wafer with a (100) crystal orientation by using a polishing method to form a polished surface on the front surface of the n-type silicon wafer.
2) And partially covering the front surface of the polished n-type silicon wafer with a boron dopant by using a printing method, wherein the boron dopant is distributed in a grid line shape with equal intervals, the width of the grid line is about 20 mu m, the interval of the grid line is about 1mm, and the partially covered boron dopant is positioned right below the front metal electrode on the surface of the silicon wafer. The boron dopant used on the surface of the n-type silicon wafer is boron-doped silicon powder.
3) And putting the n-type silicon wafer partially covered with the boron dopant into a high-temperature furnace for propulsion to form a local p-type heavily doped region. The propulsion process scheme can be set as follows: the propulsion temperature is 1080 ℃, the propulsion time is 120min, the nitrogen flow is 10000sccm, and the oxygen flow is 5000 sccm. The surface concentration of boron element in the partial p-type heavily doped region after the drive-in process is finished is 8E21cm-3The junction depth is 3 um. The surface concentration of boron in the light diffusion layer formed by volatilization of boron in the boron dopant outside the local p-type heavily doped region after the drive-in process is finished is lower than 1E19cm-3And borosilicate glass is formed above the doped layer on the surface of the n-type silicon wafer.
4) And removing the borosilicate glass generated on the surface of the n-type silicon wafer in the high-temperature propulsion by using a hydrofluoric acid etching method. The hydrofluoric acid etching process conditions are that the concentration of hydrofluoric acid is 12% and the cleaning time is 10 min.
5) And (3) alkali texturing is carried out on the n-type silicon wafer cleaned by hydrofluoric acid, a p-type light doping concentration layer formed at the position of the n-type silicon wafer surface, which is not covered by the boron doping agent, due to volatilization of boron in the boron doping agent is etched to remove, a random pyramid-shaped textured surface is formed in the region, and meanwhile, a local p-type heavy doping region and the surface appearance of the region are still kept. The alkali texturing condition is as follows: the temperature of the alkali wool making liquid is 70 ℃, the wool making time is 7min, the KOH concentration is 3 percent, and the concentration of the wool making auxiliary chemical is 0.05 percent. After the alkali texturing is finished, the height of the local p-type heavily doped region is 2um higher than that of other boron-doped textured regions which are not covered.
6) And lightly doping the n-type silicon wafer subjected to alkali texturing by using a boron tribromide tubular boron diffusion method, forming a lightly doped p-type emitter junction on the front surface of the n-type silicon wafer, and forming a layer of borosilicate glass on the surface of the n-type silicon wafer. The surface concentration of the lightly doped region is 3E19cm-3The junction depth is 0.7 um.
7) And (3) carrying out back polishing on the n-type silicon wafer obtained in the step 6) by using an alkali polishing method, etching to remove the p-type doping layer which extends around the back and the edge of the silicon wafer in the p-type light doping process in the step 6), and forming a polished surface shape on the back of the silicon wafer. The alkali polishing process conditions are as follows: firstly, removing the borosilicate glass on the back of the silicon wafer by using a hydrofluoric acid water bleaching method, and then polishing the back of the silicon wafer by using a potassium hydroxide solution, wherein the alkali concentration is 3%, the solution temperature is 80 ℃, and the time is 300 s. The borosilicate glass on the front side of the silicon wafer is still remained after polishing.
8) The back doping layer is a local phosphorus back field structure (namely the back structure of an n-type PER L battery) which is distributed in an equidistant grid line shape, the doping of the local phosphorus back field is realized by adopting a mask plate technology in the ion implantation, the width of the grid line is 30 mu m, the distance of the grid line is 1mm, and the square resistance of the local phosphorus back field is 20 omega/□.
9) And manufacturing a back passivation layer on the n-type silicon wafer back doped layer. The back passivation layer can be a layer of silicon oxynitride deposited on the back of the silicon wafer by a plasma enhanced chemical vapor deposition method, the thickness of the silicon oxynitride is 130nm, and the refractive index of the silicon oxynitride is 1.7.
10) And manufacturing a passivation antireflection layer on the front surface of the n-type silicon wafer, wherein the passivation antireflection layer can be a laminated layer of aluminum oxide and silicon nitride, and the aluminum oxide layer is positioned below the silicon nitride layer, wherein the aluminum oxide layer is 5nm, and the silicon nitride layer is 70 nm.
11) And manufacturing metal electrodes on the front surface and the back surface of the n-type silicon wafer by using an evaporation method. The front metal electrode is made of aluminum, the patterns are designed to be distributed in a grid line shape at equal intervals, the width of each grid line is about 20 mu m, the interval between the grid lines is about 1mm, and the front metal electrode is positioned right above the local p-type heavily doped region; the back metal electrode is made of silver, the pattern design is made of grid lines distributed at equal intervals, the width of each grid line is about 30um, the interval between the grid lines is about 1mm, and the back metal electrode is located right above the local phosphorus back field area.
The embodiment provides an n-type battery, wherein a front emitter junction of the battery is a selective emitter junction composed of a p-type lightly doped region and a p-type heavily doped region which is higher than the p-type lightly doped region and deeper than the lightly doped region, a back doped layer of the battery is a back local phosphorus back field structure (namely a back structure of the n-type PER L battery), compared with other traditional n-type PER L batteries, the n-type battery can effectively reduce contact resistance of the front of the battery and recombination loss of photo-generated carriers on the front of the battery, and further improves battery performance, and the surface appearance of the heavily doped region of the selective emitter junction is a polished structure, so that the contact performance formed by a metallization method for vapor deposition is facilitated.
Example 3: a method for preparing an n-type cell with a back doped layer of a tunneling oxidation passivation contact structure (namely a back structure of the n-type TOPCon cell). The method mainly comprises the following steps:
1) an n-type monocrystalline silicon wafer with a (100) crystal orientation is subjected to texturing by using an alkali texturing method, so that a textured structure with a random pyramid morphology is formed on the front surface of the n-type silicon wafer.
2) The front surface of the n-type silicon wafer after texturing is partially covered with boron dopant by using a screen printing method, the boron dopant is distributed in a grid line shape with equal intervals, the width of the grid line is about 40 mu m, the interval of the grid line is about 1.5mm, and the partially covered boron dopant is positioned under the front electrode to be printed on the surface of the silicon wafer. The boron dopant used on the surface of the n-type silicon wafer is boron-containing slurry.
3) And putting the n-type silicon wafer partially covered with the boron dopant into a high-temperature furnace for propulsion to form a local p-type heavily doped region. The propulsion process scheme can be set as follows: the propulsion temperature is 930 ℃, the propulsion time is 120min, the nitrogen flow is 20000sccm, and the oxygen flow is 0 sccm. The surface concentration of boron element in the partial p-type heavily doped region is 6E21cm after the drive-in process is finished-3The junction depth is 1.2 um. In a p-type lightly doped concentration layer formed at the position which is not covered with the boron dopant region and is outside the local p-type heavily doped region after the advancing process is finished, the surface concentration of boron is lower than 1E19cm-3. And borosilicate glass is formed above the doped layer on the surface of the n-type silicon wafer.
4) And removing the borosilicate glass generated on the surface of the n-type silicon wafer in the high-temperature propulsion by using a hydrofluoric acid etching method. The hydrofluoric acid etching process conditions are that the concentration of hydrofluoric acid is 5% and the cleaning time is 30 min.
5) And (3) carrying out alkali texturing on the n-type silicon wafer cleaned by hydrofluoric acid, etching to remove a p-type light doping concentration layer formed at the position of the front surface of the n-type silicon wafer, which is not covered by the boron doping agent, due to volatilization of boron in the boron doping agent, forming a textured surface with a random pyramid shape in the regions, and simultaneously keeping the local p-type heavy doping region and the surface shape thereof. The alkali texturing condition is as follows: the temperature of the alkali wool making liquid is 60 ℃, the wool making time is 10min, the KOH concentration is 2 percent, and the concentration of the wool making auxiliary chemical is 0.05 percent. After the alkali texturing is finished, the height of the local p-type heavily doped region is 0.5um higher than that of other boron-doped textured regions which are not covered.
6) And lightly doping the n-type silicon wafer subjected to alkali texturing by using a boron tribromide tubular boron diffusion method, forming a lightly doped p-type emitter junction on the front surface of the n-type silicon wafer, and forming a layer of borosilicate glass on the surface of the n-type silicon wafer. The surface concentration of the lightly doped region is 2E19cm-3The junction depth is 0.5 um.
7) And (3) polishing the back surface of the n-type silicon wafer obtained in the step 6) by using an acid etching method, etching to remove the p-type doping layer which extends around the back surface and the edge of the silicon wafer in the p-type light doping process in the step 6), and forming a polished surface shape on the back surface of the silicon wafer. Wherein, the acid etching process conditions are as follows: etching the back of the silicon wafer by a method of rinsing the mixed solution of hydrofluoric acid and nitric acid on water, wherein the concentration of the hydrofluoric acid is 4%, the concentration of the nitric acid is 40%, the temperature of the solution is 8 ℃, the etching time is 10s, and the borosilicate glass on the front of the silicon wafer is still retained after acid etching.
8) And manufacturing a back doping layer on the back of the n-type silicon wafer. The back doped layer is a tunneling oxidation passivation contact structure (namely a back structure of the n-type TOPCon battery). The tunneling oxidation passivation contact structure comprises an ultrathin tunneling oxidation layer and a phosphorus-doped polycrystalline silicon layer, wherein the ultrathin tunneling oxidation layer is positioned below the phosphorus-doped polycrystalline silicon layer.
The ultrathin tunneling oxide layer is prepared by a thermal oxidation method, and the thickness of the ultrathin tunneling oxide layer is about 1.5 nm.
The preparation of the phosphorus-doped polycrystalline silicon layer comprises the steps of firstly preparing on-line phosphorus-doped amorphous silicon by a plasma enhanced chemical vapor deposition method, then crystallizing the amorphous silicon into polycrystalline silicon by thermal annealing, and simultaneously activating phosphorus doping and realizing redistribution in the polycrystalline silicon layer. The thickness of the phosphorus-doped polysilicon is about 150nm, and the phosphorus doping concentration is 2E20cm-3And the square resistance is 50 omega/□.
9) After the back doped layer is manufactured, a small amount of phosphorus doped polysilicon is deposited on the borosilicate glass on the front side of the n-type silicon wafer due to the phenomenon of plating. When the front borosilicate glass is etched by hydrofluoric acid, the front borosilicate glass can be etched and removed together, the hydrofluoric acid etching process condition is that the concentration of the hydrofluoric acid is 8%, and the cleaning time is 25 min.
10) On the basis of the tunneling oxidation passivation contact structure on the back surface of the n-type silicon wafer, a layer of silicon nitride is continuously prepared, and the preparation can be realized by a plasma enhanced chemical vapor deposition method. The silicon nitride thickness was 100nm and the refractive index was 2.05.
11) And manufacturing a passivation antireflection layer on the front surface of the n-type silicon wafer, wherein the passivation antireflection layer can be a laminated layer of aluminum oxide and silicon nitride, and the aluminum oxide layer is positioned below the silicon nitride layer, wherein the aluminum oxide layer is 5nm, and the silicon nitride layer is 70 nm.
12) And manufacturing metal electrodes on the front surface and the back surface of the n-type silicon wafer by using a screen printing method. The front metal electrode is made of silver paste, the pattern design is in grid line-shaped distribution with equal intervals, the width of each grid line is about 25 micrometers, the interval between the grid lines is about 1.5mm, and the front metal electrode is positioned right above the local p-type heavily doped region; wherein, back metal electrode adopts the silver thick liquid, and the pattern design adopts equidistant grid line form to distribute, and grid line width is about 30um, and the grid line interval is about 1 mm.
The present embodiment provides an n-type cell, in which the cell front emitter junction is a selective emitter junction composed of a p-type lightly doped region and a p-type heavily doped region that is higher than the p-type lightly doped region and deeper than the lightly doped region, and the cell back doped layer is a tunneling oxidation passivation contact structure (i.e., an n-type TOPCon cell back structure). Compared with the traditional n-type TOPCon battery, the n-type battery provided by the example can effectively reduce the contact resistance of the front surface of the battery and the recombination loss of photon-generated carriers on the front surface of the battery, and further improves the performance of the battery. The surface appearance of the selective emitter junction heavily doped region is a suede structure with a random pyramid appearance, and the metal semiconductor ohmic contact performance formed by a screen printing metallization method is facilitated.
Finally, the n-type cell and the method for manufacturing the same provided by the present invention are described in detail above. The principles and embodiments of the present invention have been described herein using specific examples, and the foregoing examples are merely illustrative of the principles and concepts of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims (10)

1. A preparation method of an n-type battery is characterized by comprising the following steps:
selecting a (100) crystal orientation n-type monocrystalline silicon wafer, and carrying out surface structuring treatment on the n-type monocrystalline silicon wafer to form a specific morphology on the surface of the silicon wafer;
partially covering the front surface of the n-type silicon wafer subjected to the structuring treatment with a boron dopant, and carrying out high-temperature propulsion on the n-type silicon wafer to form a local p-type heavily doped region on the front surface of the n-type silicon wafer, wherein the surface concentration of boron in the local p-type heavily doped region is 7E19-1E22cm-3；
Removing borosilicate glass formed on the surface of the n-type silicon wafer in the high-temperature propelling process, then carrying out alkali texturing on the n-type silicon wafer, etching a light diffusion layer formed in a crystalline silicon area which is not covered with the boron dopant in the high-temperature propelling process and is formed due to volatilization of boron elements in the boron dopant, and forming a textured structure on the surface of the crystalline silicon area, wherein in the process, the local p-type heavily doped area still retains the original surface appearance;
lightly doping boron on the front surface of the n-type silicon wafer subjected to alkali texturing to form a p-type lightly doped region, wherein the surface concentration of boron in the p-type lightly doped region is lower than that in the local p-type heavily doped region, and the height of the boron in the p-type lightly doped region is lower than that in the local p-type heavily doped region;
manufacturing an n-type doping layer on the back surface of the n-type silicon wafer, wherein the n-type doping layer is any one of a full-area phosphorus-doped back field structure, a local phosphorus-doped back field structure and a passivation contact structure;
manufacturing a passivation antireflection layer on the front side of the n-type silicon wafer, and manufacturing a passivation layer on the back side of the n-type silicon wafer;
and manufacturing metal electrodes on the front surface and the back surface of the n-type silicon wafer, wherein the front metal electrode corresponds to the local p-type heavily doped region.
2. The method for preparing the n-type cell according to claim 1, wherein the front surface of the n-type silicon wafer after the structuring treatment is partially covered with boron dopant by adopting a screen printing or printing mode; the boron dopants include, but are not limited to, boron-containing slurries, boron inks, and boron-doped silicon powders.
3. The method of manufacturing an n-type cell according to claim 1, wherein the alkali texturing conditions are: the alkaline wool making solution is 2-5% potassium hydroxide or sodium hydroxide solution, and has a temperature of 50-80 deg.C and wool making time of 5-10 min.
4. The method for preparing an n-type cell according to claim 1, wherein after the alkali texturing is finished, the height of the local p-type heavily doped region is 0.5-2um higher than that of the p-type lightly doped region of the textured structure.
5. The method of claim 1, wherein the junction depth of the localized heavily p-doped region is deeper than the lightly p-doped region.
6. The method of claim 1, wherein the high temperature drive-in process scheme is: the propulsion temperature is 750-; after the high-temperature propelling process is finished, the junction depth of the local p-type heavily doped region is 1-3um, and the square resistance is 20-80 omega/□.
7. The method of claim 6, wherein the light doping is performed by any one of boron tribromide tubular boron diffusion, boron ion implantation and vapor phase chemical deposition, and the p-type lightly doped region has a junction depth of 0.3-1um and a sheet resistance of 100-250 Ω/□.
8. The method of claim 1, wherein the localized heavily p-doped region is patterned, the pattern corresponding to a front side metal electrode pattern.
9. The method of claim 1, wherein the metal electrode is formed by screen printing, electroplating or physical vapor deposition; when the metal electrode is manufactured in an electroplating or physical vapor deposition mode, the surface structuring treatment adopts a polishing mode, so that a polishing structure is formed in the local p-type heavily doped region; when the metal electrode is manufactured by screen printing, the surface structuring treatment adopts a texturing mode, so that a texturing structure is formed in the local p-type heavily doped region.
10. An n-type cell prepared by the method of any one of claims 1 to 9, comprising:
a monocrystalline n-type silicon wafer;
the p-type doping layer is positioned on the front surface of the n-type silicon wafer and comprises a local p-type heavily doped region and a p-type lightly doped region, and the height of the local p-type heavily doped region is 0.5-2um higher than that of other lightly doped p-type emitter junction regions; the junction depth of the local p-type heavily doped region is 1-3um, and the square resistance is 20-80 omega/□; the junction depth of the p-type lightly doped region is 0.3-1um, and the square resistance is 80-500 omega/□;
the n-type doping layer is positioned on the back surface of the n-type silicon wafer, and the n-type doping layer is any one of a full-area phosphorus-doped back field structure, a local phosphorus-doped back field structure and a passivation contact structure;
the front passivation antireflection layer is positioned on the p-type doping layer;
a back passivation layer located on the n-type doped layer;
the front metal electrode is positioned on the front passivation antireflection layer, and the back metal electrode is positioned on the back passivation layer, and the front metal electrode corresponds to the position of the local p-type heavily doped region.
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CN115241300A (en) * 2021-04-22 2022-10-25 苏州阿特斯阳光电力科技有限公司 Solar cell and preparation method thereof
CN115458612A (en) * 2022-10-27 2022-12-09 通威太阳能(眉山)有限公司 Solar cell and preparation method thereof
EP4287267A1 (en) * 2022-06-01 2023-12-06 Jinko Solar (Haining) Co., Ltd. Photovoltaic cell and photovoltaic module
CN117199190A (en) * 2023-09-27 2023-12-08 淮安捷泰新能源科技有限公司 Manufacturing method of N-TOPCON battery

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100267187A1 (en) * 2007-12-13 2010-10-21 Yasushi Funakoshi Method for manufacturing solar cell
CN103066164A (en) * 2013-01-31 2013-04-24 英利集团有限公司 N-type solar battery and manufacturing method thereof
CN103296103A (en) * 2012-02-29 2013-09-11 日本琵维吉咨询株式会社 Solar cell unit and manufacturing method thereof
CN107482079A (en) * 2016-06-02 2017-12-15 上海神舟新能源发展有限公司 Selective emitter junction and tunnel oxide high-efficiency N-type battery preparation method
CN110098284A (en) * 2019-05-13 2019-08-06 浙江正泰太阳能科技有限公司 A kind of N-type selective emitter solar battery and its manufacturing method
CN110707178A (en) * 2019-08-29 2020-01-17 晶科能源科技（海宁）有限公司 Preparation method of N-type solar cell boron-diffusion SE structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100267187A1 (en) * 2007-12-13 2010-10-21 Yasushi Funakoshi Method for manufacturing solar cell
CN103296103A (en) * 2012-02-29 2013-09-11 日本琵维吉咨询株式会社 Solar cell unit and manufacturing method thereof
CN103066164A (en) * 2013-01-31 2013-04-24 英利集团有限公司 N-type solar battery and manufacturing method thereof
CN107482079A (en) * 2016-06-02 2017-12-15 上海神舟新能源发展有限公司 Selective emitter junction and tunnel oxide high-efficiency N-type battery preparation method
CN110098284A (en) * 2019-05-13 2019-08-06 浙江正泰太阳能科技有限公司 A kind of N-type selective emitter solar battery and its manufacturing method
CN110707178A (en) * 2019-08-29 2020-01-17 晶科能源科技（海宁）有限公司 Preparation method of N-type solar cell boron-diffusion SE structure

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111987188A (en) * 2020-08-25 2020-11-24 常州时创能源股份有限公司 Preparation method of passivated contact battery
CN112768562A (en) * 2021-01-11 2021-05-07 东方日升新能源股份有限公司 Method for removing edge wrap plating of solar cell and method for manufacturing solar cell
CN115241300A (en) * 2021-04-22 2022-10-25 苏州阿特斯阳光电力科技有限公司 Solar cell and preparation method thereof
CN115241300B (en) * 2021-04-22 2023-11-17 苏州阿特斯阳光电力科技有限公司 Solar cell and preparation method thereof
CN114597285A (en) * 2022-02-24 2022-06-07 浙江晶科能源有限公司 Preparation method of solar cell, solar cell and photovoltaic module
CN114597285B (en) * 2022-02-24 2023-11-07 浙江晶科能源有限公司 Solar cell manufacturing method, solar cell and photovoltaic module
EP4287267A1 (en) * 2022-06-01 2023-12-06 Jinko Solar (Haining) Co., Ltd. Photovoltaic cell and photovoltaic module
NL2033699A (en) * 2022-06-01 2023-12-12 Jinko Solar Haining Co Ltd Photovoltaic cell and photovoltaic module
JP2023177241A (en) * 2022-06-01 2023-12-13 晶科能源（海▲寧▼）有限公司 Solar cell and photovoltaic module
JP7515650B2 (en) 2022-06-01 2024-07-12 晶科能源（海▲寧▼）有限公司 Solar Cells and Photovoltaic Modules
CN115458612A (en) * 2022-10-27 2022-12-09 通威太阳能(眉山)有限公司 Solar cell and preparation method thereof
CN117199190A (en) * 2023-09-27 2023-12-08 淮安捷泰新能源科技有限公司 Manufacturing method of N-TOPCON battery

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