CN112768562A - Method for removing edge wrap plating of solar cell and method for manufacturing solar cell - Google Patents

Method for removing edge wrap plating of solar cell and method for manufacturing solar cell Download PDF

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Publication number
CN112768562A
CN112768562A CN202110032636.4A CN202110032636A CN112768562A CN 112768562 A CN112768562 A CN 112768562A CN 202110032636 A CN202110032636 A CN 202110032636A CN 112768562 A CN112768562 A CN 112768562A
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layer
edge
plating
solar cell
phosphorus
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庄魏辰
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Risen Energy Co Ltd
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Risen Energy Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

A method for removing the edge of a solar cell by winding plating and a method for manufacturing the solar cell belong to the technical field of solar cells. The method for removing the edge wrap-around plating of the solar cell comprises the following steps: forming a boron doped layer and a borosilicate glass layer on the front surface of the textured N-type silicon wafer; sequentially forming a tunneling oxide layer and a phosphorus-doped amorphous silicon layer on the back of the N-type silicon wafer or forming a phosphorus-doped layer on the back of the N-type silicon wafer, and performing edge-wrap plating on the phosphorus-doped amorphous silicon layer or the phosphorus-doped layer to the side edge of the N-type silicon wafer and the surface edge of the borosilicate glass layer in the process; and etching and removing the edge surrounding coating by adopting a plasma gas etching method. The edge winding plating can be effectively removed, and the PN junction is not easy to damage.

Description

Method for removing edge wrap plating of solar cell and method for manufacturing solar cell
Technical Field
The application relates to the technical field of solar cells, in particular to a method for removing edge wrap-plating of a solar cell and a method for manufacturing the solar cell.
Background
The solar cell has more industrial procedures, a Topcon cell needs to manufacture a phosphorus-doped amorphous silicon layer on the back of an N-type silicon wafer, a PERT cell needs to manufacture a phosphorus-containing diffusion layer on the back of the N-type silicon wafer, when the phosphorus-containing phosphorus-doped amorphous silicon layer and the phosphorus-containing diffusion layer are manufactured, the problem of plating around can be inevitably generated on the surface of a front PN junction and the edge of a side surface, phosphorus is plated around to the surface of the front PN junction and can be contacted with a front boron element to cause electric leakage, and therefore plating around needs to be removed.
In the prior art, a chemical solvent is generally used for removing the wraparound plating, for example, some mixed solutions of alkali and additives are used for removing the wraparound plating, some mixed solutions are used for removing the wraparound plating, but the wraparound plating formed on the surface of the front PN junction in the solar cell manufacturing process is generally small in area, and when the wraparound plating on the surface of the front PN junction is removed by the chemical solvent, the chemical solvent has certain fluidity, so that the PN junction is easily damaged to cause large-degree electric leakage.
Disclosure of Invention
The application provides a method for removing edge wrap-around plating of a solar cell and a method for manufacturing the solar cell, which can effectively remove the edge wrap-around plating and are not easy to damage PN junctions.
The embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a method for removing edge wrap-plating of a solar cell, including:
forming a boron doped layer and a borosilicate glass layer on the front surface of the textured N-type silicon wafer;
sequentially forming a tunneling oxide layer and a phosphorus-doped amorphous silicon layer on the back of the N-type silicon wafer or forming a phosphorus-doped layer on the back of the N-type silicon wafer, and performing edge-wrap plating on the phosphorus-doped amorphous silicon layer or the phosphorus-doped layer to the side edge of the N-type silicon wafer and the surface edge of the borosilicate glass layer in the process;
and etching and removing the edge surrounding coating by adopting a plasma gas etching method.
In a second aspect, an embodiment of the present application provides a method for manufacturing a solar cell, including the method for removing the edge wrap-around plating of the solar cell of the first aspect.
The method for removing the edge of the solar cell in the round plating mode and the method for manufacturing the solar cell have the advantages that:
when a phosphorus-doped amorphous silicon layer is formed on the back surface of the N-type silicon wafer, the phosphorus-doped amorphous silicon layer inevitably winds and plates to the side edge of the N-type silicon wafer and the surface edge of the borosilicate glass layer to form an edge winding and plating layer in the process; when the phosphorus doped layer is formed on the back of the N-type silicon wafer, the phosphorus doped layer inevitably forms an edge winding coating layer around the side edge of the N-type silicon wafer and the surface edge of the borosilicate glass layer, and the edge winding coating layer is removed by a plasma gas etching method, so that the removal is more accurate, and the PN junction is not easy to damage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of an N-type silicon wafer after texturing in a solar cell edge plating removal method according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of the solar cell edge wrap-around plating removal method according to the embodiment of the present application after being processed in step S1;
fig. 3 is a schematic structural diagram of the solar cell edge wrap-around plating removing method according to the embodiment of the present application after being processed in step S2;
fig. 4 is another schematic structural diagram of the solar cell edge wrap-around plating removing method according to the embodiment of the present application after being processed in step S2;
fig. 5 is a schematic structural diagram of the solar cell edge wrap-around plating removing method according to the embodiment of the present application after being processed in step S3;
fig. 6 is another schematic structural diagram of the solar cell edge wrap-around plating removing method according to the embodiment of the present application after being processed in step S3.
Icon: 11-N type silicon wafer; a 12-boron doped layer; 13-a borosilicate glass layer; 14-tunneling oxide layer; 15-phosphorus doped amorphous silicon layer; 16-a polysilicon layer; 17-edge wrap plating; 18-phosphorus doped layer.
Detailed Description
Embodiments of the present application will be described in detail below with reference to examples, but those skilled in the art will appreciate that the following examples are only illustrative of the present application and should not be construed as limiting the scope of the present application. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
In the prior art, a chemical solvent is generally adopted to remove the plating, but the chemical solvent is easy to etch the PN junction while removing the plating. Based on this, the embodiments of the present application provide a method for removing edge wraparound plating of a solar cell and a method for manufacturing a solar cell, which can effectively remove the edge wraparound plating and do not easily damage a PN junction.
The following describes a method for removing the edge wrap-around plating of the solar cell and a method for manufacturing the solar cell in embodiments of the present application:
in a first aspect, an embodiment of the present application provides a method for removing edge wrap-plating of a solar cell, including:
s1, a boron doped layer 12 and a borosilicate glass layer 13 (see FIG. 2) are formed on the front surface of the N-type silicon wafer 11 (see FIG. 1) after texturing.
Illustratively, the textured N-type silicon wafer 11 is placed in a diffusion furnace for boron diffusion to form a boron doped layer 12 and a borosilicate glass layer 13 on the front surface of the N-type silicon wafer 11. When boron diffusion is performed in the diffusion furnace, a boron diffusion layer is also formed on the back surface of the N-type silicon wafer 11, and the boron diffusion layer on the back surface is removed by a single-sided etching cleaning machine after boron diffusion.
Optionally, the thickness of the N-type silicon wafer 11 is 160-180 μm, such as any one of 160 μm, 170 μm, and 180 μm or a range between any two. Alternatively, the resistivity of the N-type silicon wafer 11 is 0.5 to 10. omega. cm, for example, in a range of any one or between any two of 0.5. omega. cm, 1. omega. cm, 2. omega. cm, 4. omega. cm, 5. omega. cm, 7. omega. cm, 8. omega. cm and 10. omega. cm, and is illustratively 0.5 to 1.5. omega. cm.
Optionally, a boron source used for boron diffusion is boron trichloride, the boron diffusion temperature is 900-1050 ℃, and the time is 150-240 min. For example, the boron diffusion temperature is in a range between any one or any two of 900 ℃, 950 ℃, 1000 ℃, and 1050 ℃; the time is in a range between any one or any two of 150min, 170min, 180min, 200min, 220min, 230min, and 250 min.
Optionally, the square resistance value of the front boron doped layer 12 is 80-150 Ω/sqr, such as any one or a range between 80 Ω/sqr, 90 Ω/sqr, 100 Ω/sqr, 110 Ω/sqr, 120 Ω/sqr, 130 Ω/sqr, 140 Ω/sqr and 150 Ω/sqr. Illustratively, the sheet resistance of the front-side boron doped layer 12 is 100-130 Ω/sqr.
And S2, sequentially forming a tunneling oxide layer 14 and a phosphorus-doped amorphous silicon layer 15 on the back surface of the N-type silicon wafer 11 or forming a phosphorus-doped layer 18 on the back surface of the N-type silicon wafer 11, and performing edge-wrap plating on the phosphorus-doped amorphous silicon layer 15 or the phosphorus-doped layer 18 to the side edge of the N-type silicon wafer 11 and the surface edge of the borosilicate glass layer 13 to form an edge-wrap plating layer 17 (refer to FIGS. 3 and 4).
It should be noted that the method for removing the edge wrap-plating of the solar cell according to the embodiment of the present application is applicable to a Topcon cell and an N-type PERT cell. In the case of a Topcon cell, a tunnel oxide layer 14 and a phosphorus-doped amorphous silicon layer 15 are sequentially formed on the back surface of the N-type silicon wafer 11 (see fig. 3), and in the case of an N-type PERT cell, a phosphorus-doped layer 18 is formed on the back surface of the N-type silicon wafer 11 (see fig. 4).
When the battery is an N-type PERT battery, the phosphorus doped layer 18 is formed by phosphorus diffusion, and because the front surface of the N-type silicon wafer 11 is provided with the borosilicate glass layer 13, when the phosphorus doped layer 18 is coated to the side edge of the N-type silicon wafer 11 and the surface edge of the borosilicate glass layer 13 to form the edge coating layer 17, the borosilicate glass layer 13 can play a role in blocking so as to prevent phosphorus from entering the front surface of the N-type silicon wafer 11 to cause short circuit and electric leakage to form a reverse junction. When the cell is an N-type PERT cell, the main component of the edge wrap plating 17 is phosphorus silicon.
In addition, optionally, the material of the tunnel oxide layer 14 is silicon dioxide, and the formation method of the tunnel oxide layer 14 is thermal oxidation and HNO3Oxidation, O3Oxidation or atomic layer deposition. Optionally, the thickness of the tunnel oxide layer 14 is 0.5-3 nm, such as any one of 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm and 3nm or a range between any two. Illustratively, the tunnel oxide layer 14 has a thickness of 1-2 nm.
Optionally, the thickness of the phosphorus-doped amorphous silicon layer 15 is 50-150 nm, for example, any one of 50nm, 70nm, 90nm, 100nm, 120nm, 135nm and 150nm or a range between any two of them. Illustratively, the thickness of the phosphorus-doped amorphous silicon layer 15 is 50-110 nm.
In addition, the forming method of the phosphorus-doped amorphous silicon layer 15 can be a plasma enhanced chemical vapor deposition method, the deposition temperature is 300-600 ℃, the pressure is 100-300 Pa, the power is 3000-8000 w, the frequency is 20-60 KHZ, and the time is 600-2400 s.
The research of the applicant discovers that the winding plating formed in the process of forming the phosphorus-doped amorphous silicon layer 15 by adopting a plasma enhanced chemical vapor deposition method and using the process parameters of 300-600 ℃ of deposition temperature, 100-300 Pa of pressure, 3000-8000W of power, 20-60 KHZ of frequency and 600-2400 s of time is smaller, and the subsequent removal is facilitated. Illustratively, the deposition temperature is any one of, or a range between any two of, 300 ℃, 350 ℃, 400 ℃, 450 ℃, 500 ℃, 550 ℃ and 600 ℃. Illustratively, the pressure is any one of 100Pa, 150Pa, 200Pa, 250Pa, and 300Pa, or a range between any two. Illustratively, the power is any one of 3000W, 4000W, 5000W, 6000W, 7000W, and 8000W, or a range between any two. The frequency is in a range of any one or between any two of 20KHZ, 30KHZ, 40KHZ, 50KHZ, and 60 KHZ. The processing time is any one of 600s, 800s, 1000s, 1200s, 1500s, 1800s, 2000s, 2200s, and 2400s, or a range between any two. In addition, when the cell is a Topcon cell, the doping sources adopted for depositing the phosphorus-doped amorphous silicon layer by adopting the plasma enhanced chemical vapor deposition method in the embodiment of the application are phosphine and silane, wherein the flow rate of the phosphine is 200-1000 sccm, and the flow rate of the silane is 300-600 sccm.
In other embodiments, the phosphorus-doped amorphous silicon layer 15 may also be prepared by low-pressure chemical vapor deposition, which forms a relatively large amount of plating, and the plasma etching cannot achieve a complete etching process.
S3: the edge wrap plating 17 is etched away using a plasma gas etch (see fig. 5 and 6).
When the cell is an N-type PERT cell, the edge wrap plating layer 17 may be etched and removed by plasma gas etching after the edge wrap plating layer 17 is formed (see fig. 6).
When the cell is a Topcon cell, after the edge-winding plating layer 17 is formed, the phosphorus in the phosphorus-doped amorphous silicon layer 15 and the edge-winding plating layer 17 is activated at high temperature, the amorphous silicon is crystallized into polysilicon, the polysilicon layer 16 is formed on the surface of the tunnel oxide layer 14 in the process, and then the edge-winding plating layer 17 is etched and removed by using a plasma gas etching method (refer to fig. 5). It should be noted that, in this way, the components of the edge-surrounding plating layer 17 after the high-temperature activation step are also changed into phosphorus-containing polysilicon, and in the process of diffusing phosphorus in the phosphorus-doped amorphous silicon layer into the N-type silicon wafer 11, due to the presence of the borosilicate glass layer 13, the borosilicate glass layer 13 can play a role in blocking so as to prevent the phosphorus from entering the front surface of the N-type silicon wafer 11 to cause short-circuit leakage and form a reverse junction.
When the cell is a Topcon cell, the edge winding plating layer 17 can be etched and removed by using a plasma gas etching method after the edge winding plating layer 17 is formed, wherein the main component of the edge winding plating layer 17 is phosphorus-doped amorphous silicon, and then the phosphorus in the phosphorus-doped amorphous silicon layer 15 is activated at high temperature to crystallize the amorphous silicon into polysilicon. By adopting the method, impurities generated by plasma etching can be prevented from diffusing into the silicon wafer.
Optionally, the temperature of the high temperature activation is 800-900 ℃, for example, any one of 800 ℃, 820 ℃, 850 ℃, 880 ℃ and 900 ℃ or a range between any two.
In the research process, the applicant tries to remove the edge winding coating 17 by using a wet chemical etching method, the wet chemical etching method has the characteristic of isotropy, the part of the edge winding coating 17 wound on the front surface of the N-type silicon wafer 11 is small in size and generally smaller than 200 microns, when the edge winding coating 17 is removed by using a chemical solvent to perform the wet chemical etching, the borosilicate glass layer 13 and the PN junction on the front surface of the N-type silicon wafer 11 are easily damaged, the borosilicate glass layer 13 is damaged to cause phosphorus to diffuse into the N-type silicon wafer 11 to cause short circuit and electric leakage, and the PN junction is damaged to cause electric leakage, so that the battery efficiency is influenced. When the plasma gas etching method is adopted to remove the edge cladding layer 17, the etching is relatively accurate, and even if the cladding size of the front part of the N-type silicon wafer 11 is smaller, the PN junction is not easy to damage.
In the present embodiment, a plurality of pieces of N-type silicon wafers 11 having the edge-wise plating layer 17 formed thereon may be stacked and then plasma gas etched together. Wherein, the process of plasma gas etching can be carried out in a plasma etching machine.
In addition, after the edge surrounding plating layer 17 is removed by etching, a step of removing the borosilicate glass layer 13 is further included. Wherein the borosilicate glass layer 13 may be removed by an acid solution.
In one possible embodiment, the plasma gas used for plasma etching includes at least one of a fluorine-containing gas and a chlorine gas. That is, the plasma gas may include a fluorine-containing gas other than chlorine gas, may include chlorine gas other than fluorine-containing gas, and may include both fluorine-containing gas and chlorine gas.
When the cell is a Topcon cell or an N-type PERT cell, the components of the edge surrounding coating 17 are phosphorus silicon, and different plasma gases are adopted for etching, so that different etching rates are achieved. The plasma gas containing fluorine and the plasma gas containing chlorine form SiFx groups or SiClx groups on the surface of the edge-surrounding plating layer 17, and the SiFx groups and the SiClx groups have lower bonding energy compared with elemental silicon, so that the sputtering rate is higher during ion bombardment, and the edge-surrounding plating layer 17 can be removed better. Optionally, the flow rate of the fluorine-containing gas and the chlorine gas is 400-600sccm, such as any one of 400sccm, 450sccm, 500sccm, 550sccm, and 600sccm, or a range between any two thereof.
Illustratively, the fluorine-containing gas comprises CF4、C2F6、C3F8、C4F10、NF3And SF6At least one of (1).
Optionally, the fluorine-containing gas is CF4In use, CF4Plasma gas compared to C2F6、C3F8、C4F10、NF3And SF6Is safer and is not easy to burnExplosive and non-toxic, and, CF4Is more reasonable, thus, CF4The plasma gas is more suitable for industrial mass production.
Further, in a possible embodiment, when the plasma gas used only for the plasma gas etching includes at least one of a fluorine-containing gas and a chlorine gas, the plasma gas further includes O2，O2The etching speed can be accelerated. Illustratively, O2The flow rate of (b) is 40-100sccm, such as any one of 40sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm, and 100sccm, or a range between any two thereof.
Further, in a possible embodiment, the glow discharge power of the plasma gas etching process is 1000-2000 w, the reflection power is less than 200w, the glow discharge time is 900-1800 s, and the pressure of the plasma gas etching process is 20-60 Pa.
The applicant researches and discovers that the etching effect is reduced if the glow discharge power is too low in the plasma gas etching process, and the N-type silicon wafer 11 is easily damaged if the glow discharge power is too high, so that the glow discharge power is selected to be 1000-2000 w, for example, any one of 1000w, 1200w, 1400w, 1500w, 1700w, 1800w and 2000w or a range between any two of the 1000w, 1200w, 1400w, 1500w, 1700w, 1800w and 2000 w. In addition, the reflected power of the plasma gas etching process is less than 200w, and the smaller the reflected power is, the smaller the energy loss is. Illustratively, the reflected power of the plasma gas etching process is 5w, 10w, 20w, 30w, 50w, 80w, 100w, 120w, 150w, or 180 w.
Under the condition of the glow discharge power of 1000-2000 w, if the glow discharge time is too short, the edge surrounding plating layer 17 is not easy to be etched clean, and if the glow discharge time is too long, the N-type silicon wafer 11 is easy to be damaged, so the glow discharge time is selected to be 900-1800 s, for example, any one of 900s, 1000s, 1200s, 1400s, 1500s, 1600s and 1800s or the range between any two of the two.
Moreover, the applicant researches and discovers that the pressure of the plasma gas can influence the reaction speed of the plasma gas and the edge etching layer, and when the pressure of the plasma gas is 20-60Pa, the plasma gas and the edge winding layer 17 can be ensured to have a faster reaction speed. Illustratively, the pressure of the plasma gas is in a range of any one or between any two of 20Pa, 30Pa, 40Pa, 50Pa, and 60 Pa.
By simultaneously controlling the glow discharge power, the reflection power, the glow discharge time and the plasma gas pressure in the plasma gas etching process within the above ranges of the embodiment of the application, not only can the edge-winding coating 17 be quickly etched, but also the N-type silicon wafer 11 is not easily damaged.
In addition, optionally, the N-type silicon wafer 11 with the edge-wrapped coating 17 formed thereon is rotated during the plasma gas etching process so that the plasma gas is ejected to the edge-wrapped coating 17, wherein the rotating speed is 8-15 rmp. The N-type silicon wafer 11 with the edge-winding coating 17 is rotated by keeping the rotating speed of 8-15 rpm, so that the plasma gas and the edge-winding coating 17 can react more uniformly. The rotation speed is, for example, any one of 8rpm, 9rpm, 10rpm, 12rpm, 14rpm and 15rpm or a range between any two of them.
In a second aspect, an embodiment of the present application provides a method for manufacturing a solar cell, including the method for removing the edge wrap-around plating of the solar cell of the first aspect.
After the edge wrap plating layer 17 is removed, the processes such as plating, printing, and sintering may be performed subsequently.
The following describes the method for removing the edge wrap-around plating of the solar cell and the method for manufacturing the solar cell in detail with reference to the following embodiments.
Example 1
The embodiment provides a method for manufacturing a solar cell, which includes:
s1: and (3) performing texturing treatment on the N-type crystal silicon wafer, putting the textured N-type crystal silicon wafer into an industrial diffusion furnace, performing boron diffusion on a texturing surface, and forming a boron doping layer and a borosilicate glass layer on the front surface of the N-type crystal silicon wafer.
S2: and (4) depositing a tunneling oxide layer with the thickness of 1nm and a phosphorus-doped amorphous silicon layer with the thickness of 100nm on the back surface of the N-type crystal silicon wafer treated in the step (S1) in sequence, and in the process, winding and plating the phosphorus-doped amorphous silicon layer to the side edge of the N-type silicon wafer and the surface edge of the borosilicate glass layer to form an edge winding and plating layer. The phosphorus-doped amorphous silicon layer is formed by deposition through a plasma enhanced chemical vapor deposition method, wherein the deposition temperature is 500 ℃, the pressure is 200Pa, the power is 5000W, the frequency is 40KHZ, and the time is 1000 s.
And S3, activating and diffusing phosphorus in the phosphorus-doped amorphous silicon layer into the N-type silicon wafer at the high temperature of 850 ℃, wherein in the high-temperature activation process, the amorphous silicon is crystallized into polycrystalline silicon, so that a polycrystalline silicon layer is formed on the surface of the tunneling oxide layer.
S4, placing the N-type silicon wafer processed in the step S3 into a plasma etching machine, and adopting CF4And O2The plasma gas of (1) etching the edge wrap coating, wherein CF4At a flow rate of 500sccm, O2The flow rate of (2) is 60 sccm. The glow discharge power in the plasma gas etching process is 1200w, the glow discharge time is 1200s, the plasma gas pressure is 45Pa, and the reflection power is less than 200 w.
And S5, cleaning and removing the borosilicate glass layer.
S6: and depositing back silicon oxide, back aluminum oxide and back silicon nitride on the surface of the polycrystalline silicon layer in sequence, and depositing front silicon oxide, front aluminum oxide and front silicon nitride on the surface of the boron doped layer in sequence.
Example 2
This example provides a method for manufacturing a solar cell, which has the same steps as those of example 1, except that CF is used in example 24The plasma gas of (1) etching the edge wrap coating, wherein CF4The flow rate of (2) was 500sccm, and the glow discharge power, glow discharge time, plasma gas pressure and reflected power in the plasma gas etching process were the same as those in example 1.
Example 3
This example provides a method for manufacturing a solar cell, which has substantially the same steps as those of example 1, except that in example 3, a plasma gas of chlorine is used to etch an edge wrap plating layer.
Example 4
This example provides a method for manufacturing a solar cell, which has substantially the same steps as those of example 1, except that the glow discharge power in the plasma gas etching process of example 4 is 800w, and the glow discharge time is 2000 s.
Example 5
This example provides a method for manufacturing a solar cell, which has substantially the same steps as those of example 1, except that the glow discharge power in the plasma gas etching process of example 5 is 2000w, and the glow discharge time is 700 s.
Example 6
This example provides a method for manufacturing a solar cell, which has substantially the same steps as those in example 1, except that the glow discharge power in the plasma gas etching process in example 6 is 700w, the glow discharge time is 1000s, and the plasma gas pressure is 50 Pa.
Example 7
This example provides a method for manufacturing a solar cell, which has substantially the same steps as those of example 1, except that the glow discharge power in the plasma gas etching process of example 7 is 2000w, the glow discharge time is 1800s, and the plasma gas pressure is 20 Pa.
Example 8
This embodiment provides a method for manufacturing a solar cell, which has the same steps as those of embodiment 1, except that the plasma gas used is C3F8. Wherein, C3F8The flow rate of the plasma etching solution is 600sccm, the glow discharge power in the plasma gas etching process is 1200w, the glow discharge time is 1200s, the plasma gas pressure is 45Pa, and the reflection power is less than 200 w.
Comparative example 1
The embodiment provides a method for manufacturing a solar cell, which includes:
s01: and (3) performing texturing treatment on the N-type crystal silicon wafer, putting the textured N-type crystal silicon wafer into an industrial diffusion furnace, performing boron diffusion on a texturing surface, and forming a boron doping layer and a borosilicate glass layer on the front surface of the N-type crystal silicon wafer.
S02: and (4) depositing a tunneling oxide layer and a phosphorus-doped amorphous silicon layer on the back surface of the N-type silicon wafer treated in the step (S1) in sequence, and in the process, performing winding plating on the phosphorus-doped amorphous silicon layer to the surface of the borosilicate glass layer and forming an edge winding plating layer.
And S03, diffusing phosphorus in the phosphorus-doped amorphous silicon layer into the N-type crystal silicon wafer at high temperature of 850 ℃, and crystallizing the amorphous silicon in the phosphorus-doped amorphous silicon layer into polycrystalline silicon in the high-temperature activation process so as to form a polycrystalline silicon layer on the surface of the tunneling oxide layer.
And S04, cleaning and removing the borosilicate glass layer.
S05: and depositing back silicon oxide, back aluminum oxide and back silicon nitride on the surface of the polycrystalline silicon layer in sequence, and depositing front silicon oxide, front aluminum oxide and front silicon nitride on the surface of the boron doped layer in sequence.
Test example 1
The solar cells prepared in examples 1 to 8 and comparative example 1 were tested for electrical properties, and the results are reported in table 1.
TABLE 1 test results of electrical properties of solar cells
Figure BDA0002892768540000121
Comparing the results of the examples 1 to 8 with the results of the comparative example 1, the leakage current degree of the examples 1 to 8 is smaller than that of the comparative example 1, wherein the best effect of the example 1 is shown, which shows that the parallel resistance of the solar cell prepared by the method for removing the edge plating around the edge of the solar cell is greatly improved, and the leakage current is obviously reduced. It is found by comparing example 1 with example 2 that example 2 has a slow reaction rate without oxygen, incomplete etching, and a larger degree of leakage than example 1. By comparing example 1, example 3 and example 8, it is found that the plasma gas used in example 3 and example 8 is different from example 1, and the degree of leakage is greater in example 3 and example 8 than in example 1. In addition, the glow discharge power of the embodiment 4 and the embodiment 6 is smaller than that of the embodiment 1, the gas reaction energy is insufficient, the etching is incomplete, and the electric leakage degree is larger than that of the embodiment 1; the glow discharge power of the embodiment 5 and the embodiment 7 is larger than that of the embodiment 1, the N-type silicon wafer is damaged due to excessive energy, the open-circuit voltage and the short-circuit current are both reduced, and the battery efficiency is influenced.
The conclusion can be drawn by combining the above experiments: CF is used as the reaction gas4And O2The flow rates are respectively 500sccm and 60sccm, the glow power is 1200w, the time is 1200s, the pressure is 45pa, the optimal conditions are adopted, the leakage current is the lowest, and the damage to the battery is the smallest. The N-type silicon wafer is damaged due to excessive power, and the conversion efficiency is influenced. The power is too low, the energy required by the reaction is insufficient, the edge surrounding coating cannot be completely removed, and electric leakage still exists. Although other reaction gases also have etching effect, the etching effect is far less than that of CF4Adding O2The ideal situation is that.
The foregoing is illustrative of the present application and is not to be construed as limiting thereof, as numerous modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A method for removing edge wrap-around plating of a solar cell is characterized by comprising the following steps:
forming a boron doped layer and a borosilicate glass layer on the front surface of the textured N-type silicon wafer;
sequentially forming a tunneling oxide layer and a phosphorus-doped amorphous silicon layer on the back of the N-type silicon wafer or forming a phosphorus-doped layer on the back of the N-type silicon wafer, wherein the phosphorus-doped amorphous silicon layer or the phosphorus-doped layer is coated to the side edge of the N-type silicon wafer and the surface edge of the borosilicate glass layer to form an edge coating layer;
and etching and removing the edge surrounding coating by adopting a plasma gas etching method.
2. The method for removing the solar cell edge wrap-plating according to claim 1, wherein the plasma gas used for the plasma gas etching includes at least one of a fluorine-containing gas and a chlorine gas; optionally, the flow rates of the fluorine-containing gas and the chlorine gas are 400-600 sccm.
3. The method of claim 2, wherein the fluorine-containing gas comprises CF4、C2F6、C3F8、C4F10、NF3And SF6At least one of (1).
4. The method of claim 2, wherein the fluorine-containing gas is CF4。
5. The method of removing edge wrap plating of a solar cell according to any of claims 2-4, wherein the plasma gas further comprises O2(ii) a Alternatively, the O is2The flow rate of (A) is 40-100 sccm.
6. The method for removing the solar cell edge wrap-around plating according to any one of claims 1 to 4, wherein the glow discharge power in the plasma gas etching process is 700-2000w, the reflection power is less than 200w, the glow discharge time is 700-1800s, and the pressure of the plasma gas in the plasma gas etching process is 20-50 Pa.
7. The method for removing the edge wrap-around plating of the solar cell according to any one of claims 1 to 4, wherein the N-type silicon wafer on which the edge wrap-around plating is formed is rotated during the plasma gas etching so that the plasma gas is ejected to the edge wrap-around plating, wherein the rotation speed is 10 rmp.
8. The method for removing the solar cell edge wraparound plating according to any one of claims 1 to 4, wherein after the tunneling oxide layer and the phosphorus-doped amorphous silicon layer are sequentially formed on the back surface of the N-type silicon wafer, phosphorus in the phosphorus-doped amorphous silicon layer and the edge wraparound plating layer is activated at high temperature, the amorphous silicon is crystallized into polycrystalline silicon, a polycrystalline silicon layer is formed on the surface of the tunneling oxide layer in the process, and then the edge wraparound plating layer is etched and removed by the plasma gas etching method.
9. The method for removing the edge wrap-around plating of the solar cell as claimed in any one of claims 1 to 4, wherein the method for forming the phosphorus-doped amorphous silicon layer on the back surface of the N-type silicon wafer comprises the following steps: the plasma enhanced chemical vapor deposition method comprises the steps of depositing at the temperature of 300-600 ℃, under the pressure of 100-300 Pa, at the power of 3000-8000 w, at the frequency of 20-60 KHZ and for the time of 600-2400 s.
10. A method for manufacturing a solar cell, comprising the method for removing the edge wrap plating of the solar cell according to any one of claims 1 to 9.
CN202110032636.4A 2021-01-11 2021-01-11 Method for removing edge wrap plating of solar cell and method for manufacturing solar cell Pending CN112768562A (en)

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